yosys.git
3 years agosv: allow typenames as function return types
Zachary Snow [Thu, 18 Mar 2021 17:38:25 +0000 (13:38 -0400)]
sv: allow typenames as function return types

3 years agoMerge pull request #2681 from msinger/fix-issue2606
Miodrag Milanović [Fri, 19 Mar 2021 07:47:07 +0000 (08:47 +0100)]
Merge pull request #2681 from msinger/fix-issue2606

Fix check for bad std::regex

3 years agoverilog: rebuild user_type_stack from globals before parsing file
Xiretza [Tue, 16 Mar 2021 15:42:14 +0000 (16:42 +0100)]
verilog: rebuild user_type_stack from globals before parsing file

This was actually a ticking UB bomb: after running the parser, the type
maps contain pointers to children of the current AST, which is
recursively deleted after the pass has executed. This leaves the
pointers in user_type_stack dangling, which just happened to never be a
problem due to another bug that causes typedefs from higher-level type
maps to never be considered.

Rebuilding the type stack from the design's globals ensures the AstNode
pointers are valid.

3 years agoAdd simple CI using github actions.
Marcelina Kościelnicka [Wed, 17 Mar 2021 18:32:50 +0000 (19:32 +0100)]
Add simple CI using github actions.

3 years agomodtools: fix use-after-free of cell pointers in ModWalker
Xiretza [Mon, 15 Mar 2021 14:55:18 +0000 (15:55 +0100)]
modtools: fix use-after-free of cell pointers in ModWalker

cell_inputs and cell_outputs retain cell pointers as their keys across
invocations of setup(), which may however be invalidated in the meantime
(as happens in e.g. passes/opt/share.cc:1432). A later rehash of the
dicts (caused by inserting in ModWalker::add_wire()) will cause them to
be dereferenced.

3 years agoquicklogic: PolarPro 3 support
Lofty [Wed, 17 Mar 2021 02:34:30 +0000 (02:34 +0000)]
quicklogic: PolarPro 3 support

Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
3 years agoast: Use better parameter serialization for paramod names.
Marcelina Kościelnicka [Wed, 17 Mar 2021 17:30:49 +0000 (18:30 +0100)]
ast: Use better parameter serialization for paramod names.

Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.

3 years agoFix check for bad std::regex (fixes #2606)
Michael Singer [Wed, 17 Mar 2021 22:22:50 +0000 (23:22 +0100)]
Fix check for bad std::regex (fixes #2606)

3 years agoBlackbox all whiteboxes after synthesis
gatecat [Wed, 17 Mar 2021 12:16:53 +0000 (12:16 +0000)]
Blackbox all whiteboxes after synthesis

This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
3 years agobugpoint: add runner option
Zachary Snow [Tue, 16 Mar 2021 14:54:22 +0000 (10:54 -0400)]
bugpoint: add runner option

3 years agosv: carry over global typedefs from previous files
Zachary Snow [Tue, 16 Mar 2021 15:06:40 +0000 (11:06 -0400)]
sv: carry over global typedefs from previous files

This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.

3 years agoverilog: fix buf/not primitives with multiple outputs
Xiretza [Tue, 16 Mar 2021 23:18:36 +0000 (00:18 +0100)]
verilog: fix buf/not primitives with multiple outputs

From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.

3 years agoblackbox: Include whiteboxed modules
gatecat [Wed, 17 Mar 2021 12:06:09 +0000 (12:06 +0000)]
blackbox: Include whiteboxed modules

Signed-off-by: gatecat <gatecat@ds0.me>
3 years agoReplace assert in get_reference with more useful error message
Lofty [Wed, 17 Mar 2021 02:43:25 +0000 (02:43 +0000)]
Replace assert in get_reference with more useful error message

3 years agoverilog: support module scope identifiers in parametric modules
Zachary Snow [Thu, 4 Mar 2021 19:07:56 +0000 (14:07 -0500)]
verilog: support module scope identifiers in parametric modules

3 years agojson: Add support for memories.
Marcelina Kościelnicka [Tue, 9 Mar 2021 19:42:14 +0000 (20:42 +0100)]
json: Add support for memories.

Previously, memories were silently discarded by the JSON backend, making
round-tripping modules with them crash.

Since there are already some users using JSON to implement custom
external passes that use memories (and infer width/size from memory
ports), let's fix this by just making JSON backend and frontend support
memories as first-class objects.

Processes are still not supported, and will now cause a hard error.

Fixes #1908.

3 years agoproc_arst: Add special-casing of clock signal in conditionals.
Marcelina Kościelnicka [Fri, 12 Mar 2021 16:05:39 +0000 (17:05 +0100)]
proc_arst: Add special-casing of clock signal in conditionals.

The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.

3 years agoopt_clean: Remove init attribute bits together with removed DFFs.
Marcelina Kościelnicka [Tue, 9 Mar 2021 20:32:16 +0000 (21:32 +0100)]
opt_clean: Remove init attribute bits together with removed DFFs.

Fixes #2546.

3 years agortlil: Disallow 0-width chunks in SigSpec.
Marcelina Kościelnicka [Tue, 9 Mar 2021 01:54:56 +0000 (02:54 +0100)]
rtlil: Disallow 0-width chunks in SigSpec.

Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.

Also fix another minor issue with possible non-canonical SigSpec.

Fixes #2623.

3 years agoMerge pull request #2658 from zachjs/parameters-across-files
whitequark [Sun, 14 Mar 2021 15:02:16 +0000 (15:02 +0000)]
Merge pull request #2658 from zachjs/parameters-across-files

sv: allow globals in one file to depend on globals in another

3 years agosv: allow globals in one file to depend on globals in another
Zachary Snow [Thu, 11 Mar 2021 18:05:04 +0000 (13:05 -0500)]
sv: allow globals in one file to depend on globals in another

This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.

3 years agoMerge pull request #2653 from zachjs/global-parameter
whitequark [Fri, 12 Mar 2021 01:34:06 +0000 (01:34 +0000)]
Merge pull request #2653 from zachjs/global-parameter

verilog: disallow overriding global parameters

3 years agoMerge pull request #2642 from whitequark/cxxrtl-noproc-fixes
whitequark [Thu, 11 Mar 2021 20:01:10 +0000 (20:01 +0000)]
Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes

CXXRTL: some -noproc fixes

3 years agoverilog: disallow overriding global parameters
Zachary Snow [Thu, 11 Mar 2021 16:49:15 +0000 (11:49 -0500)]
verilog: disallow overriding global parameters

It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.

3 years agoAdd _pm.h files to GENLIST, fixes vcxsrc target
Miodrag Milanovic [Thu, 11 Mar 2021 14:56:32 +0000 (15:56 +0100)]
Add _pm.h files to GENLIST, fixes vcxsrc target

3 years agoReplace assert in xaiger with more useful error message
Dan Ravensloft [Wed, 10 Mar 2021 19:31:55 +0000 (19:31 +0000)]
Replace assert in xaiger with more useful error message

3 years agoMerge pull request #2643 from zachjs/fix-param-no-default-log
whitequark [Tue, 9 Mar 2021 00:36:03 +0000 (16:36 -0800)]
Merge pull request #2643 from zachjs/fix-param-no-default-log

Fix param without default log line

3 years agoBump version
Marcelina Kościelnicka [Mon, 8 Mar 2021 19:18:11 +0000 (20:18 +0100)]
Bump version

3 years agomemory_dff: Remove now-useless write port handling. working-ls180
Marcelina Kościelnicka [Tue, 23 Feb 2021 18:42:51 +0000 (19:42 +0100)]
memory_dff: Remove now-useless write port handling.

3 years agoverilog: Use proc memory writes in the frontend.
Marcelina Kościelnicka [Tue, 23 Feb 2021 15:48:29 +0000 (16:48 +0100)]
verilog: Use proc memory writes in the frontend.

3 years agoAdd support for memory writes in processes.
Marcelina Kościelnicka [Mon, 22 Feb 2021 23:21:46 +0000 (00:21 +0100)]
Add support for memory writes in processes.

3 years agosim: Avoid a crash on empty cell connection.
Marcelina Kościelnicka [Mon, 1 Mar 2021 19:01:39 +0000 (20:01 +0100)]
sim: Avoid a crash on empty cell connection.

Fixes #2513.

3 years agoproc_dff: Fix emitted FF when a register is not assigned in async reset
Marcelina Kościelnicka [Sat, 6 Mar 2021 02:59:03 +0000 (03:59 +0100)]
proc_dff: Fix emitted FF when a register is not assigned in async reset

Fixes #2619.

3 years agomemory_dff: Remove code looking for $mux cells.
Marcelina Kościelnicka [Fri, 5 Mar 2021 00:23:25 +0000 (01:23 +0100)]
memory_dff: Remove code looking for $mux cells.

This job is now performed by `opt_dff`, which runs before this pass.

3 years agotests/bram: Do not generate write address collisions.
Marcelina Kościelnicka [Thu, 4 Mar 2021 16:55:57 +0000 (17:55 +0100)]
tests/bram: Do not generate write address collisions.

These have no defined semantics, making the tests non-deterministic.

3 years agoFix param without default log line
Zachary Snow [Sun, 7 Mar 2021 21:06:25 +0000 (16:06 -0500)]
Fix param without default log line

3 years agoReplace assert in abc9_ops with more useful error message
Dan Ravensloft [Fri, 5 Mar 2021 22:13:15 +0000 (22:13 +0000)]
Replace assert in abc9_ops with more useful error message

3 years agocxxrtl: don't assert on edge sync rules tied to a constant.
whitequark [Sun, 7 Mar 2021 14:29:30 +0000 (14:29 +0000)]
cxxrtl: don't assert on edge sync rules tied to a constant.

These are commonly the result of tying an async reset to an inactive
level.

3 years agocxxrtl: allow `always` sync rules in debug_eval.
whitequark [Sun, 7 Mar 2021 14:28:45 +0000 (14:28 +0000)]
cxxrtl: allow `always` sync rules in debug_eval.

These can be produced from `always @*` processes, if `-noproc`
is used.

3 years agoMerge pull request #2626 from zachjs/param-no-default
whitequark [Sun, 7 Mar 2021 13:48:03 +0000 (05:48 -0800)]
Merge pull request #2626 from zachjs/param-no-default

sv: support for parameters without default values

3 years agoMerge pull request #2632 from zachjs/width-limit
whitequark [Sun, 7 Mar 2021 11:45:41 +0000 (03:45 -0800)]
Merge pull request #2632 from zachjs/width-limit

verilog: impose limit on maximum expression width

3 years agosv: fix some edge cases for unbased unsized literals
Zachary Snow [Wed, 3 Mar 2021 19:36:19 +0000 (14:36 -0500)]
sv: fix some edge cases for unbased unsized literals

- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`

3 years agoproc_clean: Fix empty case removal conditions.
Marcelina Kościelnicka [Sat, 6 Mar 2021 10:05:57 +0000 (11:05 +0100)]
proc_clean: Fix empty case removal conditions.

Fixes #2639.

3 years agoRemove a few functions that, in fact, did not exist in the first place.
Marcelina Kościelnicka [Sat, 6 Mar 2021 00:18:24 +0000 (01:18 +0100)]
Remove a few functions that, in fact, did not exist in the first place.

3 years agoReplace assert in addModule with more useful error message
Dan Ravensloft [Fri, 5 Mar 2021 21:45:11 +0000 (21:45 +0000)]
Replace assert in addModule with more useful error message

3 years agoMerge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
whitequark [Fri, 5 Mar 2021 13:30:19 +0000 (05:30 -0800)]
Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr

cxxrtl: follow aliases to outlines when emitting $memrd.ADDR

3 years agoMerge pull request #2634 from whitequark/cxxrtl-debug-wire-types
whitequark [Fri, 5 Mar 2021 12:57:22 +0000 (04:57 -0800)]
Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types

cxxrtl: add pass debug flag to show assigned wire types

3 years agoMerge pull request #2633 from whitequark/cxxrtl-no-top
whitequark [Fri, 5 Mar 2021 12:14:07 +0000 (04:14 -0800)]
Merge pull request #2633 from whitequark/cxxrtl-no-top

cxxrtl: don't crash on empty designs

3 years agocxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
whitequark [Fri, 5 Mar 2021 12:08:48 +0000 (12:08 +0000)]
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.

3 years agocxxrtl: add pass debug flag to show assigned wire types.
whitequark [Fri, 5 Mar 2021 11:44:39 +0000 (11:44 +0000)]
cxxrtl: add pass debug flag to show assigned wire types.

Refs #2543.

3 years agocxxrtl: don't crash on empty designs.
whitequark [Fri, 5 Mar 2021 11:05:19 +0000 (11:05 +0000)]
cxxrtl: don't crash on empty designs.

3 years agoverilog: impose limit on maximum expression width
Zachary Snow [Thu, 4 Mar 2021 20:08:16 +0000 (15:08 -0500)]
verilog: impose limit on maximum expression width

Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.

3 years agoUpdate command-reference-manual.tex
Claire Xen [Thu, 4 Mar 2021 15:45:21 +0000 (16:45 +0100)]
Update command-reference-manual.tex

3 years agoUpdate README
Claire Xen [Thu, 4 Mar 2021 15:43:30 +0000 (16:43 +0100)]
Update README

3 years agosv: support for parameters without default values
Zachary Snow [Tue, 2 Mar 2021 15:43:53 +0000 (10:43 -0500)]
sv: support for parameters without default values

- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations

3 years agoMerge pull request #2620 from zachjs/port-int-types
whitequark [Tue, 2 Mar 2021 06:46:07 +0000 (22:46 -0800)]
Merge pull request #2620 from zachjs/port-int-types

verilog: fix sizing of ports with int types in module headers

3 years agoverilog: fix sizing of ports with int types in module headers
Zachary Snow [Mon, 1 Mar 2021 18:31:25 +0000 (13:31 -0500)]
verilog: fix sizing of ports with int types in module headers

Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.

3 years agoBump version
Marcelina Kościelnicka [Mon, 1 Mar 2021 18:33:05 +0000 (19:33 +0100)]
Bump version

3 years agoverilog: fix handling of nested ifdef directives
Zachary Snow [Thu, 25 Feb 2021 20:53:55 +0000 (15:53 -0500)]
verilog: fix handling of nested ifdef directives

- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else

3 years agoSet aside extraneous tests in simple_abc9 test suite
Zachary Snow [Wed, 10 Feb 2021 00:58:15 +0000 (19:58 -0500)]
Set aside extraneous tests in simple_abc9 test suite

New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.

3 years agoMerge pull request #2523 from tomverbeure/define_synthesis
Claire Xen [Mon, 1 Mar 2021 17:00:48 +0000 (18:00 +0100)]
Merge pull request #2523 from tomverbeure/define_synthesis

Add -nosynthesis flag for read_verilog command

3 years agoMerge pull request #2524 from bkbncn/patch-1
Claire Xen [Mon, 1 Mar 2021 16:46:33 +0000 (17:46 +0100)]
Merge pull request #2524 from bkbncn/patch-1

Add boost-python3

3 years agoMerge pull request #2617 from RobertBaruch/doc
whitequark [Mon, 1 Mar 2021 16:10:32 +0000 (08:10 -0800)]
Merge pull request #2617 from RobertBaruch/doc

RTLIL Documentation: switch in process is optional

3 years agoMerge pull request #2615 from zachjs/genrtlil-conflict
whitequark [Mon, 1 Mar 2021 16:10:19 +0000 (08:10 -0800)]
Merge pull request #2615 from zachjs/genrtlil-conflict

genrtlil: improve name conflict error messaging

3 years agoMerge pull request #2618 from zachjs/int-types
whitequark [Mon, 1 Mar 2021 04:29:44 +0000 (20:29 -0800)]
Merge pull request #2618 from zachjs/int-types

sv: extended support for integer types

3 years agosv: extended support for integer types
Zachary Snow [Sun, 28 Feb 2021 20:49:16 +0000 (15:49 -0500)]
sv: extended support for integer types

- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths

3 years agoRTLIL Documentation: switch in process is optional
Robert Baruch [Sat, 27 Feb 2021 17:58:03 +0000 (09:58 -0800)]
RTLIL Documentation: switch in process is optional

3 years agoUpdate issue_template.md
Claire Xen [Sat, 27 Feb 2021 15:52:30 +0000 (16:52 +0100)]
Update issue_template.md

3 years agogenrtlil: improve name conflict error messaging
Zachary Snow [Fri, 26 Feb 2021 23:08:23 +0000 (18:08 -0500)]
genrtlil: improve name conflict error messaging

3 years agoAdd tests for $countbits
Michael Singer [Thu, 25 Feb 2021 00:21:36 +0000 (01:21 +0100)]
Add tests for $countbits

3 years agoImplement $countones, $isunknown and $onehot{,0}
Michael Singer [Tue, 23 Feb 2021 00:19:06 +0000 (01:19 +0100)]
Implement $countones, $isunknown and $onehot{,0}

3 years agoImplement $countbits function
Michael Singer [Mon, 22 Feb 2021 23:55:55 +0000 (00:55 +0100)]
Implement $countbits function

3 years agoExtend simplify() recursion warning
Zachary Snow [Thu, 25 Feb 2021 21:02:55 +0000 (16:02 -0500)]
Extend simplify() recursion warning

3 years agoBump version
Marcelina Kościelnicka [Thu, 25 Feb 2021 23:24:33 +0000 (00:24 +0100)]
Bump version

3 years agoMerge pull request #2554 from hzeller/master
whitequark [Thu, 25 Feb 2021 21:54:16 +0000 (13:54 -0800)]
Merge pull request #2554 from hzeller/master

Fix digit-formatting calculation for small numbers.

3 years agobtor, smt2, smv: Add a hint on how to deal with funny FF types.
Marcelina Kościelnicka [Tue, 23 Feb 2021 11:06:21 +0000 (12:06 +0100)]
btor, smt2, smv: Add a hint on how to deal with funny FF types.

3 years agoFix handling of unique/unique0/priority cases in the frontend.
Marcelina Kościelnicka [Mon, 22 Feb 2021 18:19:42 +0000 (19:19 +0100)]
Fix handling of unique/unique0/priority cases in the frontend.

Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.

3 years agoExtend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off...
TimRudy [Wed, 24 Feb 2021 20:48:15 +0000 (15:48 -0500)]
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566)

3 years agoMerge pull request #2607 from zachjs/logger-error-atexit
whitequark [Wed, 24 Feb 2021 19:12:56 +0000 (19:12 +0000)]
Merge pull request #2607 from zachjs/logger-error-atexit

Fix double-free on unmatched logger error pattern

3 years agoFix double-free on unmatched logger error pattern
Zachary Snow [Wed, 24 Feb 2021 01:39:13 +0000 (20:39 -0500)]
Fix double-free on unmatched logger error pattern

When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.

3 years agoAdd tests for some common techmap files.
Marcelina Kościelnicka [Tue, 23 Feb 2021 20:23:26 +0000 (21:23 +0100)]
Add tests for some common techmap files.

3 years agoFix syntax error in adff2dff.v
Marcelina Kościelnicka [Tue, 23 Feb 2021 11:12:37 +0000 (12:12 +0100)]
Fix syntax error in adff2dff.v

Fixes #2600.

3 years agofrontend: Make helper functions for printing locations.
Marcelina Kościelnicka [Tue, 23 Feb 2021 18:22:53 +0000 (19:22 +0100)]
frontend: Make helper functions for printing locations.

3 years agoMerge pull request #2594 from zachjs/func-arg-width
whitequark [Tue, 23 Feb 2021 21:46:16 +0000 (21:46 +0000)]
Merge pull request #2594 from zachjs/func-arg-width

verilog: fix sizing of constant args for tasks/functions

3 years agoint -> bool
Robert Baruch [Mon, 22 Feb 2021 04:00:31 +0000 (20:00 -0800)]
int -> bool

3 years agoAdds is_wire to SigBit and SigChunk
Robert Baruch [Sat, 20 Feb 2021 19:46:30 +0000 (11:46 -0800)]
Adds is_wire to SigBit and SigChunk

Useful for PYOSYS because Python can't easily check wire against NULL.

3 years agomachxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
William D. Jones [Sun, 21 Feb 2021 14:14:37 +0000 (09:14 -0500)]
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.

3 years agomachxo2: Update tribuf test to reflect active-low OE.
William D. Jones [Wed, 10 Feb 2021 23:50:17 +0000 (18:50 -0500)]
machxo2: Update tribuf test to reflect active-low OE.

3 years agomachxo2: Add experimental status to help.
William D. Jones [Mon, 8 Feb 2021 22:31:58 +0000 (17:31 -0500)]
machxo2: Add experimental status to help.

3 years agomachxo2: Add DCCA and DCMA blackbox primitives.
William D. Jones [Mon, 1 Feb 2021 04:57:13 +0000 (23:57 -0500)]
machxo2: Add DCCA and DCMA blackbox primitives.

3 years agomachxo2: Fix reversed interpretation of REG_SD config bits.
William D. Jones [Mon, 1 Feb 2021 00:05:15 +0000 (19:05 -0500)]
machxo2: Fix reversed interpretation of REG_SD config bits.

3 years agomachxo2: Tristate is active-low.
William D. Jones [Sun, 31 Jan 2021 16:33:20 +0000 (11:33 -0500)]
machxo2: Tristate is active-low.

3 years agomachxo2: Fix typos in FACADE_FF sim model.
William D. Jones [Sun, 31 Jan 2021 04:55:00 +0000 (23:55 -0500)]
machxo2: Fix typos in FACADE_FF sim model.

3 years agomachxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
William D. Jones [Fri, 29 Jan 2021 23:14:13 +0000 (18:14 -0500)]
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.

3 years agomachxo2: Improve help_mode output in synth_machxo2.
William D. Jones [Sun, 13 Dec 2020 05:34:01 +0000 (00:34 -0500)]
machxo2: Improve help_mode output in synth_machxo2.

3 years agomachxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO...
William D. Jones [Sat, 12 Dec 2020 23:09:52 +0000 (18:09 -0500)]
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells.

3 years agomachxo2: Add missing OSCH oscillator primitive.
William D. Jones [Tue, 8 Dec 2020 03:29:36 +0000 (22:29 -0500)]
machxo2: Add missing OSCH oscillator primitive.

3 years agomachxo2: Add believed-to-be-correct tribuf test.
William D. Jones [Fri, 27 Nov 2020 03:34:46 +0000 (22:34 -0500)]
machxo2: Add believed-to-be-correct tribuf test.

3 years agomachxo2: Add passing fsm, mux, and shifter tests.
William D. Jones [Fri, 27 Nov 2020 03:30:48 +0000 (22:30 -0500)]
machxo2: Add passing fsm, mux, and shifter tests.

3 years agomachxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.
William D. Jones [Fri, 27 Nov 2020 02:58:20 +0000 (21:58 -0500)]
machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.