Kevin Lim [Tue, 28 Nov 2006 16:41:17 +0000 (11:41 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
--HG--
extra : convert_revision :
ffc7931d7da153b421b3c838a0968e484fd182ec
Kevin Lim [Tue, 28 Nov 2006 16:41:08 +0000 (11:41 -0500)]
Remove assertion. It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting.
--HG--
extra : convert_revision :
020a9799cd7177fdb85a767701d6fcb8cf018827
Steve Reinhardt [Mon, 27 Nov 2006 07:16:24 +0000 (02:16 -0500)]
Add TRACING_ON setting for m5.prof.
--HG--
extra : convert_revision :
ebda49bff30d76d3209acce55458d3f4e29594d3
Kevin Lim [Sun, 26 Nov 2006 16:46:58 +0000 (11:46 -0500)]
Include check for making sure caches are enabled.
--HG--
extra : convert_revision :
e3902b065db524ebe5bf762e44a840133ccb8d75
Steve Reinhardt [Fri, 24 Nov 2006 17:32:33 +0000 (12:32 -0500)]
Add no-op versions of ivlb and ivle back in for backwards compatibility.
--HG--
extra : convert_revision :
383b72c130b20f3d7cde4e08fa36a481f3c0bf7c
Steve Reinhardt [Thu, 23 Nov 2006 15:46:24 +0000 (10:46 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
154bc605c62b1e51c32e65916d4c2eda3a3f22fd
Ron Dreslinski [Thu, 23 Nov 2006 01:20:38 +0000 (20:20 -0500)]
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode
src/mem/bus.cc:
Fix a comment to make sense
src/mem/cache/cache_impl.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
Update ref's for writeback changes
--HG--
extra : convert_revision :
937febd577b16b7fd97a5a68acaf53541828a251
Kevin Lim [Mon, 20 Nov 2006 16:44:27 +0000 (11:44 -0500)]
Fix typo.
--HG--
extra : convert_revision :
2dd830c6b3b5df894608b7596250b0181a3dfdf0
Steve Reinhardt [Sun, 19 Nov 2006 23:38:12 +0000 (18:38 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
c2b7784377d85df5b8ee39c891cd3da9907410d8
Kevin Lim [Sun, 19 Nov 2006 22:43:03 +0000 (17:43 -0500)]
Update Virtual and Physical ports.
src/cpu/o3/alpha/cpu_impl.hh:
Handle the PhysicalPort and VirtualPort in the ThreadState.
src/cpu/o3/cpu.cc:
Initialize the thread context.
src/cpu/o3/thread_context.hh:
Add new function to initialize thread context.
src/cpu/o3/thread_context_impl.hh:
Use code now put into function.
src/cpu/simple_thread.cc:
Move code to ThreadState and use the new helper function.
src/cpu/simple_thread.hh:
Remove init() in this derived class; use init() from ThreadState base class.
src/cpu/thread_state.cc:
Move setting up of Physical and Virtual ports here. Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU.
src/cpu/thread_state.hh:
Update functions.
--HG--
extra : convert_revision :
ff254715ef0b259dc80d08f13543b63e4024ca8d
Ron Dreslinski [Sat, 18 Nov 2006 03:01:18 +0000 (22:01 -0500)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
1fc55d7d5707bb7c63790aab306ca5ea8ade5fab
Ron Dreslinski [Sat, 18 Nov 2006 02:55:28 +0000 (21:55 -0500)]
Make an initialization pass for the thread context and set the [phys,virt]Port correctly
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Call the thread context initialization
--HG--
extra : convert_revision :
d7dc2a8b893dc670077b7f6150d4b710a1778620
Nathan Binkert [Thu, 16 Nov 2006 21:18:21 +0000 (13:18 -0800)]
add warn_once which will print any given warning message
only once.
--HG--
extra : convert_revision :
b64bb495c1bd0c4beb3db6ca28fad5af4d05ef8e
Nathan Binkert [Thu, 16 Nov 2006 21:10:38 +0000 (13:10 -0800)]
Implement a single config file to encompass all of the SPEC
CPU2000 stuff, and use it in all of the tests that currently
use SPEC
--HG--
extra : convert_revision :
8cd26a597e51a90b6d2810d344a075f5aa0f011b
Nathan Binkert [Thu, 16 Nov 2006 21:08:29 +0000 (13:08 -0800)]
implement RUSAGE_CHILDREN for getrusage since it's trivial
--HG--
extra : convert_revision :
bc12b3b2e9ee02f42c437cbc20680ea00e19a801
Nathan Binkert [Thu, 16 Nov 2006 20:43:11 +0000 (12:43 -0800)]
Implement current working directory for LiveProcesses
--HG--
extra : convert_revision :
a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
Ron Dreslinski [Wed, 15 Nov 2006 23:22:15 +0000 (18:22 -0500)]
Add L2 cache option to fs.py --l2cache
--HG--
extra : convert_revision :
5bdd1129c3b23e91d441e7b83f6a824ef7740fab
Ron Dreslinski [Tue, 14 Nov 2006 23:41:37 +0000 (18:41 -0500)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
8d61b474428d494b1a5382e4cf95934ad54e35dd
Kevin Lim [Tue, 14 Nov 2006 22:22:32 +0000 (17:22 -0500)]
Various fixes to delete packet and request a little better.
src/cpu/simple/timing.cc:
Various updates for deleting requests more properly.
The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed. This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.
--HG--
extra : convert_revision :
c7cf114bb1ff3cdaa7b0a40ed4c5302dc9d3a522
Ron Dreslinski [Tue, 14 Nov 2006 22:19:57 +0000 (17:19 -0500)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
b216fcdb2632dce68ac18932b0c13408eb1aeaf4
Ron Dreslinski [Tue, 14 Nov 2006 22:15:05 +0000 (17:15 -0500)]
Fix bugs around uni-coherence invalidates being propogated properly.
src/mem/bus.cc:
Make it so that invalidates being sent from the responder up don't call the responder
but they should also not Panic.
src/mem/packet.hh:
If we don't have data in the packet, don't call deleteData:
Example: InvalidateRequests never have data.
--HG--
extra : convert_revision :
18766bc9f3bb4d852ac651d094254d347abd1634
Lisa Hsu [Tue, 14 Nov 2006 18:00:05 +0000 (13:00 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
6abd919711966eaaa157483557a3f953b02dde01
Lisa Hsu [Tue, 14 Nov 2006 17:59:57 +0000 (12:59 -0500)]
interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
src/arch/sparc/interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
--HG--
extra : convert_revision :
5f469d0cf897479b42703104cd801a8ef923fcae
Ron Dreslinski [Tue, 14 Nov 2006 15:09:13 +0000 (10:09 -0500)]
If all the targets aren't satisfied, reinitialize the packet.
--HG--
extra : convert_revision :
5b0a977a162a1b881b97a3185fb386cc76632a4a
Ron Dreslinski [Tue, 14 Nov 2006 06:38:42 +0000 (01:38 -0500)]
Update atomic and functional paths for snoops as well
--HG--
extra : convert_revision :
566d73438efb87ca683e4dee23454d880db3dfc7
Ron Dreslinski [Tue, 14 Nov 2006 06:13:26 +0000 (01:13 -0500)]
Update phase param in the .py file for the cpus
--HG--
extra : convert_revision :
cd2eb8c00adcb34b8693a4d1a66187927c0f6803
Ron Dreslinski [Tue, 14 Nov 2006 06:12:52 +0000 (01:12 -0500)]
Update bus bridges now that snoop ranges are passed properly
src/mem/bridge.cc:
Update brdiges, now that snoop addresses are properly forwarded.
Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once
--HG--
extra : convert_revision :
26cc9ee4429be45d4476fa435e0e9a54843c2509
Ron Dreslinski [Tue, 14 Nov 2006 06:10:36 +0000 (01:10 -0500)]
Make cpu's capable of having a phase shift
--HG--
extra : convert_revision :
7f082ba5c1cd2445aec731950c31a877aac23a75
Ron Dreslinski [Tue, 14 Nov 2006 03:37:22 +0000 (22:37 -0500)]
Fix a bug to handle the fact that a CPU can send Functional accesses while a sendTiming has not returned in the call stack.
src/mem/cache/base_cache.cc:
Sometimes a functional access comes while waiting on a outstanding packet being sent.
This could be because Timing CPU does some post processing on the recvTiming which send functional access.
Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem
system should remove them from outstanding lists and reinsert them if they fail in the sendTiming.
I did the later, eventually we should consider doing the former if that is the correct behavior.
--HG--
extra : convert_revision :
be41e0d2632369dca9d7c15e96e5576d7583fe6a
Ron Dreslinski [Tue, 14 Nov 2006 02:59:50 +0000 (21:59 -0500)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
253766a17bb5e109f8ad76b3c54e443db5274ef5
Ron Dreslinski [Tue, 14 Nov 2006 02:34:25 +0000 (21:34 -0500)]
If we didn't satisfy all targets, reset the packet we are requesting with.
--HG--
extra : convert_revision :
736372131b046eccf3520292fb3c086dc568d918
Ron Dreslinski [Tue, 14 Nov 2006 02:33:01 +0000 (21:33 -0500)]
Fix some errors related to snooping and functional access in the bus
src/mem/bus.cc:
Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.
--HG--
extra : convert_revision :
7276059c798a85cb9d138ccc5531298ecd055c13
Ron Dreslinski [Tue, 14 Nov 2006 00:56:34 +0000 (19:56 -0500)]
Fix problems with snoop ranges not working properly on functional accesses
src/mem/bus.cc:
Actually return the snoop list when asked for it.
Don't get stuck in infinite functional loops
--HG--
extra : convert_revision :
8e6dafbd10b30d48d28b6b5d4b464e8e8f6a3ddc
Ron Dreslinski [Tue, 14 Nov 2006 00:12:45 +0000 (19:12 -0500)]
Changes needed for a bus from CPU->L1
src/cpu/simple/atomic.cc:
Make the atomic cpu return 0 on snoops.
--HG--
extra : convert_revision :
aad96ad36e0c764c7cfef8b0c8e97877574f5845
Ron Dreslinski [Tue, 14 Nov 2006 00:00:50 +0000 (19:00 -0500)]
Since cpus now send out snoop ranges, remove it from the cache.
--HG--
extra : convert_revision :
82882eb131aa66eba9f281b64db21d5cbfefb1b9
Ron Dreslinski [Mon, 13 Nov 2006 23:51:16 +0000 (18:51 -0500)]
Make CPU models signal to update the snoop ranges
--HG--
extra : convert_revision :
717b62510f28a69af99453309fbbb458359eeb2a
Lisa Hsu [Mon, 13 Nov 2006 21:18:47 +0000 (16:18 -0500)]
main.i:
swig still thought the default arg for simulate() was -1, make it MaxTick
--HG--
extra : convert_revision :
2bcbef7e5e5d28cf55645fdc53d43e3953b1a11c
Ron Dreslinski [Mon, 13 Nov 2006 21:09:47 +0000 (16:09 -0500)]
Update splash2 config files
configs/splash2/run.py:
Fix MaxTick for splash configs
configs/splash2/cluster.py:
Add a config that allows clusters of CPU's to be attached to a single L1
--HG--
extra : convert_revision :
1bb0a0c5f4889316940a9858be90ae2eaa849f1a
Nathan Binkert [Mon, 13 Nov 2006 20:20:08 +0000 (12:20 -0800)]
Expose debugBreakCycle through swig and get rid of
the Debug param context
--HG--
extra : convert_revision :
40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
Nathan Binkert [Mon, 13 Nov 2006 20:18:36 +0000 (12:18 -0800)]
Clean up comment
--HG--
extra : convert_revision :
75c6415c49305e2f8cf7f833c66a46a4dee503ea
Ali Saidi [Mon, 13 Nov 2006 18:26:36 +0000 (13:26 -0500)]
Parse CC/CXX early so that we use the correct compiler for testing dependencies/versions/libraries/etc
--HG--
extra : convert_revision :
b34ee03e44b35df30b746c4c570316db75d6ffe5
Kevin Lim [Mon, 13 Nov 2006 07:49:13 +0000 (02:49 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision :
6ef2249bfa3f7149830efdb42a313422090da7d7
Kevin Lim [Mon, 13 Nov 2006 07:49:03 +0000 (02:49 -0500)]
More interrupt reworking.
--HG--
extra : convert_revision :
40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
Steve Reinhardt [Mon, 13 Nov 2006 06:04:00 +0000 (22:04 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
faab7569deefde94c20133b2f70a8567bcaa2960
Steve Reinhardt [Mon, 13 Nov 2006 06:03:42 +0000 (22:03 -0800)]
Make setRegWithEffect do something in SE mode.
--HG--
extra : convert_revision :
88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8
Kevin Lim [Mon, 13 Nov 2006 05:26:38 +0000 (00:26 -0500)]
Change warn to DPRINTF.
--HG--
extra : convert_revision :
746bdf92334d220158eb0eb6bf113b4dcedbb354
Kevin Lim [Mon, 13 Nov 2006 05:24:22 +0000 (00:24 -0500)]
Update output refs. Some FS statistics will change (namely the ITB) due to the recent TLB changes. Now PAL mode accesses are counted as hits in the TLB.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
Update refs.
--HG--
extra : convert_revision :
6798c5753d4d7bd7b5667d59cf564012b781ce8a
Kevin Lim [Mon, 13 Nov 2006 04:31:29 +0000 (23:31 -0500)]
Fix typo.
--HG--
extra : convert_revision :
05db10e20d33302fe830d5759b8881b1233aca87
Kevin Lim [Mon, 13 Nov 2006 04:30:09 +0000 (23:30 -0500)]
Fix for regression failure.
src/cpu/o3/fetch_impl.hh:
Fetch needs to make sure it isn't waiting on an Icache access.
--HG--
extra : convert_revision :
b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
Kevin Lim [Mon, 13 Nov 2006 02:57:58 +0000 (21:57 -0500)]
Merge ktlim@zamp:./local/clean/tmp/test-regress
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision :
b98236507bb8996ce605b48b5a5a6a7aac297dc5
Kevin Lim [Mon, 13 Nov 2006 02:49:51 +0000 (21:49 -0500)]
Fix for non-FS compile.
--HG--
extra : convert_revision :
661b412b0ae670181b89cb7dbc5e9d813804aa7a
Nathan Binkert [Mon, 13 Nov 2006 02:49:16 +0000 (18:49 -0800)]
Create a module called internal where swigged stuff goes.
Rename cc_main to internal.main
--HG--
extra : convert_revision :
e938005f600fbf8a43435e29426a948f4501f072
Kevin Lim [Mon, 13 Nov 2006 01:15:30 +0000 (20:15 -0500)]
Updates to support new interrupt processing and removal of PcPAL.
src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
--HG--
extra : convert_revision :
9bac3f9ffed4948ee788699b2fa8419bc1ca647c
Ron Dreslinski [Sun, 12 Nov 2006 16:42:07 +0000 (11:42 -0500)]
Update for maxtick in splash2/memtest configs
configs/example/memtest.py:
configs/splash2/run.py:
Update for maxtick
--HG--
extra : convert_revision :
94106625be1ebc2b614db16720a4861e47222c0b
Ron Dreslinski [Sun, 12 Nov 2006 16:07:34 +0000 (11:07 -0500)]
Update refs for functional access fixes
--HG--
extra : convert_revision :
aa34e0e7254daf20ecb7c14d430f08927a8fb9ca
Ron Dreslinski [Sun, 12 Nov 2006 15:41:18 +0000 (10:41 -0500)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
498304c24435437f8f1942bb8aeafe69ba22a089
Ron Dreslinski [Sun, 12 Nov 2006 14:30:12 +0000 (09:30 -0500)]
Physical memory overrides the tport version of recvFunctional, need to do the
check here for responses that match as well
--HG--
extra : convert_revision :
69c3628a381a9da885fab0272abf40c3411a5f0f
Ron Dreslinski [Sun, 12 Nov 2006 14:06:15 +0000 (09:06 -0500)]
Handle packets being deleted by lower level properly.
Fixes for Mem Leak associated with Writebacks.
src/mem/cache/miss/mshr_queue.cc:
Fixes for Mem Leak associated with Writebacks. (Double Delete removed)
--HG--
extra : convert_revision :
7a52ddd57da35995896f2c4438a58aa53f762416
Ron Dreslinski [Sun, 12 Nov 2006 12:16:34 +0000 (07:16 -0500)]
Don't insert reponses into the list more than once
If you get inserted in the front, reschedule the event
--HG--
extra : convert_revision :
eccbacf5ec85600e5b68eb554fee2c0e2b65e965
Ron Dreslinski [Sun, 12 Nov 2006 11:44:05 +0000 (06:44 -0500)]
Move code before a early return to make sure it is executed on all paths
--HG--
extra : convert_revision :
cfdd5b6911422fbb733677c43d027aa4407fbc85
Ron Dreslinski [Sun, 12 Nov 2006 11:36:33 +0000 (06:36 -0500)]
Yet another small bug in mem system related to flow control
src/mem/cache/cache_impl.hh:
When upgrades change to readEx make sure to allocate the block
Fix dprintf
--HG--
extra : convert_revision :
8700a7e47ad042c8708302620b907849c4bfdded
Ron Dreslinski [Sun, 12 Nov 2006 11:35:39 +0000 (06:35 -0500)]
Fix functional access errors related to delayed respnoses in cachePort
src/mem/cache/base_cache.cc:
On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
Create a wrapper to toggle the hasData flag on delayed responses
--HG--
extra : convert_revision :
1ced8d4e3dc12a059fb7636d59e429cd3dd46901
Nathan Binkert [Sun, 12 Nov 2006 07:57:20 +0000 (23:57 -0800)]
Fix Typo
--HG--
extra : convert_revision :
4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
Nathan Binkert [Sun, 12 Nov 2006 04:46:56 +0000 (20:46 -0800)]
set TRACING_ON one way or another explicitly in the
SConscript file instead of basing it on DEBUG
--HG--
extra : convert_revision :
6e6807cc4350ef92baeaaabfeb3dc0bb785128ba
Nathan Binkert [Sun, 12 Nov 2006 01:30:37 +0000 (17:30 -0800)]
Delete the actual PseudoInst file
--HG--
extra : convert_revision :
54e3dfbc1022fcc663a9c0e67f6434395d1fe33c
Nathan Binkert [Sun, 12 Nov 2006 01:22:10 +0000 (17:22 -0800)]
Get rid of the ParamContext for pseudo instructions and move
the parameters to the BaseCPU object.
--HG--
extra : convert_revision :
557292cffb40918133647b0c9ac653ee5112df2e
Gabe Black [Sat, 11 Nov 2006 12:16:24 +0000 (07:16 -0500)]
The Lock_Flag_DepTag went away earlier, and using TheISA gives the false impression that this code is ISA independent.
--HG--
extra : convert_revision :
67d9e51702efbe5f5244268e3753328a6cf1a1d5
Gabe Black [Sat, 11 Nov 2006 12:15:16 +0000 (07:15 -0500)]
Certain header files should only be used in FS.
src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
--HG--
extra : convert_revision :
91ea61f2e7970e7146b6d407ee250fcb20cd4d48
Ron Dreslinski [Sat, 11 Nov 2006 03:45:50 +0000 (22:45 -0500)]
More fixes for functional accesses. It now makes the writeback memory leak to crash all configs.
Working on that now.
src/mem/cache/base_cache.cc:
Keep a list of the responders so we can search them on functional accesses.
src/mem/cache/base_cache.hh:
Properly put things on a list for responses so we can search the list.
Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there)
src/mem/cache/cache_impl.hh:
Properly return when the first read hit on a functional access.
Make sure to call to check the other ports list of packets before forwarding it out.
--HG--
extra : convert_revision :
1d21cb55ff29c15716617efc48441329707c088a
Ron Dreslinski [Sat, 11 Nov 2006 03:41:21 +0000 (22:41 -0500)]
Big fix for functional access, where we forgot to copy the last byte on write intersections.
src/mem/packet.cc:
Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
Fix for the proper semantics of fixPacket
--HG--
extra : convert_revision :
215e05db9099d427afd4994f5b29079354c847d8
Ali Saidi [Sat, 11 Nov 2006 01:17:54 +0000 (20:17 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
e4f9bb663099662a94c5522e6b4955c2a83bac8d
Ali Saidi [Sat, 11 Nov 2006 01:17:42 +0000 (20:17 -0500)]
fix endian issues with condition codes
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
--HG--
extra : convert_revision :
4579392184b40bcc1062671a953c6595c685e9b2
Kevin Lim [Fri, 10 Nov 2006 20:35:06 +0000 (15:35 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision :
35e2ff6ce62281299ad98dca64ba04a3a8a6757c
Gabe Black [Fri, 10 Nov 2006 20:32:15 +0000 (15:32 -0500)]
Elaborated on the tlb stubs so that they just set the physical address to the virtual address.
--HG--
extra : convert_revision :
41478abc4d21d504420f6842338675c0767f7cf9
Gabe Black [Fri, 10 Nov 2006 20:30:59 +0000 (15:30 -0500)]
Fixed up DepTags a little. I think NumMicroIntRegs shouldn't be added to Ctrl_Base_DepTag.
--HG--
extra : convert_revision :
2ebb3eb781441ba936c8d8bb1f42e4c0840aff2e
Gabe Black [Fri, 10 Nov 2006 20:29:32 +0000 (15:29 -0500)]
Added StrandStsReg operand.
--HG--
extra : convert_revision :
51be41716ed9fe0e99e53f2341ad5651a525055a
Gabe Black [Fri, 10 Nov 2006 20:28:58 +0000 (15:28 -0500)]
Put in provisions for rd, rdpr, rdhpr, wr, wrpr, and wrhpr to disassemble properly.
--HG--
extra : convert_revision :
f2cad8a5879999438ba9b05f15a91320e7a4cc4a
Gabe Black [Fri, 10 Nov 2006 20:27:06 +0000 (15:27 -0500)]
Made the annul of unconditional conditional branches behave properly, added code to read and write the strand_sts_reg, and made restored a Priv instruction.
--HG--
extra : convert_revision :
386512215f7243d230717c369217f8d2f9ada935
Gabe Black [Fri, 10 Nov 2006 20:25:52 +0000 (15:25 -0500)]
Fixed up the code that prints out registers to take into account microregisters.
--HG--
extra : convert_revision :
6809de467e4500ce34447c0544caf0ba04af81e7
Gabe Black [Fri, 10 Nov 2006 20:25:03 +0000 (15:25 -0500)]
Tweaked debug output.
--HG--
extra : convert_revision :
cd33b7c1ebdbefd42f18c1435b2519d06d9914a6
Gabe Black [Fri, 10 Nov 2006 20:24:10 +0000 (15:24 -0500)]
Touched up faults, and made POR actually do something.
--HG--
extra : convert_revision :
38951352edbfc423fb6767a9aac49a703578c0ac
Kevin Lim [Fri, 10 Nov 2006 17:44:15 +0000 (12:44 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision :
0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
Kevin Lim [Fri, 10 Nov 2006 17:39:43 +0000 (12:39 -0500)]
Also include a function to form the input path.
--HG--
extra : convert_revision :
d2141e3b8c56296fbbe2c4c1ceb80616f269884a
Kevin Lim [Fri, 10 Nov 2006 17:28:23 +0000 (12:28 -0500)]
Try to setup commands properly.
--HG--
extra : convert_revision :
9f4af3c5f52841b10e9f17c48470716703a1be67
Kevin Lim [Fri, 10 Nov 2006 17:25:08 +0000 (12:25 -0500)]
Change up some warnings to DPRINTFs.
--HG--
extra : convert_revision :
b3e9fa094d68f608865dedfc9f3f4125a20fd748
Kevin Lim [Fri, 10 Nov 2006 17:14:38 +0000 (12:14 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision :
56cb7fe3be5b63bd89b48ac6cb88b47d13b4c137
Gabe Black [Fri, 10 Nov 2006 10:49:16 +0000 (05:49 -0500)]
Actually finished moving the register file stuff around.
--HG--
extra : convert_revision :
786735ecea8ff480db6b3754ac5daa562938d988
Gabe Black [Fri, 10 Nov 2006 10:29:05 +0000 (05:29 -0500)]
Moved the Alpha float regfile into it's own regfile and got rid of constants.hh and isa_traits.cc
--HG--
extra : convert_revision :
55afd7d21c276906520da375b3bbb563be420880
Gabe Black [Fri, 10 Nov 2006 09:54:25 +0000 (04:54 -0500)]
Split out alpha integer register file into it's own files.
--HG--
extra : convert_revision :
164bdcec2860c5dca3f0f11d189781b88dd717cb
Gabe Black [Fri, 10 Nov 2006 09:33:41 +0000 (04:33 -0500)]
The reset function of the MiscRegFile really resets it now. This function is called from the class's constructor.
--HG--
extra : convert_revision :
4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe
Gabe Black [Fri, 10 Nov 2006 09:14:25 +0000 (04:14 -0500)]
Set the ASI register to be something explicitly so that simulation is deterministic.
--HG--
extra : convert_revision :
38cd06f946fc0cc22288f71f567e77ce8fdfea99
Gabe Black [Fri, 10 Nov 2006 09:11:46 +0000 (04:11 -0500)]
Change exetrace code for working with my trace tool to use stream io rather than sprintf which was breaking on 64 bit hosts.
--HG--
extra : convert_revision :
184d751392dfcc8c80ac1a6c0ebc3061ff0a3f20
Gabe Black [Fri, 10 Nov 2006 09:02:39 +0000 (04:02 -0500)]
Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.
--HG--
extra : convert_revision :
1b518873b6e1a073b58cbe27642537d5ae3a604d
Gabe Black [Fri, 10 Nov 2006 02:30:48 +0000 (21:30 -0500)]
Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants.
--HG--
extra : convert_revision :
e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
Gabe Black [Fri, 10 Nov 2006 00:24:35 +0000 (19:24 -0500)]
Fix a couple uninitialized variables.
--HG--
extra : convert_revision :
d17d28a9520524e5f56bd79beb9b2be6ce76a22f
Ali Saidi [Thu, 9 Nov 2006 23:22:46 +0000 (18:22 -0500)]
Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision :
bbbd8a56134f2dda2728091f740e2f7119b0c4af
Kevin Lim [Thu, 9 Nov 2006 20:06:00 +0000 (15:06 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
--HG--
extra : convert_revision :
dafe2d4a032b277c219ea13faf20567c20c1f2f4
Kevin Lim [Thu, 9 Nov 2006 20:05:13 +0000 (15:05 -0500)]
Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.
configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
--HG--
extra : convert_revision :
534ded558ef96cafd76b4b5c5317bd8f4d05076e
Nathan Binkert [Thu, 9 Nov 2006 16:43:35 +0000 (08:43 -0800)]
Factor out all of the encumbered stuff into separate SConscript
files so the directories can easily be deleted.
Remove the FullCPU from the ALL_CPU_LIST and only add it if
it exists.
--HG--
extra : convert_revision :
b16f56bb92a0063803c5099732dc289fe4363768
Kevin Lim [Thu, 9 Nov 2006 16:37:26 +0000 (11:37 -0500)]
Be sure to populate the packet's finishTime field in the atomic timing case.
--HG--
extra : convert_revision :
ef34818eb2dea5b3a8e754bf56745a7cd2497bf0