mem-cache: Use Packet functions to write data blocks

Instead of using raw memcpy, use the proper writer functions
from the Packet class in Cache.

Fixed typos in comments of these functions.

Change-Id: I156a00989c6cbaa73763349006a37a18243d6ed4
Reviewed-on: https://gem5-review.googlesource.com/9661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev: Make sure the EtherTap device uses the right event queue.

The EtherTap device may be called into from an event on the PollQueue when
some event queue other than its own is active. This change ensures that it
switches event queues if necessary before doing anything that may cause more
events to be scheduled.

Change-Id: If8666542d7664780c0b371230e1e5fba93fbc1c0
Reviewed-on: https://gem5-review.googlesource.com/9521
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Make bitunion output functions static/inline.

The specializations need to be online only and not static, but the
template itself is static and inline.

Originally they were in an anonymous namespace, but that causes
warnings when building on clang or with certain versions of gcc because
the functions may not be used in every .cc.

Change-Id: Iff127337f7bf0c18755de07a49d6e7a9ce6f2f0a
Reviewed-on: https://gem5-review.googlesource.com/9581
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove unused return value from the recvTimingReq func

The recvTimingReq function in the cache always returns true. This
changeset removes the return value.

Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972
Reviewed-on: https://gem5-review.googlesource.com/8289
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Fix FALRU data block seg fault

FALRU didn't initialize the blocks' data, causing seg faults.
This patch does not make FALRU functional yet.

Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b
Reviewed-on: https://gem5-review.googlesource.com/9302
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create LFU replacement policy

Implementation of a Least Frequently Used replacement policy.

Change-Id: I772afccd3a7955777e53d59341e922718db44e5c
Reviewed-on: https://gem5-review.googlesource.com/8890
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create RRIP Replacement Policy

Implementation of a Re-Reference Interval Prediction replacement
policy.

Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b
Reviewed-on: https://gem5-review.googlesource.com/8981
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Create BRRIP replacement policy

Implementation of a Bimodal Re-Reference Interval Prediction
replacement policy.

Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912
Reviewed-on: https://gem5-review.googlesource.com/8891
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Add a default output function for bitunion types.

This way printing bitunions with, for instance, DPRINTF actually prints
something useful. More specialized overloads will still allow printing
particular bitunion types in ways that might make more sense for that
particular type.

Change-Id: I92beb0ce07683ba8b318cf25aa73e0057e4a60ef
Reviewed-on: https://gem5-review.googlesource.com/9461
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

dev: sparc: Get rid of the TheISA namespace in the SPARC devices.

It's not used, and so doesn't need to be brought in with a "using"
statement.

Change-Id: Iff4f7c66dbf1ee18e2e1a7d3e73bbae8cc4bf8eb
Reviewed-on: https://gem5-review.googlesource.com/9406
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

dev: Remove a bunch of Alpha code from MIPS, and unnecessary TheISAs.

There was a bunch of commented out code in the MIPS malta
implementation which originally came from Alpha. That code is now
deleted. Also, the MIPS code pulled in the TheISA namespace which it
didn't use.

Change-Id: I8470cc2fecb302f4399e52de4de9daf79c00a711
Reviewed-on: https://gem5-review.googlesource.com/9405
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Remove ExtMachInst typedefs from the O3 CPU model.

These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.

Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

This doesn't completely hide the ISA specific ExtMachInst type inside
the ISAs since it still gets applied in arch/generic, but it at least
pulls it into the arch directory.

Change-Id: Ic2188d59696530d7ecafdff0785d71867182701d
Reviewed-on: https://gem5-review.googlesource.com/9403
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

sparc: Add some missing M5_FALLTHROUGHs and breaks.

These fix what I believe are some bugs, and also some gcc warnings.

Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0
Reviewed-on: https://gem5-review.googlesource.com/9402
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Stop extracting inst_flags from the machInst.

The instruction representation is already encoded in the trace
protobuf, so there's no reason to encode a part of it again. This is
especially true since this supposedly generic code is extracting the
first 8 bits of the machInst, a totally arbitrary set of bits for most
ISAs. If certain bits within a machine instruction are actually
relevant, the consumer of the trace should be able to interpret the
instruction bytes which are already there and extract the same bits
within the context of whatever ISA they're appropriate for.

Change-Id: Idaebe6a110d7d4812c3d7c434582d5a9470bcec1
Reviewed-on: https://gem5-review.googlesource.com/9401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Proposed fix for backwards compatibility in proto/inst.proto.

I haven't tested this at all, but this may fix backwards compatibility
in inst.proto by removing the oneof construct.

Change-Id: Iba19744791c2c577c3b442402f8cc6dcef8550bd
Reviewed-on: https://gem5-review.googlesource.com/9361
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Re-enable override based warnings on gcc.

These warnings have been fixed.

Change-Id: I28ee5f4ae21412121849fcb9d273939d8e462842
Reviewed-on: https://gem5-review.googlesource.com/9344
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Fix all override related warnings.

Clang has started(?) reporting override related warnings, something gcc
apparently did before, but was disabled in the SConstruct. Rather than
disable the warnings in for clang as well, this change fixes the
warnings. A future change will re-enable the warnings for gcc.

Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da
Reviewed-on: https://gem5-review.googlesource.com/9343
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Use the new asBytes function in the protobuf inst tracer.

Use this function to get the binary representation of the instruction
rather than referencing the ExtMachInst typed machInst member of the
StaticInst directly. ExtMachInst is an ISA specific type and can't
always be straightforwardly squished into a 32 bit integer.

Change-Id: Ic1f74d6d86eb779016677ae45c022939ce3e2b9f
Reviewed-on: https://gem5-review.googlesource.com/7563
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Add a virtual asBytes function to the StaticInst class.

This function takes a pointer to a buffer and the current size of the
buffer as a pass by reference argument. If the size of the buffer is
sufficient, the function stores a binary representation of itself
(generally the ISA defined instruction encoding) in the buffer, and
sets the size argument to how much space it used. This could be used
by ISAs which have two instruction sizes (ARM and thumb, for example).
If the buffer size isn't sufficient, then the size parameter should be
set to what size is required, and then the function should return
without modifying the buffer.

The buffer itself should be aligned to the same standard as memory
returned by new, specifically "The pointer returned shall be suitably
aligned so that it can be converted to a pointer of any complete object
type and then used to access the object or array in the storage
allocated...". This will avoid having to memcpy buffers to avoid
unaligned accesses.

To standardize the representation of the data, it should be stored in
the buffer as little endian. Since most hosts (including ARM and x86
hosts) will be little endian, this will almost always be a no-op.

Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6
Reviewed-on: https://gem5-review.googlesource.com/7562
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: fix missing overrides in repl policies

Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/9321
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Make sure addresses print in hex

Added fix in the invalid transition panic and various places in ruby
random tester.

Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8941
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

learning_gem5: Add a simple config for MI_example

Adds a new config script to configure the MI_example protocol. This script
closely follows the script used for MSI, but instead supports the
MI_example protocol. This script works with the simple_ruby runscript and
can be included instead of msi_caches.

Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8945
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

learning_gem5: Ruby random tester files for MSI

Adds a pair of scripts to run the Ruby random tester with the MSI protocol.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I15550a36618546f0354163b0216cf771f434ed84
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8944
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

learning_gem5: Add config files for MSI protocol

Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.

By default, this script runs with two CPUs and runs the recently added
thread test binary.

Currently, only SE mode is supported.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8943
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8942

mem-cache: Create FIFO replacement policy

Implementation of a First-In, First-Out replacement policy.

Change-Id: Id234ec9d29c092dd4516e609da14b8a75a96b5e4
Reviewed-on: https://gem5-review.googlesource.com/8888
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix MRU rebase

Rebase of MRU missed a const qualifier, introducing a compilation
error.

Change-Id: Ia25aa30523613a1a87593a353abe439946656f63
Reviewed-on: https://gem5-review.googlesource.com/9301
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Distinguish IS TLBI from non-IS

TLBI broadcasting was the default implementation of most of TLBI
instructions. This patch applies the broadcasting behaviour only to the
Inner-Shareable subset, while simpler TLB invalidation instructions only
affect the PE that executes them.

Change-Id: Idb01d0d4f593131f657e8fc9668112de8e4ccdcb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9182
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Created function for TLB ASID Invalidation

This patch is intended to avoid code duplication and extends the set of
TLBI ISA functions adding the entry invalidation by ASID match.

Change-Id: I9bcb498059ea480dd2118639c7b3c64fea80a5e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9181
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

hsail: Get rid of an inert private member of StorageSpace.

The "segment" private element in this class was only ever set to zero
on construction, and then used to index into a list of segment names
to get the string "none" in a DPRINTF. If debugging was turned off,
there would be no consumers of that variable, and that upset g++. This
change removes the essentially useless variable, and also that bit of
text in the DPRINTF.

Change-Id: I3f85db4af5f0678768243daf84b8d698350af931
Reviewed-on: https://gem5-review.googlesource.com/9221
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: Make the protobuf inst tracer accept variable sized instructions.

This change adds an inst_bytes field which is of type bytes, and puts
it in a oneof with the previously required inst field. If an
instruction's encoding happens to be 4 bytes long, the original inst
field will be used. Otherwise, the new variably sized inst_bytes field
will be used.

Because this tracer doesn't have visibility into how the data in
inst_bytes is structured, it can't do any endian conversion itself.
To maintain compatibility between producers and consumers who may have
different endiannesses, all data should be manually converted to
little endian before being stored in this field.

inst will be converted into little endian by protobuf, and so
compatibility doesn't have to be handled manually.

Change-Id: I290713f70e7124d8aa9550c022c71334939d84a6
Reviewed-on: https://gem5-review.googlesource.com/7561
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Create MRU replacement policy

Implementation of a Most Recently Used replacement policy.

Change-Id: Id52cb247ca25d4523dcc53490d113695dac6a3f1
Reviewed-on: https://gem5-review.googlesource.com/8889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Split array indexing and replacement policies.

Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:

- Array indexers determine the possible locations for block allocation.
  This information is used to generate replacement candidates when
  conflicts happen.
- Replacement policies determine which of the replacement candidates
  should be evicted to make room for new allocations.

For this reason, they were split into different classes. Advantages:

- Easier and more straightforward to implement other replacement
  policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes

As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).

Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow clean operations when block allocation fails

Block allocation can fail when there is an in-service MSHR that
operates on the victim block. This can happed due to:
* an upgrade operation: a request that needs a writable copy of the
  block finds a shared (non-writable) copy of the block in the cache
  and has allocates an MSHR for the pending upgrade operation, or
* a clean operation: a clean request finds a dirty copy of the block
  and allocates an MSHR for the pending clean operation.
This changes relaxes an assertion to allow for the 2nd case (cache
clean operations).

Change-Id: Ib51482160b5f2b3702ed744b0eac2029d34bc9d4
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9021
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch, arm: Fix implicit-fallthrough GCC warnings

GCC 7 generates spurious fallthrough warnings in nested switch blocks
where the inner switch block return.  There is already a GCC fix [1]
submitted for review but, until it is merged into GCC trunk, GEM5 will
not build with GCC 7 due to these fallthrough warnings.  This patch
silences the spurious fallthrough warnings by appending a M5_UNREACHABLE
statement in the outer switch cases.

Note there is another GEM5 patch [2] to fix other fallthrough warnings.

[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html
[2] https://gem5-review.googlesource.com/c/public/gem5/+/8541

Change-Id: I97cd8bfa90a88e93cee60cf27a8c93611d11a242
Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/9101
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

riscv: throw IllegalInstFault when decoding invalid instructions

If an instruction is invalid, some assertions may in the decoder may
fail the entire simulation. Instead, we want to raise an
IllegalInstFault instead of failing immediately in the decoder if the
invalid instruction is being speculatively executed.

Change-Id: I5cb72ba06f07f173922f86897ddfdf677e8c702f
Reviewed-on: https://gem5-review.googlesource.com/9261
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Monir Zaman <monir.zaman.m@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arm: Fix implicit-fallthrough warnings when building with gcc-7+

gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.

The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.

[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html

Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-x86,sim-se: Enable prlimit syscall

Change-Id: I15f0e5ddb72578de90ed68866c8a0c1501717d61
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8921
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim-se: Fix fallthrough in prlimit

Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8904
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-x86,sim-se: Bump kernel version to 3.2

Current glibc expects at least kernel 3.2. Bump this so syscall emulation
with dynamically-linked binaries works.

Change-Id: I07077ed2de14c308f6ff79cae677915612557332
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8903
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim-se: Add /sys/devices/system/cpu/online file

Add the special file /sys/devices/system/cpu/online to the files that gem5
knows how to handle in SE mode. This file lists the CPUs that are active.
For instance, in an 8 CPU system it is the following:
0-7

This implementation simply returns a file that is 0-%d where %d is the
current number of thread contexts.

This file is required for C++11 threads with gcc 4.8 and above.

Change-Id: I0b566f77e75e9eca480509814d0fd038a231b940
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8902
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

tests: Add test program for C++ threads

Simple program that spawns threads equal to the number of CPU cores and
has some false sharing for testing coherence protocols.

Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8901
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

arch-arm: Fix unused variable warning in faults.cc

Change-Id: Ife4a2189e140cdefcf53fa88213d8a5225067457
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9201
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

x86: Add bitfields which can gather/scatter bases and limits.

Add bitfields which can gather/scatter base and limit fields within
"normal" segment descriptors, and in TSS descriptors which have the
same bitfields in the same positions for those two values.

This centralizes the code which manages those bitfields and makes it
less likely that a local implementation will be buggy.

Change-Id: I9809aa626fc31388595c3d3b225c25a0ec6a1275
Reviewed-on: https://gem5-review.googlesource.com/7661
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Simplify the implementations of RDTSC and RDTSCP slightly.

These instructions originally read the TSC into t1 and then unpacked it
into eax and edx using a move, a right shift, and then another move.
We can combine the second shift and move. The shift will move the
upper 32 bits into the lower 32 bits, and clear the upper 32 bits to
zero. This has the same effect as moving the lower 32 bits post-shift
into another register, since the upper 32 bits will be cleared to zero
based on x86 partial register access semantics.

Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b
Reviewed-on: https://gem5-review.googlesource.com/9044
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Implement the RDTSCP instruction.

This is very similar to RDTSC, except that it requires all younger
instructions to retire before it completes, and it writes the TSC_AUX
MSR into ECX. I've added an mfence as an iniitial microop to ensure
that memory accesses complete before RDTSCP runs, and added an rdval
microop at the end to read the TSC_AUX value into ECX.

Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9
Reviewed-on: https://gem5-review.googlesource.com/9043
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Mark the RDTSC instruction as .serialize_before.

Change-Id: I20bf6a57ea4354aac9267845bb37b70b83d6fcde
Reviewed-on: https://gem5-review.googlesource.com/9042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Fix maybe-uninitialized GCC warnings

GCC 7 generates maybe-uninitialized warnings at the code that updates
the "dest" variables in the writeVecElem function of neon64_mem.hh file.
It is because the generated code does not appropriately initialize the
output variable before passing it to the writeVecElem function.  This
patch initializes the output variable to fix this.

Change-Id: I50a8f4e456ccdcaa3db1392ec097017450c56ecb
Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/9121
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix loop range in pngwriter

The inner loop range limit should be width instead of height.

Change-Id: I091c590713c945d4bd04ffcc974d4eb8aa23d1b2
Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/9081
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

tests: Add missing print replacements in tests subdir

Some python files were still using deprecated print statement.

Change-Id: I19b1fe9c28650707f01725d40c87ad0538f9c5e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9141
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: ERET from AArch64 to AArch32 ignore MSBs

The 32 most significant bits of ELR_ELx must be ignored when returning
from AArch64 to AArch32.

Change-Id: I412d72908997916404e16e9eeca2789a9c529e58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8881
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

learning_gem5: Update README for Learning gem5

Change-Id: I94485e401bc77207cab68c1e24ef7a6ed83bd43d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8946
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-ruby: Fix RubyPrefetcher support in MESI_Two_Level

Only a small quantity of prefetches were issued, as the positive
feedback mechanism was not implemented. This commit adds a new
action po_observeHit, which notifies the RubyPrefetcher of
successful prefetches and resets the prefetch flag.

When a cache line was replaced by a prefetch, the wrong queue could
be stalled. This commit adds a new event PF_L1_Replacement, which
stalls the correct queue.

The behavior when receiving a prefetch or instruction fetch while
in PF_IS_I (prefetch caused GETs, but got invalidated before the
response was received) was undefined. This was changed to drop the
prefetch request or change the state to non-prefetch, respectively.
This behavior is analogous to IS_I (non-prefetch caused GETs, but
got invalidated before the response was received) and the data case,
respectively.

In my local branch a major (20+%) performance increase can be
observed in SPEC2006 gobmk and leslie3d when enabling the
prefetcher. Some other benchmarks like bwaves, GemsFDTD, sphinx and
wrf show smaller (~10%) performance increases. Unfortunately, the
performance in most other SPEC benchmarks is still poor, most likely
as the prefetcher does not detect strides fast/often enough. In
order to push the change timely (most benchmarks have runtimes in
the order of days on my machine even with the smallest parameters)
after checkout, I have only run gobmk with the base repository
+ this commit. The results match those of my local branch.

Change-Id: I9903a2fcd02060ea5e619b409f31f7d6fac47ae8
Reviewed-on: https://gem5-review.googlesource.com/8801
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Swapnil Haria <swapnilster@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Adding IPA-Based Invalidating instructions

This patch introduces the TLB IPA-Based invalidating instructions in
aarch32. In the entry selection policy the level of translation is not
taken into account.
This means that no difference stands between (e.g.) TLBIIPAS2 and
TLBIPAS2L.

Change-Id: Ieeb54665480874d2041056f356d86448c45043cb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8822
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Implement missing aarch32 TLBI registers

In the pool of TLB Invalidate system register a category of instruction
was missing: the ones operating on entries added to the TLB during the
last level only of a table walk.  (E.g. TLBIVMAL).  This patch is not
considering this matching criteria when invalidating the entries and it
is rather performing the invalidation on all levels.

Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Python regression scripts using new print function

Change-Id: I92060da4537e4ff1c0ff665f2f6ffc3850c50e88
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8892
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use CacheBlk parameter on address regeneration

Skewed caches need to know the way to regenerate a block address.

Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40
Reviewed-on: https://gem5-review.googlesource.com/8782
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix missing overrides

clang doesn't like inconsistent overrides. Add override to all overidden
functions in lru.hh

Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8861
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sparc: Passify a new g++ warning.

g++ seems to think there are some missing brackets when initializing
the sparc fault information. Passify it by adding extra brackets.

Change-Id: I826995f88b8ac8a21721c949a244dec480831b80
Reviewed-on: https://gem5-review.googlesource.com/8763
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

arch-arm: Enable Debug IFSC when faulting to aarch64 mode

Previous code was aborting simulation when a debug exception taken in
aarch64 mode was encountered. This because an invalid (0xff)
instruction fault status code was produced.

Change-Id: I289f93f672be70cfbdc404be536809835160bdaf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8363
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix FSC generation in AbortFault

The fault status code generated by a Prefetch/Data Fault was containing
a wrong value when the fault was triggered in aarch32 but handled in
aarch64.  This because the encoding differs between the two ISAs and the
encoder was just checking the starting ISA rather than the the ending
one. In this case the getFsr must be called after we know which is the
ending ISA, which happens only after ArmFault::invoke gets called.  The
fsc update hence happens before writing into the Syndrome register.

Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8362
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Introduce update method in ArmFault class

There is a set of internal variables in ArmFault thats get updated once
the fault is invoked (ArmFault::invoke). Sometimes we rely on those even
if the fault is generated but not invoked (e.g. when checking if a
memory access is producing a fault). This patch is moving the update
functionalities inside a public method so that a client can make use of
it even when not invoking the fault.

Change-Id: I3ac5b6835023f28ec569fe25487dffa356e1b2fd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8361
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix PCAlignmentFault routing to Hypervisor

This patch enables PCAlignmentFault routing to Hypervisor in case
HCR_EL2.TGE == 1, as is happening for other arm exceptions.

Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8841
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Make the block invalidate functions virtual

This change makes the cache block invalidation function in the
BaseTags and CacheBlk class virtual to enable derived classes.

Change-Id: I2e64b01c6ca637f16d10474fc8b08eeec3f23453
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8287
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Make invalidate a common function between tag classes

invalidate was defined as a separate function in the base associative
and fully-associative tags classes although both functions should
implement identical functionality. This patch moves the invalidate
function in the base tags class.

Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8286
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow prefetchers to override setCache.

This lets them hook setCache, perhaps to set up additional state based
on the set cache.

Change-Id: Ic3b34fa43d052c71e8ef733a57fe47c70899cd27
Reviewed-on: https://gem5-review.googlesource.com/8701
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

config: Switch from the print statement to the print function.

Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0
Reviewed-on: https://gem5-review.googlesource.com/8762
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Switch from the print statement to the print function.

Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.

Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

misc: Use the code format for commands and messages

Make the style consistent across code blocks.  This also makes sure
that markdown does not try to read any of the code blocks and try to
do anything with it.

Using the blockquotes instead of code blocks results in github
attempting to render tags and special markdown chars, which is wrong.

Change-Id: I8526933c8283ae02646d6273ed0cbd8e85176bd0
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8323
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Don't fall through into BRAR after RFDR case

If the switch block inside the RFDR case selects the non-default case
and breaks out, it will fall through into the BRAR case, which seems
incorrect.  Put in a break to ensure that it breaks out of the parent
switch block as well.

Change-Id: Ie4cedf66954b7e8f4b884ad9e3a653968bbfaef7
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8563
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Remove ignored const qualifier

gcc8 warns about ignored const qualifiers (-Wignored-qualifiers) and
that breaks builds.  It was suggested that the warning be moved to
Wextra[1] but that's probably not going to happen anytime soon.

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82711

Change-Id: Ib808906deb9a1c2dccb1c34b6563db0c24c66655
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8562
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Leave last byte in strncpy for NULL

The length of the strncpy should be one less than the destination to
ensure that there is space for the last NULL byte in case the source
is longer than the destination.

Change-Id: Iea65fa6327c8242bd8ddf4bf9a5a2b5164996495
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8561
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Import print_function from future

Scons on Fedora 27 imports print_function from the future[1] as a
result of which a gem5 build errors out with a syntax error.  Make all
the scons scripts that use the print statement import the print_function
from future and replace the statements with print function calls.

[1] https://github.com/SCons/scons/commit/34cf3bdb1743de9a5534bfd25998d0a01297f004

Change-Id: I67b7ef978fd7567f94d3cd9a904f8a0c1af07ffb
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8321
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Fix bug generated by 8282

Merge 1ae7fced4d32898531a6875a339ef00e43e20e66 generated
a bug in tagsInUse calculation.

Change-Id: I079e327a0a26a7968f2ed8e433dd6e790c80998b
Reviewed-on: https://gem5-review.googlesource.com/8781
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Populate whenReady for blocks filled from writebacks

Writebacks write data to either an existing block or a newly allocated
block. In either case we need to populate the whenReady field of the
block which will determine when the new value can be used.

Change-Id: I5788fad0b8086a1be96714639bf6a9470b334926
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8285
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use findBlock() in accessBlock()

Use placement policy specific block search within generic access.

Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a
Reviewed-on: https://gem5-review.googlesource.com/8721
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove redundant block initialization on allocation

Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8282
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove mumBlock redundant initialiation from FALRU

Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8281
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Populate the secure bit when the temp block is filled

The secure bit should be set when we fill a block with data from a
secure location, as indicated by the packet that triggers the fill.
This patch fixes a bug in which the cache wouldn't populate the secure
bit when filling the temp block.

Change-Id: I95c706146449804ff42b205b25dd79750f3e882a
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8284
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove unnecessary block initialization on writeback

Change-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8283
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

configs: Fix L3Cache instantiation in lat_mem_rd.py

This changeset updates the lat_mem_rd.py to configure the L3Cache
using the split tag_latency, data_latency parameters.

Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5
Reviewed-on: https://gem5-review.googlesource.com/8288
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove extra block init in BaseSetAssoc

Removed extra initialization of cache block just after they have been
created and organized the comments.

Change-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f
Reviewed-on: https://gem5-review.googlesource.com/8661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Vectorize C arrays in BaseSetAssoc.

Transform BaseSetAssoc's arrays into C++ vectors to avoid unnecessary
resource management.

Change-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34
Reviewed-on: https://gem5-review.googlesource.com/8621
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim, power: Temperature used for power calculations

The temperature used for the power calculations was fixed at 0
degrees, unless a thermal model was setup.  This commit allows
the user to set the temperature that needs to be used by the
power calculation during gem5 configuration.  This value will be
overwritten if there are thermal models present.

Change-Id: I7ca8fa6766bdcba9d362c12fc75d1e1f74385f35
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8602
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Added model type to power model

Static, dynamic or all to differentiate between types of power models
so for example static models will not be asked for a dynamic power

Change-Id: I3a0385821f7c671aedddaebeb038c677367faa81
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Fix CacheSet memory leak

CacheSet blocks were being allocated but never freed.
Used vector to avoid using pure C array.

Change-Id: I6f32fa5a305ff4e1d7602535026c1396764102ed
Reviewed-on: https://gem5-review.googlesource.com/8603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sparc: Fix FS Checkpoint loading

Proposed changes to SPARC FS simulation, testing indicates that checkpoints are now loaded correctly with the following command: build/SPARC/gem5.opt configs/example/fs.py -r 1

Change-Id: Icd44f01a74c41a78828ef6fd7b661e584bdb6966
Reviewed-on: https://gem5-review.googlesource.com/8581
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Make hlt64 a mem barrier with semihosting

The HLT instruction is used to trap into semihosting. The semihosting
code can change the contents of memory behind the back of the CPU,
which requires instructions triggering semihosting to be
non-speculative and memory barriers.

Change-Id: I735166251aa194120ad49c08082d4ac65fe96524
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8373
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add AArch32 HLT Semihosting interface

AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add AArch32 SVC Semihosting interface

AArch32 Svc instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8371
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Adding isa templates for semihosting ops

A new class of Semihosting constructor templates has been added.  Their
main purpose is to check if the Exception Generation Instructions (HLT,
SVC) are actually a semihosting command.  If that is the case, the
IsMemBarrier flag is raised, so that in the O3 model we perform a
coherent memory access during the semihosting operation.

Change-Id: Ib87fdeb70ee7a930659563230a80cce0e1372c32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8370
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: HLT using immediate when checking for semihosting

HLT can use the immediate field when checking for semihosting,
rather than re-parsing it from the machInst variable.

Change-Id: I072cb100029da34d129b90c5d17e1728f9016c88
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8369
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly

This patch fixes the disassembly of AArch64 Exception Generating
instructions, which were not printing the encoded immediate field. This
has been accomplished by changing their underlying type to a newly
defined one.

Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8368
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-o3: Don't add non-speculative mem barriers to the IQ twice

There are cases where the IEW adds a non-speculative instruction to
the IQ twice. This can happen if an instruction is flagged as
IsMemBarrier and IsNonSpeculative. Avoid adding non-speculative
instructions in the IEW to the IQ by checking if it has been added
already.

Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8374
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: fix page_table bug for .fast build

Since b8b13206c8, the '.fast' build has failed to compile with an error
caused by a variable and an assert.

As a reminder, assert macros are optimized out of the build for '.fast'.
If an assert check requires a variable that is unused anywhere else in
the code, the compiler complains that the variable is unused and the
scons build fails. The solution is to add a M5_VAR_USED specifier to
tell the compiler to ignore the variable.

Change-Id: I38f6bbed1e4c0506c5bbc1206c21f1f7e3d8dfe6
Reviewed-on: https://gem5-review.googlesource.com/8462
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-riscv: Fix compressed branch op offset

There is a bug in RISC-V's compressed branch instructions where the
offsets are not stored in ImmOp's immediate field, causing incorrect
branchTarget() return values.  This patch adds a new compressed branch
op format, CBOp, which correctly stores the offset.

Change-Id: Iac6e9b091d63f3dce4717ee5a9ec31a7cbd6c377
Reviewed-on: https://gem5-review.googlesource.com/8441
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

arch-arm: Semihosting not available in syscall emulation

Arm Semihosting is not available in syscall emulation since we don't
have an Arm system in that scenario. Trying to use it in "se" mode will
make getArmSystem assertion fail.

Change-Id: I4cf49ae801ec6e6c93134ac6ae2a0f412040684c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8367
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>