radeon: Use PRINTLIKE macro.

configure.ac: Replace gallium_check_st with gallium_require_drm.

configure.ac: Drop gallium directory tracking.

Was only tracked to be printed at the end of configure, but configure
quits if it can't build something we requested, rather than silently
dropping it, so printing these directories has little use.

configure.ac: Use autoconf macro for GNU make.

ralloc: Mark ralloc functions with gcc's malloc attribute.

Cuts a few hundred bytes from the DRI drivers, so it must give gcc some
extra information.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Replace a priori knowledge of gcc attributes with configure tests.

Note that I had to add support for testing the packed attribute to
m4/ax_gcc_func_attribute.m4.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [C bits]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Replace a priori knowledge of gcc builtins with configure tests.

Presumbly this will let clang and other compilers use the built-ins as
well.

Notice two changes specifically:
   - in _mesa_next_pow_two_64(), always use __builtin_clzll and add a
     static assertion that this is safe.
   - in macros.h, remove the clang-specific definition since it should
     be able to detect __builtin_unreachable in configure.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [C bits]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/compaction: Document instruction compaction capabilities.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Emit ELSE/ENDIF JIP with type D on Gen 7.

The spec says the type must be W (JIP is 16-bits after all), but we've
been emitting it with a UD type all along and have experienced no
adverse effects. Changing the type to D allows ELSE and ENDIF
instructions to be compacted.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Support compaction of control flow instructions.

We're currently emitting compactable control flow instruction the wrong
types, preventing their compaction. The next patch will fix this and
actually enable compaction.

On chips that cannot compact control flow instructions, attempts to find
a match in the datatype table will fail.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Add support for G45.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965: Add BRW_OPCODE_NENOP for G45.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Add support for Gen5.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>

i965/compaction: Reduce size of compacted_counts[] array.

The array was previously indexed in units of brw_compact_inst (8-bytes),
but before compaction all instructions are uncompacted, so every odd
element was unused.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Use sizeof brw_inst/brw_compact_inst.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Increment offset in for loop.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/compaction: Make src_offset local to the for loop.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Remove unnecessary is-compacted? check.

Used to pass over previously compacted instructions in this loop, but no
longer. No point in checking.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/compaction: Don't set UIP on ELSE on Gen < 8.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/compaction: Rework 3-src compaction logic.

It may be possible to create a contrived example in which a 3-src
instruction would have been compacted on Gen < 8. I'd rather not
discover it in the wild.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/sf: Disable instruction compaction.

Currently a no-op, since instruction compaction isn't implemented for the
generations that have a programmable strips-and-fans unit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Set JumpCount, not JIP, on ENDIF on Gen 6.

Despite what the Sandybridge PRM says, ENDIF has Jump Count in <dst>,
not JIP in <src1>. (The same mistake appears about WHILE as well).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Use VertexArray, not _VertexArray, in array size expressions.

Both sizes are VERT_ATTRIB_MAX, so this has no effect.  But it drops a
few trivial uses of the derived state.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Set correct array element in vbo_exec_vtx_init.

I'm not familiar with this code, but this sure appears to be a typo.
It looks like the intent is to set each array element, not arrays[0]
each time.  Notably, the loop just below uses "array", not "arrays".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: mesa-stable@lists.freedesktop.org

mesa: Use proper structure for glGet*(GL_TEXTURE_COORD_ARRAY*).

The code in get.c that handles this uses ctx->Array.VAO->VertexAttrib,
which is a gl_vertex_attrib_array structure, not a gl_client_array.

The offsets of all fields happened to be the same in both structures, at
least on x86_64.  "Size," "Type," and "Stride" are obviously the same:
both structures start with the same fields, in the same order.

"Enabled" is dicier: there are different fields before it in both
structures, including pointer sized values which might need special
alignment.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: mesa-stable@lists.freedesktop.org

mesa: Remove some dead helper functions.

Dead since the _MaxElement removal, but these functions seemed generally
applicable, so I decided to remove them in a separate patch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

vc4: Compute max_index instead of trusting the rest of userspace.

max_index was coming from either the user telling us as part of
glDrawRangeElements, or from an incidental calculation as part of some
sort of primitive conversion fallback.  Sometimes, it was just set to the
default "I don't know" ~0 value.

If it wasn't set to the actual max index, then the kernel would reject the
draw call for allowing out-of-bounds VBO reads.  So, compute the max index
from the sizes of the VBOs, which isn't too expensive (unlike mapping and
reading the index buffer) and is reliable.

Fixes piglit vao-element-array-buffer.

vc4: Move shader record setup before the draw call.

The flush only happens after both are written, so we can do them in either
order.  This will let me compute max_index during the shader record setup.

i965/vec4: Call calculate_cfg() in test programs to avoid crashing.

Reported-by: Mark Janes <mark.a.janes@intel.com>

vc4: Add support for gl_PointCoord.

Fixes piglit glsl-fs-pointcoord, point-sprite, and fbo-gl_pointcoord.

vc4: Add support for point size setting.

This is the support for both the global and per-vertex modes.

vc4: Add support for line width setting.

I don't see piglit tests for it, but this should be better than not
emitting it at all.

vc4: Actually add support for polygon offset.

Setting the bit without setting the offset values is kind of useless.
Fixes piglit polygon-offset (but not polygon-mode-offset).

vc4: Fix swapped 565 dithering versus no-dithering render configs.

Fixes many 565 piglit tests (like fbo-generatemipmap-formats) that weren't
expecting dithering.

vc4: Add support for alpha test.

Fixes most of piglit fbo-alphatest-formats (but not RGB565/332).

freedreno/a3xx: initial texture border-color

Still some open questions.. and at any rate, no additional piglit passes
due to various wrap modes that we need to emulate in at least some
cases :-(

But it does fix some mystery page-faults.. So add some comments in the
code where there are things that we need to emulate or do more r/e, and
push as-is.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

util: use linear formats in util_blit_pixels()

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

util: simplify writemask parameters for util_blit_pixels()

Instead of separate color and Z/S writemasks, just have one writemask
parameter that takes a mask of the PIPE_MASK_[RGBAZS] flags.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

util: s/PIPE_TEX_MIPFILTER/PIPE_TEX_FILTER/ in u_blit code

PIPE_TEX_MIPFILTER_x is not legal for the pipe_sampler_state::
min/mag_img_filter fields.  But PIPE_TEX_MIPFILTER_x == PIPE_TEX_FILTER_x
so we were getting lucky.

This also makes the code consistent with u_blitter.c.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

mesa: remove EXT suffix from FBO error messages

And use pass caller="" for _mesa_FramebufferTexture().

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Drop _mesa_getenv() wrapper.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: Drop _mesa_bsearch() wrapper.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: Unifdef _WIN32_WCE.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: Unifdef _XBOX.

Inexplicably added in commit 36940429.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

configure.ac: Remove duplicate -DHAVE_PTHREAD.

It's also defined by the AX_PTHREAD macro.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

configure.ac: Stop checking for perl.

Added by commit a75c6163, but no longer used.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

configure.ac: Use test -a, rather than another test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: Use realloc() instead of _mesa_realloc() and remove the latter.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Remove duplicate _mesa_{init,free}_shader_state prototypes.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

gallivm: Wrap deleted inlcude in if HAVE_LLVM < 0x0306

This was missed in 8f4ee56.

i965: Add and use functions to get next/prev blocks.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Call insert and remove functions from exec_node directly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make instruction lists local to the bblocks.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/cfg: Add note about double-loop macros and break behavior.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Replace initialization loops with memset().

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/vec4: Don't iterate between blocks with inst->next/prev.

The register coalescing portion of this patch hurts three shaders in
Guacamelee by one instruction each, but examining the diff makes me
believe that what we were generating was (perhaps harmlessly) incorrect.

i965/fs: Don't iterate between blocks with inst->next/prev.

When instruction lists are per-basic block, this won't work.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/cfg: Add macros to iterate through a block given a starting point.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/fs: Make count_to_loop_end() use basic blocks.

When the instructions aren't in a flat list, this wouldn't have worked.
Also, this should be faster.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/vec4: Don't use instruction list after calculating the cfg.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/fs: Don't use instruction list after calculating the cfg.

The only trick is changing a break into a return true in register
coalescing, since the macro is actually a double loop, and break will do
something different than you expect. (Wish I'd realized that earlier!)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Remove now unneeded calls to calculate_cfg().

Now that nothing invalidates the CFG, we can calculate_cfg() immediately
after emit_fb_writes()/emit_thread_end() and never again.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Remove cfg-invalidating parameter from invalidate_live_intervals.

Everything has been converted to preserve the CFG.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Preserve the CFG in instruction scheduling.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/vec4: Preserve CFG in spill_reg().

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/vec4: Preserve the CFG in a few more places.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/fs: Preserve the CFG in a few more places.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Restructure debug flags

This cleans up the debug flags to be consistently indented, use bit
shifting instead of hex-values and fixes a bug where the new DEBUG_NO8 flag
used the same value as the DEBUG_VUE flag.  This was hidden by the numbers not
being aligned.  Also removes gaps in the range where DEBUG_IOCTL (0x4) and
DEBUG_REGION (0x400) used to be.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

gallivm: Disable gallivm to fix build with LLVM 3.6

LLVM commit r218316 removes the JITMemoryManager class, which is
the parent for a seemingly important class in gallivm.  In order to
fix the build, I've wrapped most of lp_bld_misc.cpp in
if HAVE_LLVM < 0x0306 and modifyed the
lp_build_create_jit_compiler_for_module() function to return false
for 3.6 and newer which effectively disables the gallivm functionality.

I realize this is overkill, but I could not come up with a simple
solution to fix the build.  Also, since 3.6 will be the first release
without the old JIT, it would be really great if we could
move gallivm to use the C API only for accessing MCJIT.  There
is still time before the 3.6 release to extend the C API in
case it is missing some functionality that is required by gallivm.

gallium/rbug: correctly unreference a sampler view

This fixes heap corruption. The sampler view can be bound in the context,
so we cannot call destroy directly.

Reviewed-by: Brian Paul <brianp@vmware.com>

gallium/rbug: unlock a mutex in rbug_create_query

Reviewed-by: Brian Paul <brianp@vmware.com>

radeonsi: remove old cache flushing code

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi/compute: do CS partial flush with si_emit_cache_flush

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeonsi/compute: flush caches with si_emit_cache_flush

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeonsi/compute: directly emit CONTEXT_CONTROL

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeonsi: properly destroy the GS copy shader and scratch_bo for compute

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: release GS rings at context destruction

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: don't use pipe_constant_buffer for GS rings

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: don't pass the context to the shader translator

This should prevent accessing context state there.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: don't snoop currently-bound GS shader when compiling ES

Instead, pass the layout of GS inputs in memory to the ES using the shader
key. Only 64 bits are needed to represent the layout in the key.

Mixing and matching different VS and GS shaders should now always work.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: shorten si_pipe_* prefixes to si_*

This was the original naming convention in r600g and it somehow crept
into radeonsi.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: merge si_pipe_shader into si_shader

One is part of the other anyway.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: disable gl_SampleMask fragment shader output if MSAA is disabled

This fixes piglit: arb_sample_shading-builtin-gl-sample-mask 0

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: only update MSAA-specific framebuffer state if nr_samples is changed

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move DB_SHADER_CONTROL into db_render_state

I will need this for fixing sample shading with 1 sample.

The good news is that all shader pm4 states no longer use the current context
state, so we can generate the pm4 states outside of draw_vbo if needed.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set KILL_ENABLE during shader compilation, remove uses_kill flag

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: remove shader.ps_conservative_z, set db_shader_control instead

Also set the field on SI too. It's not just specific to CIK.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move DB registers from draw_vbo into new db_render_state

It's called db_misc_state in r600g.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: remove unused variable si_pipe_shader::sprite_coord_enable

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: document what si_descriptors.c does

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r300g: implement MSAA copies by resolving and upsampling

There's no other way. It will use hw resolve + blit.

st/mesa: redefine mapping from VARYING_SLOT_TEXi/PNTC/VARi to TGSI GENERIC[i]

Generic varyings in TGSI were based on the value of VARYING_SLOT_TEX0, so VAR0
was always GENERIC[22] (with tessellation patches). Some drivers might not
be able to cope with that.

This commit defines a proper mapping, so that PNTC is GENERIC[8] and VAR0 is
GENERIC[9].

Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: don't set coord_enable for gl_PointCoord if using TGSI_SEMANTIC_PCOORD

This was missed when Christoph Bumiller added PIPE_CAP_TGSI_TEXCOORD.

Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: use UniformBooleanTrue in glsl_to_tgsi

Just for consistency. This doesn't fix anything as the original code was
already pretty good.

Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: drop dependence on API profile in st_init_extensions

The extensions and limits being set in the conditional block are core-only
anyway and don't have any effect on other profiles.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: allow forcing >=3.1 compatibility contexts with MESA_GL_VERSION_OVERRIDE

E.g. the 4.0 compatibility profile can be forced with:

MESA_GL_VERSION_OVERRIDE=4.0COMPAT

Some tests that I have require 4.0 compatibility.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: don't set ES versions to GLSLVersion in _mesa_init_constants

No place in Mesa expects an ES version there.
Drivers don't even set it like this.

Reviewed-by: Brian Paul <brianp@vmware.com>

targets/vl: don't forget to set GALLIUM_STATIC_TARGETS

git rebase failure while dropping out a patch that reworks
the way we build aux/vl.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/egl: fold in target LDFLAGS variables

Both variables are identical thus we can fold them into AM_LDFLAGS.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

targets: drop the old MEGADRIVERS & STATIC_TARGET... variables

No longer used/needed as of last commit.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>