util: Rename PURE to ATTRIBUTE_PURE.

To avoid collission with windows.h's PURE macro.

We could consider eventually renaming to __pure, but that would require
further care, so it's left to the future.

Reviewed-by: Brian Paul <brianp@vmware.com>

egl/x11: Fix driver_name acquisition

We don't need to free driverName string from dri2 reply, on the other
hand, the driver name acquired from loader doesn't need duplication.

Fixes: 45e110bad9d (egl/x11: trust our loader over the xserver for the
drivername)

Reported-by: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: use brackets for both branches of conditional]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/skl: (trivial) Remove invalid comment about thread counts

This should have been a part of:
commit 7eaacc1678195738fab3bb98870828611cae066d
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Wed Jul 29 12:35:24 2015 -0700

    i965/skl: Add production thread counts and URB size

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

i965: Fix HW binding tables editing

Since the introduction of new gl_shader_stages in

commit a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler <fabianbieler@fastmail.fm>
Date:   Fri Mar 7 10:19:09 2014 +0100

    mesa: add tessellation shader enums

the translation table for the stage into the HW binding table edit
command was broken, and so we used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

egl/dri2: Fix include path of u_atomic.h introduced e7e29189

This was causing a failure to build on SCons due to a missing
-Isrc/egl. Instead of adding in that path, lets just -Isrc/
and include "utils/u_atomic.h".

Reviewed-by: Matt Turner <mattst88@gmail.com>

egl/x11: don't crash if dri2_dpy->conn is NULL

Identical to commit 60e9c35b3a0(egl/x11: bail out if we cannot fetch
the xcb connection) but for the swrast codepath.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/x11: auth with xserver before attempting to open the dri module

No real change, apart from keeping the calls to the underlying winsys
(x11) next to each other. Just like platform_wayland.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl/x11: trust our loader over the xserver for the drivername

This is a port of commit 7bd95ec437a(dri2: Trust our own driver name
lookup over the server's.) from glx/dri2.

v2: Add newline between code and multiline comment. (Matt)

Cc: Julien Isorce <julien.isorce@gmail.com>
Reported-by: Julien Isorce <julien.isorce@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl/x11: open the device from within dri2_x11_connect()

Allows us, with the next commit, to use alternative driver_name rather
than the one from xserver.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl/x11: fetch the device_name prior to driver_name

With the follow up commits we're about to further reshuffle things. Thus
we'll honour our our driver_name lookup (src/loader), and use the one
provided by xserver as a fall-back.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl/x11: remove dri2_dpy->conn checks

If the connection is NULL we won't be able to get here.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl/x11: bail out if we cannot fetch the xcb connection

The documentation of xcb_connection_has_error() does not mention
what will happen, if NULL is fed to the function.

Upon closer look (props to Matt), it seems that we'll crash as the
implementation dereferences conn.

This will also allow us to remove the dri2_dpy->conn checking with the
next commit.

v2: Reword commit message as per Matt's findings.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

vc4: add missing nir include, to fix the build

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: automake: remove unused include

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

clover: Stub missing CL 1.2 functions.

As sugested by Tom a long time ago
and in order to be able to create Piglit tests

v2:
replace NOT_SUPPORTED_BY_CL_1_1 macro with an inline function
remove extra space in clLinkProgram arg

v3:
use __func__

v4:
back to a macro, it make more sense to use it with __func__

[ Francisco Jerez: Rename to CLOVER_NOT_SUPPORTED_UNTIL and pass the
  minimum API version required by the entry point so the error
  messages don't become stale when support for additional CL versions
  is introduced. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

mesa: NULL check InfoLog

When a program is compiled, but linking failed the sh->InfoLog
could be NULL. This is expoloited by OpenGL ES 3.1 conformance tests.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costs

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructions

The dst is always written, in this case the predicate is only used to select
the value to write, so if we are spilling the dst we always want to write
whatever value we selected to scratch.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

glsl: remove stage ref generation for transform feedback

Stage ref cannot be queried for transform feedback.

Also simplify the build_stageref function by passing the
correct mode for uniforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

winsys/radeon: add a specific error message for cs_submit -> -ENOMEM

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/radeon: add an interface for contexts

Same idea as in libdrm_amdgpu.

A command stream can only be created for a specific context and it's always
submitted to that context.

This will mainly be used by amdgpu and it's required by the GPU reset status
query too.
(radeon only has a basic version of the query and thus doesn't need this)

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface

The timeout parameter covers both cases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: rename enable_s3tc -> enable_compressed_formats

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

gallium/radeon: add DRM and LLVM version to the renderer string

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: always flush framebuffer caches at the beginning of IBs

better safe than sorry

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi: don't count the exact needed CS space if the CS is large enough

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: don't crash when cleaning up after an incomplete context

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.

Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
needed to include no tiling at all, but the name
MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
confusion by replacing "ALLOC" with "TILING" in the identifiers.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Correct a mistake that always forced texture tiling.

Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.

The relevant enum values are

   MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5
   MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6
   MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
                                    MIPTREE_LAYOUT_ALLOC_XTILED
   MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7

so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can
never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR.

The enum this replaced was

   enum intel_miptree_tiling_mode {
      INTEL_MIPTREE_TILING_ANY,
      INTEL_MIPTREE_TILING_Y,
      INTEL_MIPTREE_TILING_NONE,
   };

where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the
unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine
MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Request a miptree with no tiling intel_miptree_map_blit().

Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

radeonsi: add a HUD query showing the number of shaders created

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: add a HUD query showing the number of compiler invocations

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: display cumulative results for some driver queries

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: switch the buffer-wait-time query to microseconds

This display the units in the HUD.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: change some driver query types to Hz

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/hud: automatically print % if max_value == 100

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/hud: fix printing % next to panes

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/hud: replace assertions with clamping the unit index

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium,hud: allow displaying cumulative values instead of average

The cumulative value is useful for queries like the number of shader
compilations.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/hud: fix printing byte units

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium,hud: add support for Hz units in driver queries

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: before storing tess levels, load them from LDS instead of temporary

Also use only one store if stride <= 4.
All the fetches from and stores to temporaries can be removed now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91461

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

winsys/radeon: loosen up the requirements for how much memory IBs can use

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: always use the llvm. prefix in intrinsic names

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeon/winsys: increase the IB size for VM

Luckily, there is a kernel query, so use the size from that.
It currently returns 256KB. It can be increased in the kernel.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: allow the winsys to choose the IB size

Picked from the amdgpu branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: suspend timer queries between IBs

When we are measuring the time spent in a draw call, an unexpected flush
can distort the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa: implement DrawTransformFeedbackStream

Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa: save which transform feedback buffer is associated with which stream

Reviewed-by: Dave Airlie <airlied@redhat.com>

vbo: pass the stream from DrawTransformFeedbackStream to drivers

Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()

If the new texture unit is the current texture unit, we can return
before error checking.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Lower arithmetic instructions with register regions of unsupported width.

This extends the SIMD lowering pass to enforce the hardware limitation
that no directly-addressed source may read more than 2 physical GRFs.
One can easily go over this limit when doing 64-bit arithmetic
(e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice
to be able to just emit an instruction of the intended execution size
from the visitor and let the lowering pass deal with this restriction
transparently.

Some hardware arithmetic instructions are not handled here, including
all instructions that use the accumulator implicitly (which the SIMD
lowering pass deliberately doesn't handle), instructions with
non-per-channel sources (e.g. LINE or PLANE) and SEND-like
instructions, which need special handling most likely as virtual
opcodes.

Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.

Otherwise it would crash on Gen8 with scalar VS.  The issue can easily
be reproduced with the following patch, but I don't see any reason why
it wouldn't be possible to end up with an ATTR argument here even
without it.

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/fs: Implement nir_op_imul/umul_high in terms of MULH.

And get rid of another no16() call.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Lower the MULH virtual instruction.

Translate MULH into the MUL/MACH sequence.  This does roughly the same
thing that nir_emit_alu() used to do but we can now handle 16-wide by
taking advantage of the SIMD lowering pass.  The force_sechalf
workaround near the bottom is required because the SIMD lowering pass
will emit instructions with non-zero quarter control and we need to
make sure we avoid that on integer arithmetic instructions with
implicit accumulator access due to a known hardware bug on IVB.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.

In order to make room for the code that will lower the MULH virtual
instruction.  Also move the hardware generation and execution type
checks into the same branch, they are going to have to be different
for MULH.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Lower 32x32 bit multiplication on BXT.

AFAIK BXT has the same annoying alignment limitation as CHV on the
source register regions of 32x32 bit MULs, give it the same treatment.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Define virtual instruction to calculate the high 32 bits of a multiply.

This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply.  Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Initialize patch member of glsl_struct_field

There is apparently a subtle difference in C++ between

    F f;

and

    F f();

The former will use the default constructor.  If there is no default
constructor specified, the compiler provides one that simply invokes the
default constructor for each field.  For built-in basic types, the
default constructor does nothing.  The later will, according to
http://stackoverflow.com/questions/2417065/does-the-default-constructor-initialize-built-in-types)
perform value-initialization of the type.  For built-in types this means
initializing to zero.

The per_vertex_accumulator constructor is:

    per_vertex_accumulator::per_vertex_accumulator()
       : fields(),
         num_fields(0)
    {
    }

This is the second form of constructor, so the glsl_struct_field
objects were previously zero initialized.  With the addition of an empty
default constructor in commit 7ac946e5, per_vertex_accumulator::fields
receive no initialization.

Fixes a bunch of random (mostly tessellation related) piglit failures
since commit 7ac946e5 ("glsl: Add constuctors for the common cases of
glsl_struct_field").

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91544
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir: add missing type to type_size_vec4()

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

mesa: Add missing check of format and type in glTexSubImageXD on GLES 3.0

Argument validation for glTexSubImageXD is missing a check of format and type
against texture object's internal format when profile is OpenGL-ES 3.0+.

This patch also groups together all format and type checks on GLES into a
new function texture_format_error_check_gles(), to factorize similar
code in texture_format_error_check().

Fixes 2 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.texsubimage2d
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal format

Page 161 of the OpenGL-ES 3.1 (PDF) spec, and page 207 of the OpenGL 4.5 (PDF),
both on section '8.6. ALTERNATE TEXTURE IMAGE SPECIFICATION COMMANDS', states:

    "An INVALID_ENUM error is generated if an invalid value is specified for
     internalformat".

It is currently returning INVALID_OPERATION error because
_mesa_get_read_renderbuffer_for_format() is called before the internalformat
argument has been validated. To fix this, we move this call down the validation
process, after _mesa_base_tex_format() has been called. _mesa_base_tex_format()
effectively serves as a validator for the internal format.

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.texture.copyteximage2d_invalid_format

Fixes 1 piglit test:
* spec@oes_compressed_etc1_rgb8_texture@basic

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>

mesa: Validate target before resolving tex obj in glTex(ture)SubImageXD

Currently, glTexSubImageXD attempt to resolve the texture object
(by calling _mesa_get_current_tex_object()) before validating the given
target. However, that method explicitly states that target must have been
validated before calling it, so it never returns a user error.

The target validation occurs later when texsubimage_error_check() is called.

This patch reorganizes target validation, taking it out from the error check
function and into a point before the texture object is resolved.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>

mesa: Fix errors values returned by glShaderBinary()

Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1,
and page 88 of the OpenGL 4.5 specs state:

    "An INVALID_VALUE error is generated if count or length is negative.
     An INVALID_ENUM error is generated if binaryformat is not a supported
     format returned in SHADER_BINARY_FORMATS."

Currently, an INVALID_OPERATION error is returned for all cases.

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.shader.shader_binary

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>

mesa: do not modify args when errors with GetProgramResourceName

Original purpose of these lines was to be more friendly against
GUI tools using the extension. However conformance suite explicitly
checks that buffers are not modified in error conditions.

Fixes:
   ES31-CTS.program_interface_query.buff-length

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

glsl: add variable mode check to build_stageref

Currently stage reference mask is built using the variable name
only. However it can happen that input of one stage has same name
as output from another stage. Adding check of variable mode makes
sure we do not pick wrong variable.

Fixes some subcases from
   ES31-CTS.program_interface_query.no-locations

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

dri: set the __DRI_API_OPENGL bit based on max gl compat version

This matches similar behaviour for the __DRI_API_OPENGL_CORE bit.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl: Add eglQuerySurface surface type check for EGL_LARGEST_PBUFFER attrib

Calling eglQuerySurface on a window or pixmap with the EGL_LARGEST_PBUFFER
attribute resulted in the contents of the 'value' parameter being modified.
This is the wrong behaviour according to the EGL spec, which states:

    "Querying EGL_LARGEST_PBUFFER for a pbuffer surface returns the
     same attribute value specified when the surface was created with
     eglCreatePbufferSurface. For a window or pixmap surface, the
     contents of value are not modified."

Avoid this from happening by checking that the surface type is EGL_PBUFFER_BIT
before modifying the contents of the parameter.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

egl/dri: Add error info needed for EGL_EXT_image_dma_buf_import extension

Update the DRI image interface error codes to reflect the needs of the
EGL_EXT_image_dma_buf_import extension. This means updating the existing error
code documentation and adding a new __DRI_IMAGE_ERROR_BAD_ACCESS error code
so that drivers can correctly reject unsupported pitches and offsets. Hook
the new error code up in EGL to return EGL_BAD_ACCESS.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: Use nir_lower_load_const_to_scalar().

nir: Add a nir_lower_load_const_to_scalar() pass.

This is useful to increase the CSE opportunities for a scalar backend.  It
avoids regressions when dropping vc4's custom CSE implementation.

v2: Cleanups by Matt (decl in the for loop, and unreachable()).
Reviewed-by: Matt Turner <mattst88@gmail.com>

vc4: Don't bother de-SSAing values that aren't part of phi webs.

We can just support them the same way we do load_const's SSA values.

nir: Add algebraic opt for no-op iand.

I lazily generated some of these in VC4 NIR lowering.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

vc4: Don't bother saturating the dst color for blending.

Since we just pulled it out of the destination as 8-bit unorm, we know
it's in [0, 1] already.

shader-db:
total instructions in shared programs: 100040 -> 98208 (-1.83%)
instructions in affected programs:     14084 -> 12252 (-13.01%)

vc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.

Previously, SFU values always moved to a temporary, and TLB color reads
and texture reads always lived in r4.  Instead, we can have these results
just be normal temporaries, and the register allocator can leave the
values in r4 when they don't interfere with anything else using r4.

shader-db results:
total instructions in shared programs: 100809 -> 100040 (-0.76%)
instructions in affected programs:     42383 -> 41614 (-1.81%)

vc4: Drop a dead prototype.

Revert "nir: Use a single bit for the dual-source blend index"

This reverts commit ab5b7a0fe659ff6f9c1885d5cb047b6531959506.  We use more
than one bit of value in tgsi_to_nir.

freedreno/a4xx: add independent blend function support

needed for MRT

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: MRT support

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: move the half-precision logic into core

Both a3xx and a4xx need the same logic to decide if half-precision can
be used for blit shaders.  So move it to core and simplify things a bit
with a helper that considers all render targets.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: simplify/cleanup resource status tracking

Collapse dirty/reading bools into status bitmask (and drop writing which
should really be the same as dirty).  And use 'used_resources' list for
all tracking, including zsbuf/cbufs, rather than special casing the
color and depth/stencil buffers.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: fix stream-out caps vec4->components

Should be in units of components, not vec4's

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: small bit of cleanup about max rendertargets

We hard-coded 4 or 8 as the max in various places.  Switch it all to a
define since the limit will go up with a4xx (and maybe even again in the
future?)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

glx: Use _mesa_lroundevenf() in glPixelStoref().

Functional change in which way half-way cases are rounded from towards
positive-infinity to even. The spec says "the passed value is rounded to
the nearest integer". Removes another case of bad half-up rounding.

util: Use SSE intrinsics in _mesa_lroundeven{f,}.

gcc actually generates this for us now that we use -fno-math-errno
(which is weird, since lrintf()/lrint() don't set errno) but clang still
does not. Presumably helps MSVC as well.

Reduced .text size by 8.5k with gcc before -fno-math-errno.

   text     data      bss      dec      hex  filename
4935850   195136    26192  5157178   4eb13a  i965_dri.so before
4927225   195128    26192  5148545   4e8f81  i965_dri.so after

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: Use _mesa_lroundevenf() in some more places.

vl/mpeg12: Silence GCC unused-variable warning.

vl/vl_mpeg12_bitstream.c: In function 'decode_slice':
vl/vl_mpeg12_bitstream.c:928:19: warning: unused variable 'extra' [-Wunused-variable]
          unsigned extra = vl_vlc_get_uimsbf(&bs->vlc, 1);
                   ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>

glsl: replace old hash table with new and faster one

The util/hash_table was intended to be a fast hash table
replacement for the program/hash_table see 35fd61bd99c1 and
72e55bb6888ff.

Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

glsl: Add constuctors for the common cases of glsl_struct_field

Fixes a giant pile of GCC warnings:

builtin_types.cpp:60:1: warning: missing initializer for member 'glsl_struct_field::stream' [-Wmissing-field-initializers]

I had to add a default constructor because a non-default constructor
was added.  Otherwise the only constructor would be the one with
parameters, and all the plases like

    glsl_struct_field foo;

would fail to compile.

I wanted to do this in two patches.  All of the initializers of
glsl_struct_field structures had to be converted to use the
constructor because C++ apparently forces you to do one or the other:

builtin_types.cpp:61:1: error: could not convert '{glsl_type::float_type, "near", -1, 0, 0, 0, GLSL_MATRIX_LAYOUT_INHERITED, 0, -1}' from '<brace-enclosed initializer list>' to 'glsl_struct_field'

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Make gen7_upload_ps_state static

It is only ever called from within the same file.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Remove extern declaration for nonexistent state atom

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Trivial formatting changes in gen7_vs_state.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Trivial formatting changes in gen6_multisample_state.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Trivial formatting changes in brw_misc_state.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Trivial formatting changes in brw_draw_upload.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Trivial formatting changes in brw_draw.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Trivial formatting changes in brw_wm.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965/nir: Do not scalarize phis in non-scalar setups

Significantly reduces register pressure in some piglit tests.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Handle uniform and GRF array access on vertex programs (NIR)

When the NIR-vec4 pass is enabled, handles uniform and GRF array access
on ARB_vertex_program like it is done on vertex shaders.

When the old IR-vec4 pass is used, emit_program_code() emits pull constant
loads directly instead of using relative addressing, hence to call to
move_uniform_array_access_to_pull_constants() is not needed and it is enough
to call to split_uniform_registers().

The patch also calls to move_grf_array_access_to_scratch() like it is
done for shaders, however I suspect this is a no-op for vertex programs and
we could remove it.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Handle uniforms on vertex programs

The implementation takes into account that on ARB_vertex_program
only a single nir variable is generated to support all the uniform data.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>