Jason Ekstrand [Tue, 24 Mar 2020 23:18:28 +0000 (18:18 -0500)]
anv: Return an error if allocating attachment memory fails
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
Samuel Pitoiset [Mon, 25 Nov 2019 14:51:03 +0000 (15:51 +0100)]
radv: advertise VK_AMD_memory_overallocation_behavior
Doom Eternal explicitly allows overallocation via this extension
but that shouldn't change anything because it's the default RADV
behavior.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
Samuel Pitoiset [Tue, 28 Apr 2020 11:10:56 +0000 (13:10 +0200)]
radv: track memory heaps usage if overallocation is explicitly disallowed
By default, RADV supports overallocation by the sense that it doesn't
reject an allocation if the target heap is full.
With VK_AMD_overallocation_behaviour, apps can disable overallocation
and the driver should account for all allocations explicitly made by
the application, and reject if the heap is full.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
Samuel Pitoiset [Tue, 28 Apr 2020 09:54:06 +0000 (11:54 +0200)]
radv: remove unused radv_device_memory::map_size field
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
Ian Romanick [Mon, 27 Apr 2020 19:11:17 +0000 (12:11 -0700)]
nir/algebraic: Require operands to iand be 32-bit
With the mask value 0x80000000, the other operand must be 32-bit. This
fixes failures in
dEQP-VK.subgroups.ballot_mask.ext_shader_subgroup_ballot.*.gl_subgroupgemaskarb_*
tests from Vulkan 1.2.2 CTS.
Checking one of the tests, it appears that the tests are doing 64-bit
iand with 0x0000000080000000, then comparing the result with zero.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2834
Fixes: 88eb8f190bd ("nir/algebraic: Simplify logic to detect sign of an integer")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4770>
Rob Clark [Tue, 28 Apr 2020 00:00:17 +0000 (17:00 -0700)]
freedreno/ir3/ra: only assign array base in first pass
In particular, we specifically don't want to let the base change between
passes, as it could end up conflicting with registers assigned in the
first pass.
Mostly-closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2838
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
Rob Clark [Mon, 27 Apr 2020 23:58:54 +0000 (16:58 -0700)]
freedreno/ir3/ra: split out helper for array assignment
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
Rob Clark [Mon, 27 Apr 2020 23:58:18 +0000 (16:58 -0700)]
freedreno/ir3/ra: use ir3_debug_print helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
Rob Clark [Mon, 27 Apr 2020 23:57:38 +0000 (16:57 -0700)]
freedreno/ir3/ra: remove unused variable
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
Rob Clark [Sun, 26 Apr 2020 17:51:50 +0000 (10:51 -0700)]
freedreno/computer: add script to test widening/narrowing
Just something I hacked together to help figure out which instructions
can fold in a wideing/narrowing conversion.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:46:33 +0000 (12:46 -0400)]
pan/bi: Add initial fcmp test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 18:16:26 +0000 (14:16 -0400)]
pan/bit: Interpret CMP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 18:16:16 +0000 (14:16 -0400)]
pan/bit: Prepare condition evaluation for vectors
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:41:14 +0000 (12:41 -0400)]
pan/bi: Relax double-abs condition
Only if both ports (<==> registers) same.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:39:47 +0000 (12:39 -0400)]
pan/bi: Pack fma.fcmp16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:39:21 +0000 (12:39 -0400)]
pan/bi: Factor out fp16 abs logic
Also used for fcmp16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:27:34 +0000 (12:27 -0400)]
pan/bi: Pack FMA 32 FCMP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:27:11 +0000 (12:27 -0400)]
pan/bi: Fix source mod testing for CMP
Outputs u32.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 15:44:51 +0000 (11:44 -0400)]
pan/bi: Structify ADD ICMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 15:40:22 +0000 (11:40 -0400)]
pan/bi: Structify FMA ICMP 16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 15:37:42 +0000 (11:37 -0400)]
pan/bi: Structify FMA ICMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 14:34:26 +0000 (10:34 -0400)]
pan/bi: Structify ADD FCMP16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 14:23:46 +0000 (10:23 -0400)]
pan/bi: Structify FMA FCMP16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Tue, 28 Apr 2020 16:46:24 +0000 (12:46 -0400)]
pan/bi Strucitfy ADD FCMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 18:38:18 +0000 (14:38 -0400)]
pan/bi: Structify FMA FCMP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 18:18:41 +0000 (14:18 -0400)]
pan/bi: Remove bi_round_op
No purpose.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 18:15:57 +0000 (14:15 -0400)]
pan/bi: Deduplicate csel/cmp cond
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 18:14:34 +0000 (14:14 -0400)]
pan/bi(t): Fix SELECT tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 17:33:21 +0000 (13:33 -0400)]
pan/bi: Add CSEL.8 opcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 17:30:11 +0000 (13:30 -0400)]
pan/bi: Add FCMP.GL.v2f16 on ADD opcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 17:29:56 +0000 (13:29 -0400)]
pan/bi: Add 64-bit int compares
Likewise.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 17:29:43 +0000 (13:29 -0400)]
pan/bi: Add some 8-bit compares
Not all but enough to see the pattern.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 17:29:25 +0000 (13:29 -0400)]
pan/bi: Add CSEL.64 opcode
Chain twice for full 64-bit CSEL.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Alyssa Rosenzweig [Mon, 27 Apr 2020 17:29:13 +0000 (13:29 -0400)]
pan/bi: Add bool->float opcodes
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
Samuel Pitoiset [Tue, 28 Apr 2020 08:08:17 +0000 (10:08 +0200)]
radv: enable FMASK for color attachments only
The reason behind this is that FMASK requires CMASK and also that
FMASK for non color attachments looks unnecessary. It's currently
much easier to add this simple check because the driver tries to
always enable DCC first and if we enable FMASK only if CMASK, we
might loose some FMASK compressions.
This helps fixing some new robustness2 tests which fails because
only FMASK is enabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4783>
Jason Ekstrand [Sat, 25 Apr 2020 00:07:44 +0000 (19:07 -0500)]
anv: Expose CS workgroup sizes based on a maximum of 64 threads
Otherwise, we'll hit asserts in brw_compile_cs.
Fixes: cf12faef614ab "intel/compiler: Restrict cs_threads to 64"
Closes: #2835
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4746>
Jason Ekstrand [Tue, 28 Apr 2020 03:43:42 +0000 (22:43 -0500)]
intel/devinfo: Compute the correct L3$ size for Gen12
Fixes: 8125d7960b6 "intel/dev: Add preliminary device info for Tigerlake"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4782>
Bas Nieuwenhuizen [Sat, 25 Apr 2020 23:52:44 +0000 (01:52 +0200)]
radv: Determine memory type for import based on fd.
This would be necessary for an application to figure out if the
memory was allocated using a memory type with VK_MEMORY_PROPERTY_PROTECTED_BIT.
It also allows one to determine VRAM vs. GTT etc.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
Bas Nieuwenhuizen [Sat, 25 Apr 2020 23:31:01 +0000 (01:31 +0200)]
radv/winsys: Add function to get domains/flags from fd.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
Bas Nieuwenhuizen [Sat, 25 Apr 2020 21:52:44 +0000 (23:52 +0200)]
radv: Stop using memory type indices.
Lots of extra coding was involved in managing them.
And for protected memory I was thinking of making a function that
goes from domain+flags to memory types, which can reuse this array.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
Bas Nieuwenhuizen [Sat, 25 Apr 2020 21:39:21 +0000 (23:39 +0200)]
radv: Use actual memory type count for setting app-visible bitset.
Otherwise we might make a bitset that is too large.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
Bas Nieuwenhuizen [Mon, 27 Apr 2020 22:40:12 +0000 (00:40 +0200)]
radeonsi: Count planes for imported textures.
For the DRI2 lowered YUV import separate pipe_resources get created
but in the end the first resource just gets asked for NPLANES.
Since
1) (Almost) everything uses the first resource + a plane index in the
Gallium interface.
2) This mirrors non-imported textures.
lets fix this in the driver.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4779>
Gert Wollny [Wed, 15 Apr 2020 14:59:46 +0000 (16:59 +0200)]
r600: Enable tesselation for NIR
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:58:11 +0000 (16:58 +0200)]
r600/sfn: Add tesselation shaders
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:56:35 +0000 (16:56 +0200)]
r600/sfn: Add lowering passes for Tesselation IO
Lower the input and output intrinsics to r600 specific LDS intrinsics
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:53:09 +0000 (16:53 +0200)]
r600/sfn: Move removing of unused variables
It doesn't make sense to do this in the optimization loop
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:48:00 +0000 (16:48 +0200)]
r600/sfn: Handle LDS output in VS
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:43:22 +0000 (16:43 +0200)]
r600/sfn: derive the GS from the vertex stage for a common interface
The GS can also provide the primid
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:40:49 +0000 (16:40 +0200)]
r600/sfn: extract class to handle the VS export to different stages
This code can be shared with the TESS_EVAL shader
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:36:10 +0000 (16:36 +0200)]
r600/sfn: Move some shader base methods to the public interface
This will be needed for handling the VS stage export better.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 15:05:48 +0000 (17:05 +0200)]
r600/sfn: Add methods to valuepool to get a vector of values
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 15:03:59 +0000 (17:03 +0200)]
r600/sfn: Move emission of barrier from compute shader to shader base
Tess shaders also use these barriers.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 15:03:10 +0000 (17:03 +0200)]
r600/sfn: Emit some LDS instructions
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 15:00:28 +0000 (17:00 +0200)]
r600/sfn: Handle umul24 and umad24
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 14:59:47 +0000 (16:59 +0200)]
r600/sfn: Add IR instruction to fetch the TESS parameters
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 14:59:05 +0000 (16:59 +0200)]
r600/sfn: Add TF write instruction
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 14:58:05 +0000 (16:58 +0200)]
r600/sfn: Add LDS instruction to assembly conversion
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 14:56:35 +0000 (16:56 +0200)]
r600/sfn: Add LDS IO instructions to r600 IR
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:34:43 +0000 (16:34 +0200)]
r600/sfn: Don't emit inline constants in the r600 IR
This can be handled when lowering to assembly, and it makes testing
for indirect buffer and sampler access easier.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Wed, 15 Apr 2020 14:33:02 +0000 (16:33 +0200)]
r600/sfn: simplify UBO lowering pass
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Gert Wollny [Sun, 12 Apr 2020 14:42:07 +0000 (16:42 +0200)]
r600: Handle texcoord semantics in LDS index evaluation
With NIR the texcoord semantic is enabled, and hence we have to handle
index evaluation differently here.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
Christian Gmeiner [Mon, 27 Apr 2020 07:53:07 +0000 (09:53 +0200)]
ci: bare-metal: power down device after tests
Helps to save electricity.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4754>
Icecream95 [Sun, 26 Apr 2020 07:19:23 +0000 (19:19 +1200)]
panfrost: Fix GL_EXT_vertex_array_bgra
Previously, attributes would always use an RGBA swizzle, even if the
format was BGRA.
Fixes piglit tests bgra-sec-color-pointer and bgra-vert-attrib-pointer.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4752>
Dave Airlie [Mon, 27 Apr 2020 22:13:31 +0000 (08:13 +1000)]
ci: add llvmpipe paths to virgl rules
since llvmpipe changes will affect virgl
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4777>
Samuel Pitoiset [Wed, 22 Apr 2020 14:54:28 +0000 (16:54 +0200)]
radv: do not expose GTT as device local memory mostly for APUs
On APUs, the memory is unified (all heaps are equally fast) and
apps should count all memory heaps together. But some games like
Id Tech games (Youngblood and such) don't manage memory correctly
on APUs and they spill everything when one VRAM heap is full.
Instead of spilling buffers, they should just allocate new buffers
in the second heap but it seems like these games are confused if
two memory heaps have the DEVICE_LOCAL_BIT set.
This is probably a first step towards better memory management on
APUs but there is still some work to do if we want to run most apps
with a small dedicated VRAM (256MB or so).
This gives a huge boost for Id Tech games on APUs, and doesn't
seem to reduce Feral games performance.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4771>
Jan Zielinski [Mon, 27 Apr 2020 20:05:35 +0000 (22:05 +0200)]
gallium/swr: Fix LLVM 11 compilation issues
Changes needed to adapt to LLVM API changes in vector
and pointer types.
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4769>
Eric Anholt [Fri, 17 Apr 2020 19:02:37 +0000 (12:02 -0700)]
ci/freedreno: Add a test run of a few driver options.
This lets us get coverage of corner cases of the driver that are tricky to
force a testcase to hit. We don't want to do a full run of the CTS with
each option because that's a lot of runner time, so stack a bunch of
fractional runs in one test job to amortize the test run setup overhead.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
Eric Anholt [Fri, 17 Apr 2020 20:01:50 +0000 (13:01 -0700)]
ci: Clean up some excessive use of pipes in dEQP results processing.
Given that we use set -x in the script, this actually makes the user
experience of viewing logs nicer.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
Eric Anholt [Fri, 17 Apr 2020 19:58:59 +0000 (12:58 -0700)]
ci: Allow namespacing of dEQP run results files.
I want to do multiple runs of some bits of the CTS in one test job to test
some driver options, but I want to be able to see the results from any of
them.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
Eric Anholt [Fri, 17 Apr 2020 17:45:17 +0000 (10:45 -0700)]
freedreno: Fix calculation of the const buffer cmdstream size.
The HW packet requires padding the number of pointers you emit, and we
would assertion fail about running out of buffer space if the number of
UBOs to be uploaded was odd.
Fixes: b4df115d3f3c ("freedreno/a6xx: pre-calculate userconst stateobj size")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
Eric Anholt [Fri, 17 Apr 2020 19:39:32 +0000 (12:39 -0700)]
ci: Add sanity checking that dEQP gets the expected GL_RENDERER.
It's easy to get something wrong in the driver build or container or
something that results in falling back to swrast, and then your only clue
was runtime and how your failure cases suspiciously match a swrast
driver's.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
Eric Anholt [Fri, 17 Apr 2020 19:28:58 +0000 (12:28 -0700)]
ci: Enable --compact-display false on all dEQP runs.
We always want to see status updates happening in the logs, otherwise it
can like maybe your machine hung until the run actually completes.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
Mike Blumenkrantz [Mon, 27 Apr 2020 17:44:08 +0000 (13:44 -0400)]
zink: explicitly unref old fb object when setting new one
this object has a ref from being created, and its lifetime is expected to
be a single frame, so remove that initial ref when we expect to stop
using it
Closes: #2648
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4768>
Mike Blumenkrantz [Mon, 27 Apr 2020 16:48:08 +0000 (12:48 -0400)]
zink: remove framebuffer cache
this can only match when re-rendering identical frames, which is not a
typical case. the lack of cache eviction also leads to memory ballooning.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4768>
Bas Nieuwenhuizen [Wed, 12 Feb 2020 15:54:21 +0000 (16:54 +0100)]
st/dri: Set next in template instead of after creation. (v2)
This should prevent horrors like Iris has with the delayed calls
to iris_resource_finish_aux_import just because info is not
available at allocation time.
AFAICT all drivers just copy the template except radeonsi/r600
which reset the next pointer.
AFAICT there is also no other place we get a state tracker setting
next ptrs on a resource.
v2: Updated Gallium docs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3792>
Erik Faye-Lund [Fri, 24 Apr 2020 13:41:49 +0000 (15:41 +0200)]
mesa/st: call _mesa_initialize() early
This allows drivers to reliably do things like using the GLSL
type-system during initialization.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
Erik Faye-Lund [Fri, 24 Apr 2020 13:34:01 +0000 (15:34 +0200)]
mesa/main: one_time_init() -> _mesa_initialize()
This exposes the logic inside one_time_init() as _mesa_initialize(), so
drivers who needs to use functionality initialized in one_time_init
earlier if they need.
This means we can reliably use the GLSL type-system when compiling
driver built-in shaders.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
Erik Faye-Lund [Fri, 24 Apr 2020 13:27:13 +0000 (15:27 +0200)]
mesa/main: Do not pass context to one_time_init
There's no longer any reason to pass the context down to one_time_init,
because we always do the same thing regardless of the context, and we
don't change the context.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
Erik Faye-Lund [Fri, 24 Apr 2020 13:24:05 +0000 (15:24 +0200)]
mesa/main: do not init remap-table per api
This hasn't really been nessecary since
8386088e3dc ("dispatch: stop
using _mesa_create_exec_table_es1() for GLES1."), when we stopped
diverging the logic here based on the context-API. So let's simplify the
code a bit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
Erik Faye-Lund [Fri, 24 Apr 2020 12:47:23 +0000 (14:47 +0200)]
mesa/main: do not pass context to one-time extension init
_mesa_problem doesn't use the ctx argument for anything, so there's no
reason to pass it. This saves us from needing a context passed down this
code-path in the first place.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
Erik Faye-Lund [Fri, 24 Apr 2020 12:41:25 +0000 (14:41 +0200)]
mesa/main: do not store unrecognized extensions in context
We process extension overrides only when we initialize the first
context, which means that unrecognized extensions only appear in the
first context created.
Let's instead store them in a global array, so we can apply them to all
contexts. This has the added benefit of making the initialization of the
first context less special, which allows us to clean up code a bit more.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
Dave Airlie [Sun, 29 Mar 2020 23:38:38 +0000 (09:38 +1000)]
vulkan: add initial device selection layer. (v6.1)
This is code Bas has out of tree but I think mesa should be shipping it, and I've improved it.
Initially-written-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
v2: add infinite recursion fix (Bas)
v3: Fix wayland/xcb barrier, whitespace
v4: use a macro for getting apis, shorten some lines, use outarray
v5: rewrite in C, use hash_table/mutex.
v6: use once_init to init the mutex, fix freeing ht
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1766>
Eric Anholt [Fri, 24 Apr 2020 18:45:31 +0000 (11:45 -0700)]
freedreno/ir3: Add support for disasm of cat2 float32 immediates.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
Eric Anholt [Fri, 24 Apr 2020 18:40:40 +0000 (11:40 -0700)]
freedreno/ir3: Refactor out print_reg_src().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
Eric Anholt [Fri, 24 Apr 2020 17:36:41 +0000 (10:36 -0700)]
freedreno/ir3: Convert remaining disasm src prints to reginfo.
More lines of code, but they're much more intelligible.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
Eric Anholt [Thu, 23 Apr 2020 19:01:04 +0000 (12:01 -0700)]
freedreno/ir3: Add a unit test for our disassembler.
Makes sure that we can maintain consistent output from our disassembly as
we refactor. I've only included stuff that matches qcom's disasm so far.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
Eric Anholt [Fri, 24 Apr 2020 17:23:20 +0000 (10:23 -0700)]
freedreno/ir3: Print a space after nop counts, like qcom's disasm.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
Eric Anholt [Thu, 23 Apr 2020 21:01:59 +0000 (14:01 -0700)]
freedreno/ir3: Fix the disasm of half-float STG dests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
Eric Anholt [Wed, 22 Apr 2020 19:08:06 +0000 (12:08 -0700)]
ci: Enable GLES 3.1 testing on db820c (a530).
The driver exposes GLES3.1, so let's make sure we're not regressing its
featureset.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
Eric Anholt [Wed, 22 Apr 2020 18:48:44 +0000 (11:48 -0700)]
freedreno: Fix derivatives without texturing on a3xx-a5xx.
The shader variant tells us if we should set the PIXLODENABLE flag.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
Eric Anholt [Wed, 22 Apr 2020 18:30:38 +0000 (11:30 -0700)]
ci: Enable GLES3 testing on db410c/db820c (freedreno a306 and a530).
We haven't had it enabled due tointermittent failures. Those failures
are, as far as I can tell, due to GPU faults from buffer overflows where a
failing test in a thread stomps an otherwise passing thread's buffers. By
running deqp single-threaded, we can get more consistent failures, at the
cost of needing to do a tiny subset of the tests to keep runtime down.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
Eric Anholt [Wed, 22 Apr 2020 18:28:54 +0000 (11:28 -0700)]
ci: Drop redundant freedreno stage specification.
The source rules give us the stage.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
Jonathan Marek [Fri, 24 Apr 2020 18:28:58 +0000 (14:28 -0400)]
freedreno/ir3: run nir_lower_pack
This lowers pack_32_2x16/unpack_32_2x16 into the scalar versions of those
instructions.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4738>
Jonathan Marek [Fri, 24 Apr 2020 18:27:33 +0000 (14:27 -0400)]
nir: add pack_32_2x16_split/unpack_32_2x16_split lowering
The new option replaces the two other _split lowering options, since
there's no need for separate options.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4738>
Bas Nieuwenhuizen [Tue, 24 Mar 2020 16:59:26 +0000 (17:59 +0100)]
radv: Add WSI buffers to BO list only if they can be used.
Also reverse the BO list removal loop. This way typical WSI usage
should find the entry in O(active swapchains) iterations, which
should not be a performance issues. Tested with Doom(2106) which
found the entry in 1 iteration every time.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4306>
Bas Nieuwenhuizen [Tue, 24 Mar 2020 16:59:07 +0000 (17:59 +0100)]
vulkan/wsi: Add callback to set ownership of buffer.
For radv BO list pruning.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4306>
Samuel Pitoiset [Mon, 27 Apr 2020 09:01:24 +0000 (11:01 +0200)]
ac,radeonsi: fix compilations issues with LLVM 11
Latest LLVM replaced LLVMVectorTypeKind.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2826
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4755>
Jan Zielinski [Mon, 27 Apr 2020 11:34:59 +0000 (13:34 +0200)]
gallium/gallivm: remove unused header include for newer LLVM
In the top of the trunk LLVM (11) llvm/IR/CallSite.h header
has been removed. The file compiles without this include also
for LLVM 8, but I'm not sure about 9, 10, and older versions
so I disable it only for the latest LLVM
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4748>
Jan Zielinski [Sat, 25 Apr 2020 17:27:07 +0000 (19:27 +0200)]
gallium/gallivm: fix compilation issues with llvm 11
Top of the trunk LLVM removes old vector type
and introduces two new ones - one for fixed-width
and one for scalable vectors. This commit fixes
compilation issues by switching from LLVMVectorTypeKind
to LLVMFixedVectorTypeKind for new LLVM.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4748>
Alyssa Rosenzweig [Thu, 23 Apr 2020 23:12:43 +0000 (19:12 -0400)]
ir3: Use shared mediump output lowering
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4716>
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