cores/clock: add ECP5PLL

soc/interconnect/stream/gearbox: inverse bit order

soc/cores/spi_flash: add missing endianness parameter

platforms/avalanche: add IOStandard on ddram pins

build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification

build/microsemi/libero_soc: add additional_timing_constraints

build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper

platforms/avalanche: add package/speed to platform.device

build/microsemi/libero_soc: remove previous impl directory if exists

build/microsemi/libero_soc: give better names to pdc files: io/fp

build/microsemi/libero_soc: add additional_constraints

platforms/avalanche: fix ddram dq7

build/microsemi/libero_soc: add {} around port name.

utils/litex_read_verilog: fix generated indent on instance

soc/integration/soc_core: add csr_map_update function

Merge pull request #127 from cr1901/picorv32-data

libbase/crt0-picorv32: Add support for .data sections.

libbase/crt0-picorv32: Add support for .data sections.

build/sim/verilator: add trace parameter to enable tracer

soc_core: convert cpu_type="None" string to None

build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route

build/microsemi/common: add async reset synchronizer (using DFN1P0)

build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools

build/microsemi/libero_soc: add timing constraints support

boards/platforms/avalanche: fix swapped serial pins

boards/platforms/avalanche: rename rst to rst_n (active low reset)

build/microsemi/libero_soc: associate .pdc to place and route tool.

For constraint to be applied, we also to associate them with the tool that will use it.

test/test_targets: update

soc/interconnect/stream: add Gearbox

test: remove test_bitslip (integrated in migen)

utils: add litex_read_verilog utility

generate Migen's modules from verilog files

create utils directory and move the litex utils to it

build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.

build: add microsemi template for polarfire fpgas support

Merge pull request #126 from mithro/toolchain-fix

lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.

lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.

Fixes the following error;
```
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/ice40_hx8k_b_evn_base_lm32.lite/software/stub'
Traceback (most recent call last):
  File "./make.py", line 164, in <module>
    main()
  File "./make.py", line 148, in main
    vns = builder.build(**dict(args.build_option))
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
    toolchain_path=toolchain_path, **kwargs)
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
    **kwargs)
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
    create_clock_domains=False, **kwargs)
TypeError: convert() got an unexpected keyword argument 'toolchain_path'
```

soc_core: check for cpu before checking interrupt

cores/clock/S7: just reset the generated clock, not the PLL/MMCM

bios/main: fix typo on mor1kx

cpu/mor1kx: use clang only for linux variant

xilinx/vivado: fix migen merge

platforms: remove versaecp55g_sdram

build/xilinx/vivado: merge migen change

build: use default toolchain_path on all backend when passed value is None

generic_platform: use set for sources

build: merge more migen changes

platforms/versa_ecp5: import migen changes

targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis

build/lattice: import changes from migen

targets/versa_ecp5: increase sys_clk_freq to 50MHz

targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll

targets/ulx3s: for now revert to 25MHz clock/no pll

platforms/versa_ecp5: add ecp5 soc hat ios

Merge branch 'master' of github.com/enjoy-digital/litex

Merge pull request #125 from daveshah1/trellis_sdram

ecp5 soc hat wip

plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5

targets/ulx3s: get memtest working by disabling sdram refresh

Will need to be fixed...

soc/integration/soc_sdram: allow using axi interface with litedram

boards/platforms: add avalanche polarfire board ios definition

working on Versa-5G dram

Signed-off-by: David Shah <dave@ds0.me>

bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients

target/kcu105: add reset button

boards/platforms/kcu105: fix sdram/dq pin swap

Debugging ULX3S SDRAM

Signed-off-by: David Shah <dave@ds0.me>

bios/sdram: replace DDR3_MR1 constant with DDRX_MR1

boards/targets: add kcu105

Merge pull request #122 from daveshah1/trellis_ulx3s

Switch Trellis build to use LPF constraints; working on ULX3S

Merge pull request #124 from jfng/master

build/sim/verilator: don't use --threads when $(THREADS) is unset

build/sim/verilator: don't use --threads when $(THREADS) is unset

boards/platforms/kc705: add user_sma_mgt_refclk

Merge pull request #123 from cr1901/prv32-min

PicoRV32 Enhancements

libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time).

cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector.

libbase/crt0-picorv32: Ensure BSS is cleared on boot.

cores/clock: add with_reset parameter (default to True)

In some cases we want to generate the reset externally.

ulx3s: Connect SDRAM clock

Signed-off-by: David Shah <dave@ds0.me>

Fix Trellis build; ULX3S demo boots to BIOS

Signed-off-by: David Shah <dave@ds0.me>

trellis: Switch to using LPF for constraints

Signed-off-by: David Shah <dave@ds0.me>

boards/platforms/kcu105: add sfp_tx/rx definition

cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations).

cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.

build/lattice/prjtrellis: fix default toolchain_path

soc/cores/spi_flash: add endianness parameter

soc/interconnect/stream_packet: use reverse_bytes from litex.gen

gen: add common with reverse_bits/reverse_bytes functions

boards/targets/ulx3s: reduce l2_size

build/lattice/prjtrellis: fix typo

build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.

nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.

build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl

Merge pull request #121 from cr1901/patch-3

Update vivado.py

Update vivado.py

Fix regression which caused Vivado to not be run at all.

boards/targets: add ulx3s

boards/platforms: add ulx3s

build/lattice/prjtrellis: add inout support

build/lattice/common: add tristate support

boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed

simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g

build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis"

boards/targets/simple: add gateware-toolchain parameter

boards/platforms/versaecp55g: use ftdi serial pins

build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support

Merge branch 'master' of github.com/enjoy-digital/litex