David Shah [Fri, 15 Nov 2019 21:03:11 +0000 (21:03 +0000)]
ecp5: Use new autoname pass for better cell/net names
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Thu, 14 Nov 2019 17:03:44 +0000 (18:03 +0100)]
Merge pull request #1490 from YosysHQ/clifford/autoname
Add "autoname" pass and use it in "synth_ice40"
Clifford Wolf [Thu, 14 Nov 2019 11:10:12 +0000 (12:10 +0100)]
Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams
Python Wrappers: Expose global variables and allow logging to python streams
Clifford Wolf [Thu, 14 Nov 2019 11:07:25 +0000 (12:07 +0100)]
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
ice40: Support for post-place-and-route timing simulations
Clifford Wolf [Thu, 14 Nov 2019 10:57:53 +0000 (11:57 +0100)]
Merge branch 'makaimann-label-bads-btor'
Clifford Wolf [Thu, 14 Nov 2019 10:57:38 +0000 (11:57 +0100)]
Use cell name for btor bad state props when it is a public name
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 14 Nov 2019 10:52:41 +0000 (11:52 +0100)]
Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor
Clifford Wolf [Wed, 13 Nov 2019 12:41:16 +0000 (13:41 +0100)]
Add "autoname" pass and use it in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Wed, 13 Nov 2019 11:57:17 +0000 (11:57 +0000)]
Merge pull request #1488 from whitequark/flowmap-fixes
flowmap: fix a few crashes
Clifford Wolf [Wed, 13 Nov 2019 11:34:27 +0000 (12:34 +0100)]
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
Bugfix in fsm_detect
Clifford Wolf [Tue, 12 Nov 2019 16:31:30 +0000 (17:31 +0100)]
Update fsm_detect bugfix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Nov 2019 13:26:02 +0000 (14:26 +0100)]
Bugfix in fsm_detect
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Nov 2019 09:24:12 +0000 (10:24 +0100)]
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
Makai Mann [Tue, 12 Nov 2019 00:40:51 +0000 (16:40 -0800)]
Add an info string symbol for bad states in btor backend
whitequark [Tue, 12 Nov 2019 00:15:43 +0000 (00:15 +0000)]
flowmap: when doing mincut, ensure source is always in X, not X̅.
Fixes #1475.
whitequark [Mon, 11 Nov 2019 23:13:00 +0000 (23:13 +0000)]
flowmap: don't break if that creates a k+2 (and larger) LUT either.
Fixes #1405.
Miodrag Milanovic [Mon, 11 Nov 2019 14:41:33 +0000 (15:41 +0100)]
Fixed tests
Clifford Wolf [Mon, 11 Nov 2019 14:07:29 +0000 (15:07 +0100)]
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 10 Nov 2019 10:00:38 +0000 (11:00 +0100)]
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
Add CodingReadme section on script passes
Clifford Wolf [Thu, 7 Nov 2019 12:30:03 +0000 (13:30 +0100)]
Add check for valid macro names in macro definitions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Marcin Kościelnicki [Fri, 1 Nov 2019 14:00:15 +0000 (14:00 +0000)]
synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
Clifford Wolf [Mon, 4 Nov 2019 13:25:13 +0000 (14:25 +0100)]
Fix write_aiger bug added in
524af21
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 31 Oct 2019 09:46:20 +0000 (10:46 +0100)]
Add CodingReadme section on script passes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 27 Oct 2019 09:25:01 +0000 (10:25 +0100)]
Merge pull request #1393 from whitequark/write_verilog-avoid-init
write_verilog: do not print (*init*) attributes on regs
Clifford Wolf [Thu, 24 Oct 2019 10:13:37 +0000 (12:13 +0200)]
Improve naming scheme for (VHDL) modules imported from Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Thu, 24 Oct 2019 07:14:20 +0000 (08:14 +0100)]
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
Add BRAM and URAM mapping for UltraScale[+]
Clifford Wolf [Thu, 24 Oct 2019 07:14:03 +0000 (09:14 +0200)]
Add "verific -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Wed, 23 Oct 2019 17:44:34 +0000 (18:44 +0100)]
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Sun, 20 Oct 2019 09:24:47 +0000 (10:24 +0100)]
ice40: Support for post-pnr timing simulation
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 18 Oct 2019 13:02:57 +0000 (14:02 +0100)]
xilinx: Add URAM288 mapping for xcup
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 18 Oct 2019 12:24:19 +0000 (13:24 +0100)]
xilinx: Add support for UltraScale[+] BRAM mapping
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Tue, 22 Oct 2019 22:04:34 +0000 (00:04 +0200)]
Bugfix in smtio vcd handling of $-identifiers
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Marcin Kościelnicki [Tue, 8 Oct 2019 17:00:30 +0000 (17:00 +0000)]
xilinx: Support multiplier mapping for all families.
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
Clifford Wolf [Tue, 22 Oct 2019 15:36:54 +0000 (17:36 +0200)]
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
Clifford Wolf [Mon, 21 Oct 2019 11:35:31 +0000 (13:35 +0200)]
Add "verilog_defines -list" and "verilog_defines -reset"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 21 Oct 2019 10:39:28 +0000 (12:39 +0200)]
Fix handling of "restrict" in Verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Sun, 20 Oct 2019 09:30:41 +0000 (10:30 +0100)]
ecp5: Pass -nomfs to abc9
Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
Miodrag Milanović [Sat, 19 Oct 2019 06:58:02 +0000 (08:58 +0200)]
Merge pull request #1457 from xobs/python-binary-name
Makefile: don't assume python is called `python3`
Sean Cross [Sat, 19 Oct 2019 06:04:52 +0000 (14:04 +0800)]
Makefile: don't assume python is called `python3`
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
Miodrag Milanović [Fri, 18 Oct 2019 12:29:44 +0000 (14:29 +0200)]
Merge pull request #1454 from YosysHQ/mmicko/common_tests
Share common tests
Miodrag Milanovic [Fri, 18 Oct 2019 11:15:36 +0000 (13:15 +0200)]
fixed error
Miodrag Milanovic [Fri, 18 Oct 2019 10:50:24 +0000 (12:50 +0200)]
Unify verilog style
Miodrag Milanovic [Fri, 18 Oct 2019 10:33:35 +0000 (12:33 +0200)]
Common memory test now shared
Miodrag Milanovic [Fri, 18 Oct 2019 10:20:35 +0000 (12:20 +0200)]
Remove not needed tests
Miodrag Milanovic [Fri, 18 Oct 2019 10:19:59 +0000 (12:19 +0200)]
Share common tests
Miodrag Milanovic [Fri, 18 Oct 2019 09:18:53 +0000 (11:18 +0200)]
fix yosys path
Miodrag Milanovic [Fri, 18 Oct 2019 09:12:03 +0000 (11:12 +0200)]
Fix path to yosys
Miodrag Milanovic [Fri, 18 Oct 2019 09:06:12 +0000 (11:06 +0200)]
Moved all tests in arch sub directory
Miodrag Milanovic [Fri, 18 Oct 2019 09:00:27 +0000 (11:00 +0200)]
Add async2sync
Miodrag Milanović [Fri, 18 Oct 2019 08:54:35 +0000 (10:54 +0200)]
Merge pull request #1435 from YosysHQ/mmicko/efinix
Add tests for Efinix architecture (contd)
Miodrag Milanović [Fri, 18 Oct 2019 08:54:28 +0000 (10:54 +0200)]
Merge branch 'master' into mmicko/efinix
Miodrag Milanović [Fri, 18 Oct 2019 08:54:04 +0000 (10:54 +0200)]
Merge pull request #1434 from YosysHQ/mmicko/anlogic
Add tests for Anlogic architecture (contd)
Miodrag Milanović [Fri, 18 Oct 2019 08:53:56 +0000 (10:53 +0200)]
Merge branch 'master' into mmicko/anlogic
Miodrag Milanović [Fri, 18 Oct 2019 08:53:34 +0000 (10:53 +0200)]
Merge pull request #1421 from YosysHQ/eddie/pr1352
Add tests for ECP5 architecture (contd)
Miodrag Milanović [Fri, 18 Oct 2019 08:52:50 +0000 (10:52 +0200)]
Merge branch 'master' into eddie/pr1352
Miodrag Milanović [Fri, 18 Oct 2019 08:51:32 +0000 (10:51 +0200)]
Merge pull request #1420 from YosysHQ/eddie/pr1363
Add tests for Xilinx architecture (contd)
Miodrag Milanovic [Fri, 18 Oct 2019 07:13:06 +0000 (09:13 +0200)]
hierarchy - proc reorder
Miodrag Milanovic [Fri, 18 Oct 2019 07:06:43 +0000 (09:06 +0200)]
hierarchy - proc reorder
Miodrag Milanovic [Fri, 18 Oct 2019 07:04:02 +0000 (09:04 +0200)]
hierarchy - proc reorder
Miodrag Milanovic [Fri, 18 Oct 2019 06:06:57 +0000 (08:06 +0200)]
hierarchy - proc reorder
N. Engelhardt [Thu, 17 Oct 2019 19:33:54 +0000 (21:33 +0200)]
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
Miodrag Milanovic [Thu, 17 Oct 2019 15:24:53 +0000 (17:24 +0200)]
Make equivalence work with latest master
Miodrag Milanovic [Fri, 4 Oct 2019 07:41:45 +0000 (09:41 +0200)]
remove not needed top module
Miodrag Milanovic [Fri, 4 Oct 2019 07:39:34 +0000 (09:39 +0200)]
remove not needed top module
Miodrag Milanovic [Fri, 4 Oct 2019 07:39:22 +0000 (09:39 +0200)]
split muxes synth per type
Miodrag Milanovic [Fri, 4 Oct 2019 07:28:18 +0000 (09:28 +0200)]
Test dffs separetely
Miodrag Milanovic [Fri, 4 Oct 2019 07:24:22 +0000 (09:24 +0200)]
Split latches into separete tests
Miodrag Milanovic [Fri, 4 Oct 2019 07:19:17 +0000 (09:19 +0200)]
Fix formatting
Miodrag Milanovic [Fri, 4 Oct 2019 06:27:49 +0000 (08:27 +0200)]
Clean verilog code from not used define block
Miodrag Milanovic [Fri, 4 Oct 2019 06:24:37 +0000 (08:24 +0200)]
Removed alu and div_mod test as agreed, ignore generated files
Miodrag Milanovic [Fri, 4 Oct 2019 06:19:26 +0000 (08:19 +0200)]
Test per flip-flop type
Eddie Hung [Tue, 1 Oct 2019 02:57:26 +0000 (19:57 -0700)]
Add -assert
Eddie Hung [Mon, 30 Sep 2019 21:56:19 +0000 (14:56 -0700)]
Use built-in async2sync call as per #1417
Eddie Hung [Mon, 30 Sep 2019 21:38:06 +0000 (14:38 -0700)]
Update mul test to DSP48E1
Eddie Hung [Mon, 30 Sep 2019 21:20:47 +0000 (14:20 -0700)]
Update area for div_mod
Eddie Hung [Mon, 30 Sep 2019 21:17:59 +0000 (14:17 -0700)]
Add comment for lack of tristate logic pointing to #1225
Eddie Hung [Mon, 30 Sep 2019 21:16:45 +0000 (14:16 -0700)]
Move $x to end as
7f0eec8
SergeyDegtyar [Tue, 17 Sep 2019 08:53:49 +0000 (11:53 +0300)]
adffs test update (equiv_opt -multiclock)
Sergey [Thu, 12 Sep 2019 11:54:01 +0000 (14:54 +0300)]
Fix div_mod test
Sergey [Thu, 12 Sep 2019 10:58:49 +0000 (13:58 +0300)]
Fix div_mod test
Sergey [Thu, 12 Sep 2019 04:13:49 +0000 (07:13 +0300)]
Fix div_mod test
Sergey [Thu, 12 Sep 2019 03:24:18 +0000 (06:24 +0300)]
Fix div_mod test
Sergey [Wed, 11 Sep 2019 18:28:40 +0000 (21:28 +0300)]
Fix div_mod test
Sergey [Wed, 11 Sep 2019 17:34:22 +0000 (20:34 +0300)]
Fix div_mod test
SergeyDegtyar [Wed, 11 Sep 2019 14:01:19 +0000 (17:01 +0300)]
Add comment with expected behavior for latches,tribuf tests;Update adffs test
SergeyDegtyar [Tue, 10 Sep 2019 05:36:59 +0000 (08:36 +0300)]
Fix latches.ys test
SergeyDegtyar [Tue, 10 Sep 2019 05:11:56 +0000 (08:11 +0300)]
Remove xilinx_ug901 tests (will be moved to yosys-tests)
SergeyDegtyar [Tue, 10 Sep 2019 05:08:03 +0000 (08:08 +0300)]
Add smoke tests to tests/xilinx
SergeyDegtyar [Mon, 9 Sep 2019 05:49:29 +0000 (08:49 +0300)]
Add comments for unproven cells.
SergeyDegtyar [Mon, 9 Sep 2019 05:33:26 +0000 (08:33 +0300)]
Add tests for Xilinx UG901 examples
Clifford Wolf [Wed, 16 Oct 2019 12:44:38 +0000 (14:44 +0200)]
Merge pull request #1450 from YosysHQ/clifford/fixdffmux
Fix handling of init attributes in peepopt dffmux pattern
Clifford Wolf [Wed, 16 Oct 2019 09:40:32 +0000 (11:40 +0200)]
Fix dffmux peepopt init handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 16 Oct 2019 09:40:01 +0000 (11:40 +0200)]
Move GENERATE_PATTERN macro to separate utility header
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 16 Oct 2019 08:43:47 +0000 (10:43 +0200)]
Disable left-over log_debug in peepopt_dffmux.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 16 Oct 2019 07:06:57 +0000 (09:06 +0200)]
Fix parsing of .cname BLIF statements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 Oct 2019 22:00:27 +0000 (00:00 +0200)]
Add .blackbox support to blif front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Benedikt Tutzer [Tue, 15 Oct 2019 08:13:21 +0000 (10:13 +0200)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_wrappers/globals_and_streams
Clifford Wolf [Mon, 14 Oct 2019 14:49:15 +0000 (16:49 +0200)]
Merge pull request #1448 from YosysHQ/daveshah1-sv-experiments
Typedef support (with wrong syntax)
David Shah [Mon, 14 Oct 2019 13:05:54 +0000 (14:05 +0100)]
Merge pull request #1446 from YosysHQ/dave/ecp5-ioff
ecp5: Use IOLOGIC flipflops
Clifford Wolf [Mon, 14 Oct 2019 03:24:31 +0000 (05:24 +0200)]
Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <clifford@clifford.at>