kajoljain379 [Wed, 16 Jan 2019 11:39:56 +0000 (17:09 +0530)]
arch-power: Added Data and Instruction Interrupt Handler
Added data and instruction storage interrupr handler and
modify radixwalk.cc to check permissions and privileges of
both data and instrustion.
Change-Id: I5d3a820862cde7bd298f0b715777f069fb1e39d1
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
kajoljain379 [Wed, 16 Jan 2019 11:38:45 +0000 (17:08 +0530)]
arch-power: Added Radix Tree Page Table Entry
Change-Id: Ifde9fac352f8019247e8f5f7936c081a3b85d3ac
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
Kajol Jain [Tue, 11 Jun 2019 08:59:35 +0000 (14:29 +0530)]
arch-power: Added Illegal type Program interrupt support
Added suppot for illegal or unknown instruction type program
interrupt.
* Check if instruction is unknown or invalid and incase its unknown
raise Illegal type program interrupt.
* Added Illegal instruction interrupt handler.
Change-Id: Ib203cfc3542f47b9e0141a2a3f170dc6becf8a90
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
Kajol Jain [Wed, 12 Jun 2019 06:35:17 +0000 (12:05 +0530)]
arch-power: Added support for Program Interrupt
Added supoort for program interrupt for Privileged type instruction.
* Added flag IsPrivileged to check wheather instruction is
privileged or not.
* Define bit number to be set in MSR for corresponding interrupt.
* Added Program interrupt handler with privileged type interrupt handler.
* Add IsPrivileged flag in all privileged instructions
* Add checker for PR bit inorder to verify mode for privilege instructions
and raise interrupt if needed.
Change-Id: I2aeb1a603568a6f80cd074bf67d4a528ebb6a5bd
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
kajoljain379 [Sat, 12 Jan 2019 08:47:30 +0000 (14:17 +0530)]
arch-power: Added Logical Partitioning Control Register(LPCR) Register
Change-Id: Id9bf672007cc7dfdabc3a073d79715d74e1975ed
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
kajoljain379 [Sat, 12 Jan 2019 08:43:02 +0000 (14:13 +0530)]
arch-power: Added SystemCall Interrupt handler
Added system call interrupt handler.
Added handler calling in decoder file.
Change-Id: I80b99257fe4b96a1a286f17afcec28bb8a849b83
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
kajoljain379 [Sat, 12 Jan 2019 08:13:32 +0000 (13:43 +0530)]
arch-power: Modify Decrementer interrupt
Modify decrementer interrupt handler.
Change-Id: Ibafd535e7cb5faeb3d4f6c479893bb72f01f944c
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
kajoljain379 [Sat, 12 Jan 2019 08:08:36 +0000 (13:38 +0530)]
arch-power: Added enumeration for Interrupt PC state
Added enum to get address of required interrupt service routine.
Change-Id: I1c5e0c149b870c0a7b60e5935fb7b701b3bf3084
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
kajoljain379 [Sat, 12 Jan 2019 08:06:30 +0000 (13:36 +0530)]
arch-power: Initialize PC State
Initialize PC state to 0x100.
Change-Id: Id130d161e40d287dfb1a1f97d5e1d58dfa0f2303
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
Kajol Jain [Wed, 12 Jun 2019 07:02:59 +0000 (12:32 +0530)]
arch-power: Added function to modify MSR and SRR1 register
* Added general function to modify MSR and SRR1 register.
* Added macros to get mask for
* Set particular bit.
* Unset Bit.
Change-Id: I17b82f6ef7f7d8915f9c1320f99fc6f3f9ecaf74
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
Sandipan Das [Sat, 12 Jan 2019 07:10:57 +0000 (12:40 +0530)]
[PATCH] scons: Fix compilation issues with gcc-8.x
Change-Id: I9260578643eda6c4f84af8024b5d9ff575fc281d
Signed-off-by:Sandipan Das <sandipan@linux.ibm.com>
Phanikiran Harithas [Sun, 10 Jun 2018 12:15:05 +0000 (17:45 +0530)]
power: Add support for Radix Translation
Power ISA v3.0 introduces the Radix MMU in addition to the Hash MMU.
This patch adds support in gem5 for handling the Radix based address
translations when MSR[IR,DR] bits are set.
It also adds an example of a radix_walk.
Change-Id: I193f8d44f36b429997f7ffcb788a50544ba65a8c
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Phanikiran Harithas [Sun, 10 Jun 2018 10:41:41 +0000 (16:11 +0530)]
power: Add support for real-mode addressing (translation is off)
This patch adds support for executing programs which don't have the
translation support (MSR[IR, DR] = 0). With this change, we should be
able to run 64 little endian elf binaries executing previleged
instructions with translation off.
Change-Id: Iaa64a37676874cee1ed1a0591b51b5e842774b45
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 09:01:05 +0000 (14:31 +0530)]
power: Add support for handling the Decrementer Interrupt
This patch allows the programming of the decrementer device, which
will count down to zero. As of now, the decrement happens after every
instruction. When the decrementer value hits 0, the CPU is delivered a
decrementer interrupt.
[ego@linux.vnet.ibm.com: Fixed Conflicts in src/arch/power/interrupts.hh]
Change-Id: I3a863a8e2bca434d5a8139df662429d3e83a8542
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 08:33:04 +0000 (14:03 +0530)]
arch-power: Define more special purpose registers, mtspr,mfspr instructions
This patch defines more special purpose registers taking their count
to 49.
This also defines the mtspr and mfspr instructions to move the
contents to and from the these special purpose registers.
[ego@linux.vnet.ibm.com: Fixed conflicts in
src/arch/power/isa/decoder.isa,
src/arch/power/isa/operands.isa,
src/arch/power/registers.hh]
[kajoljain797@gmail.com: Fixed rfid, hrfid, mtmsr, mtmsrd instructions]
NOTE: Perhaps can be folded into the previous patch which introduces
CR, MSR, PTCR, etc.
Change-Id: I4dd6ba8c710c4c522fadc685b60fb039dfd0a743
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 08:19:58 +0000 (13:49 +0530)]
power: Added support for CR, XER, FPSR, MSR, PTCR Registers
Define Condition Register (CR), XER, FPSR, MSR, PTCR Registers
as miscelleneous registers.
In particular, annotate the bits of MSR and PTCR for future use.
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: I6f1490b1490e16f9095075f5cd0056894fbf6608
phanikiran [Sun, 10 Jun 2018 08:02:57 +0000 (13:32 +0530)]
Power: Add a minimal system configuration
[ego@linux.vnet.ibm.com: Fixeed conflicts in example/fs.py]
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: Idf6dad2ea3a7eef7bb3475c5abb2108690e59942
Sandipan Das [Thu, 7 Jun 2018 14:46:12 +0000 (20:16 +0530)]
arch-power: Update hello test program
This updates the hello test program binary to an equivalent
64-bit little endian executable. Since this binary is built
with a recent toolchain, the kernel version provided by the
uname system call is ramped up to be able to meet the minimum
version required by glibc. This binary also uses the readlink
system call and the Move From Time Base (mftb) instruction.
So, placeholder code is added for these.
Change-Id: I645b344e8582f938711b75488bd25899c374cca3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 14:37:02 +0000 (20:07 +0530)]
arch-power: Fix stack layout for 64-bit execution
This fixes the call stack layout by changing the size of the
auxiliary vector entries, each of which contain two 64-bit
values. Also, all base addresses for stack contents are now
considered to be 64 bits in order to prevent underflows during
program execution.
Users can now run statically-linked 64-bit ELF ABI v2 compliant
PowerPC LSB ELF executables in syscall emulation mode.
Change-Id: I256399d9344b1b101385e32ad8978325aec9844e
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 14:33:01 +0000 (20:03 +0530)]
arch-power: Add branch target address register instructions
This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it:
* Move To Target Address Register (mttar)
* Move From Target Address Register (mftar)
* Branch Conditional to Branch Target Address Register (bctar[l])
Change-Id: I5130a22040e30a05e963b1cc8d38abbed9a49edb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 14:30:41 +0000 (20:00 +0530)]
arch-power: Fix branch instructions
This fixes the following branch instructions in order to
support 64-bit addressing:
* Branch (b[l][a])
* Branch Conditional (bc[l][a])
* Branch Conditional to Link Register (bclr[l])
* Branch Conditional to Count Register (bcctr[l])
This also fixes disassembly generation for all of the above.
Change-Id: I7cad4e1b3b2945ab06c4ffc8c79842f1453c85ec
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:30:23 +0000 (19:00 +0530)]
arch-power: Add fixed-point doubleword rotate instructions
This adds the following rotate instructions:
* Rotate Left Doubleword Immediate then Clear Left (rldicl[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Clear (rldic[.])
* Rotate Left Doubleword then Clear Left (rldcl[.])
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
Change-Id: I27520314e738e5bed92bf07c1150943c9f83e881
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:20:10 +0000 (18:50 +0530)]
arch-power: Add fields for MD and MDS form instructions
This introduces the extended opcode fields and the fields
mb and me for MD and MDS form instructions.
Change-Id: I2c3366794ed42f5d31ba1d69e360c0ac67c74e06
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:16:02 +0000 (18:46 +0530)]
arch-power: Fix fixed-point word rotate instructions
This fixes the following rotate instructions:
* Rotate Left Word Immediate then And with Mask (rlwinm[.])
* Rotate Left Word then And with Mask (rlwnm[.])
* Rotate Left Word Immediate then Mask Insert (rlwimi[.])
For 64-bit execution, these instructions should perform rotate
operations on a 64-bit value formed by concatenating two copies
of the lower order 32 bits of the value in the source register.
This also fixes disassembly generation for all of the above.
Change-Id: Iccd8c6ad10a26d66dcecd64c8f1f8118ec8c1278
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:09:20 +0000 (18:39 +0530)]
arch-power: Add fixed-point doubleword shift instructions
This adds the following shift instructions:
* Shift Left Doubleword (sld[.])
* Shift Right Doubleword (srd[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
* Extend-Sign Word and Shift Left Immediate (extswsli[.])
Change-Id: Icd1f3efda715c5b8a7c7bc648ba29a8749e74695
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 12:48:50 +0000 (18:18 +0530)]
arch-power: Add fields for XS form instructions
This introduces the extended opcode field and the field
sh for XS form instructions.
Change-Id: I8f7cb3a2fda33b5b0076ffe12ffebeb5ec1c33a6
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 12:46:46 +0000 (18:16 +0530)]
arch-power: Fix fixed-point word shift instructions
This fixes the following shift instructions:
* Shift Left Word (slw[.])
* Shift Right Word (srw[.])
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
For 64-bit execution, these instructions should perform
shift operations on only the lower order 32 bits of the
source register instead of all 64 bits.
This also fixes disassembly generation for all of the above.
Change-Id: I18871486d74969244d474eaf0f9d810f06faf50a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 10:57:21 +0000 (16:27 +0530)]
arch-power: Add fixed-point logical bit permute instructions
This adds the following logical instructions:
* Bit Permute Doubleword (bpermd[.])
Change-Id: I1af329cd28871c00ebb0574e38a53bcd6a3b794c
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 10:46:01 +0000 (16:16 +0530)]
arch-power: Add fixed-point logical parity instructions
This adds the following logical instructions:
* Parity Word (prtyw)
* Parity Doubleword (prtyd)
Change-Id: Icb1737435dfabf9ac7b14ce1fcdf1c232289bf24
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 10:38:15 +0000 (16:08 +0530)]
arch-power: Add fixed-point logical population count instructions
This adds the following logical instructions:
* Population Count Bytes (popcntb)
* Population Count Words (popcntw)
* Population Count Doubleword (popcntd)
Change-Id: I946d1f8b270b4c75849cdfb7e413974ae8748494
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:39:04 +0000 (15:09 +0530)]
arch-power: Add fixed-point logical count zeros instructions
This adds the following logical instructions:
* Count Trailing Zeros Word (cnttzw[.])
* Count Leading Zeros Doubleword (cntlzd[.])
* Count Trailing Zeros Doubleword (cnttzd[.])
Change-Id: I4bcf090178d9241f230509ba55e8e58f5e7794ac
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:30:27 +0000 (15:00 +0530)]
arch-power: Add fixed-point logical extend sign instructions
This adds the following logical instructions:
* Extend Sign Word (extsw[.])
Change-Id: I610e84c2361b99b00ceef2170ede5b6dee8ec21b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:19:41 +0000 (14:49 +0530)]
arch-power: Fix fixed-point logical instructions
This fixes the following logical instructions:
* Extend Sign Byte (extsb[.])
* Extend Sign Halfword (extsh[.])
* Count Leading Zeros Word (cntlzw[.])
* Compare Bytes (cmpb)
This also fixes disassembly generation for all of the above.
Change-Id: I98873edf24db606d8de481aa18bcb809ad38d296
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:15:03 +0000 (14:45 +0530)]
arch-power: Add fixed-point compare instructions
This adds the following compare instructions:
* Compare Ranged Byte (cmprb)
* Compare Equal Byte (cmpeqb)
Change-Id: I44765b3a9a8f0a3d81ecd6984efce3fd01ba4b24
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 08:53:20 +0000 (14:23 +0530)]
arch-power: Fix fixed-point compare instructions
This fixes the following compare instructions:
* Compare (cmp)
* Compare Logical (cmpl)
* Compare Immediate (cmpi)
* Compare Logical Immediate (cmpli)
Instead of always doing a 32-bit comparison, these instructions
now use the length field to determine the type of comparison to
be done. The comparison can either be based on the lower order
32 bits or on all 64 bits of the values.
This also fixes disassembly generation for all of the above.
Change-Id: I6a9f783efa9ef2f2ef3c16eada61074d6f798a20
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:53:49 +0000 (12:23 +0530)]
arch-power: Add fixed-point doubleword arithmetic modulo instructions
This adds the following arithmetic instructions:
* Modulo Signed Doubleword (modsd)
* Modulo Unsigned Doubleword (modud)
Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:51:13 +0000 (12:21 +0530)]
arch-power: Add fixed-point doubleword arithmetic divide extended instructions
This adds the following arithmetic instructions:
* Divide Doubleword Extended (divde[o][.])
* Divide Doubleword Extended Unsigned (divdeu[o][.])
Change-Id: I535605fa6d32153054d259bcb14b952a26a1372a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:37:31 +0000 (12:07 +0530)]
arch-power: Add fixed-point doubleword arithmetic divide instructions
This adds the following arithmetic instructions:
* Divide Doubleword (divd[o][.])
* Divide Doubleword Unsigned (divdu[o][.])
Change-Id: Iedfa46ee482201a25dbc195ac5cb7f5f5e83c29b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:30:28 +0000 (12:00 +0530)]
arch-power: Add fixed-point doubleword multipy-add instructions
This adds the following arithmetic instructions:
* Multiply-Add Low Doubleword (maddld)
* Multiply-Add High Doubleword (maddhd)
* Multiply-Add High Doubleword Unsigned (maddhdu)
Change-Id: I09ecca9f3eb0abaf6b5a82a6d33d7f3e54b9837b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:25:23 +0000 (11:55 +0530)]
arch-power: Add fields for VA form instructions
This introduces the extended opcode field and the operand
field RC for VA form instructions.
Change-Id: I60d1bff6e7c7dd41e6fbe28a5f012b6fd66e7bc3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:23:03 +0000 (11:53 +0530)]
arch-power: Add fixed-point doubleword multiply instructions
This adds the following arithmetic instructions:
* Multiply Low Doubleword (mulld[o][.])
* Multiply High Doubleword (mulhd[.])
* Multiply High Doubleword Unsigned (mulhdu[.])
Change-Id: I505d94dc8e9711c575c94f75e10f7e05e1d05fdf
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:13:04 +0000 (11:43 +0530)]
arch-power: Add fixed-point arithmetic add instructions
This adds the following arithmetic instructions:
* Add PC Immediate Shifted (addpcis)
Change-Id: Id9de59427cbf8578fd75cbb7c98fb767d885d89a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:44:41 +0000 (11:14 +0530)]
arch-power: Add fields for DX form instructions
This introduces the extended opcode field and the fields
d0, d1 and d2 for DX form instructions.
Change-Id: Iac52bca39993e4a5f299f33d356e36037c516130
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:41:11 +0000 (11:11 +0530)]
arch-power: Add fixed-point word arithmetic modulo instructions
This adds the following arithmetic instructions:
* Modulo Signed Word (modsw)
* Modulo Unsigned Word (moduw)
Change-Id: I5590e569afb71dd429c473bd18c65457e2c49286
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:30:35 +0000 (11:00 +0530)]
arch-power: Add fixed-point word arithmetic divide extended instructions
This adds the following arithmetic instructions:
* Divide Word Extended (divwe[o][.])
* Divide Word Extended Unsigned (divweu[o][.])
Change-Id: I1b8321de569d1be466e9d84ca5047b0c4682a0e3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:24:51 +0000 (10:54 +0530)]
arch-power: Fix fixed-point arithmetic multiply and divide instructions
This fixes the following arithmetic instructions:
* Multiply Low Immediate (mulli)
* Multiply Low Word (mullw[o][.])
* Multiply High Word (mulhw[.])
* Multiply High Word Unsigned (mulhwu[.])
* Divide Word (divw[o][.])
* Divide Word Unsigned (divwu[o][.])
This also fixes disassembly generation for all of the above.
Change-Id: I46fd3751b86a7436a962f8b93f26d8343f215fed
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 04:54:28 +0000 (10:24 +0530)]
arch-power: Fix fixed-point arithmetic add and subtract instructions
This fixes the following arithmetic instructions:
* Add Immediate (addi)
* Add Immediate Shifted (addis)
* Add (add[o][.])
* Subtract From (subf[o][.])
* Add Immediate Carrying (addic)
* Add Immediate Carrying and Record (addic.)
* Subtract From Immediate Carrying (subfic)
* Add Carrying (addc[o][.])
* Subtract From Carrying (subfc[o][.])
* Add Extended (adde[o][.])
* Subtract From Extended (subfe[o][.])
* Add to Zero Extended (addze[o][.])
* Subtract From Zero Extended (subfze[o][.])
* Negate (neg[o][.])
This also fixes disassembly generation for all of the above.
Change-Id: I431020a3f8b8610d6e18d1450848a50f477912cb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:48:00 +0000 (03:18 +0530)]
arch-power: Add fixed-point store conditional instructions
This adds the following store instructions:
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Doubleword Conditional Indexed (stdcx.)
Change-Id: I065113e817e2ae419a6f3231e645bacd95460607
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:44:13 +0000 (03:14 +0530)]
arch-power: Add fixed-point load and reserve instructions
This adds the following load instructions:
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Doubleword And Reserve Indexed (ldarx)
Change-Id: Iac3cf0e16e2b5da8b772be81850419e21f26bdab
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:41:17 +0000 (03:11 +0530)]
arch-power: Add fixed-point byte-reversed load and store instructions
This adds the following load and store instructions:
* Load Halfword Byte-Reverse Indexed (lhbrx)
* Load Word Byte-Reverse Indexed (lwbrx)
* Load Doubleword Byte-Reverse Indexed (ldbrx)
* Store Halfword Byte-Reverse Indexed (sthbrx)
* Store Word Byte-Reverse Indexed (stwbrx)
* Store Doubleword Byte-Reverse Indexed (stdbrx)
Change-Id: I9f211bb4e3007ca09002a9ba4e5afb4b2e67cddd
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:35:44 +0000 (03:05 +0530)]
arch-power: Add fixed-point doubleword load and store instructions
This adds the following load and store instructions:
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I57a95003b6c6cfc09cc40f9ac03b32a8dfd7b26d
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:27:03 +0000 (02:57 +0530)]
arch-power: Fix fixed-point load and store instructions
This fixes the following load and store instructions as a result
of the change in register widths:
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic (lwa)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes disassembly generation for all of the above.
Change-Id: I1a25cdb5ffe86145b7ffcf2c2bd7b27048a415d2
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:00:09 +0000 (02:30 +0530)]
arch-power: Introduce proper opcode fields
This introduces separate extended opcode fields for DS, X, XFL,
XFX, XL and XO form instructions and renames the primary opcode
field from OPCODE to PO as listed in the Power ISA manual.
Scenarios where multiple instructions of different forms share
the same primary opcode have also been addressed by using the
correct extended opcode fields for decoding.
Change-Id: I4a01820f6a6326ef79330221b717952c6b9cbba3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 19:48:55 +0000 (01:18 +0530)]
arch-power: Reorder instruction decoding logic
This reorders the decoding logic based on the category of
instructions. The ordering applied here is roughly in line
with the Power ISA manual which is as follows:
* Branch facility instructions
* Branch instructions
* Condition Register instructions
* System Call instructions
* Fixed-point facility instructions
* Load instructions
* Store instructions
* Arithmetic instructions
* Compare instructions
* Logical instructions
* Rotate and Shift instructions
* Move To/From System Register instructions
* Floating-point facility instructions
* Load instructions
* Store instructions
* Arithmetic instructions
* Move instructions
* Rounding and Conversion instructions
* Compare instructions
* Status and Control Register instructions
Change-Id: Icfb57c5e442a959e502222222b84289d8e74ecbf
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Mon, 4 Jun 2018 16:21:23 +0000 (21:51 +0530)]
arch-power: Make ELF interpreter read 64-bit LSB executables
This makes the ELF interpreter read 64-bit little endian (LSB)
PowerPC executables only. This drops support for the 32-bit big
endian (MSB) executables as the goal here is to enable a modern
64-bit execution environment for the Power ISA.
Change-Id: I0569f7e1d1e58ce874ec2d13291e7a758d56399f
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Mon, 4 Jun 2018 15:02:28 +0000 (20:32 +0530)]
arch-power: Switch to 64-bit registers and operands
This increases the width of the general-purpose registers and some
of the other important registers to 64 bits. This is a prerequisite
for enabling a 64-bit execution environment and allows the register
operands provided in instructions to also be recognized as 64-bit.
Change-Id: I442315163a5029bbfb9d4b16b5e6decd3ab2d61b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Mon, 4 Jun 2018 14:57:40 +0000 (20:27 +0530)]
arch-power: Rename program counter registers
The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.
Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Mon, 4 Jun 2018 14:43:35 +0000 (20:13 +0530)]
arch-power: Simplify doubleword operand types
Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.
Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Daniel R. Carvalho [Tue, 17 Apr 2018 13:46:14 +0000 (15:46 +0200)]
mem-cache: Privatize extractSet
Only BaseSetAssoc uses extractSet(). Besides, skewed caches need
the way information to know which set an address is located at.
Change-Id: Id222e907dc550d053018561bb2683cfc415471ec
Reviewed-on: https://gem5-review.googlesource.com/9962
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Mon, 16 Apr 2018 13:36:33 +0000 (15:36 +0200)]
mem-cache: Create an address aware TempCacheBlk
tempBlock has its member variables manually set in order to allow
it to be used in the block address regeneration function. This is
not necessary, and ti can be simply given the address, so it does
not need to be aware of set and tag. This will simplify
implementation of sector and skewed caches.
Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6
Reviewed-on: https://gem5-review.googlesource.com/9961
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Thu, 31 May 2018 10:09:39 +0000 (12:09 +0200)]
mem-cache: Fix secure bit modification
Secure bit was being updated outside insertion.
Change-Id: I83d9b010e8cf64013bbea9bae3ea68b0c414a189
Reviewed-on: https://gem5-review.googlesource.com/10622
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Wed, 30 May 2018 10:54:57 +0000 (11:54 +0100)]
mem-cache: Replace block visitor with std::function
This change modifies forEachBlk tags function to accept std::function
as parameter. It also adds an anyBlk tags function that given a
condition, it iterates through the blocks and returns whether the
condition is met.
Finally, it uses forEachBlk to implement the print, computeStats and
cleanupRefs functions that also work for the FALRU class.
Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10621
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Thu, 3 May 2018 11:14:41 +0000 (12:14 +0100)]
mem-cache: Fix include directives in the cache related classes
Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Mon, 5 Feb 2018 09:45:20 +0000 (09:45 +0000)]
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Nikos Nikoleris [Thu, 3 May 2018 14:51:41 +0000 (15:51 +0100)]
mem-cache: Move cache bypass mechanism to the ports
Cache bypass is necessary for cpu models like the KvmCPU. Previously
the bypass would happen at the cache classes. With this change the
bypassing happens directly at the ports.
Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62
Reviewed-on: https://gem5-review.googlesource.com/10432
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Fri, 2 Feb 2018 17:34:40 +0000 (17:34 +0000)]
mem-cache: Adopt a more sensible cache class hierarchy
This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b
Reviewed-on: https://gem5-review.googlesource.com/10431
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Fri, 4 May 2018 15:54:48 +0000 (16:54 +0100)]
mem-cache: Add helper function to perform evictions
Change-Id: I2df24eb1a8516220bec9b685c8c09bf55be18681
Reviewed-on: https://gem5-review.googlesource.com/10430
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Thu, 10 May 2018 10:49:09 +0000 (11:49 +0100)]
mem-cache: Delegate block invalidation to block allocation
For a block replacement we first select a victim block, we invalidate
it and then populate it with the new information. Prior to this change
BaseTags::insertBlock() did the invalidation and filled in the block
with the new information. Now that the replacements stat is moved to
the BaseCache, insertBlock does not need to perform the invalidation
and as a result we can unify the block eviction code in BaseCache.
Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3
Reviewed-on: https://gem5-review.googlesource.com/10429
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Nikos Nikoleris [Fri, 4 May 2018 14:57:44 +0000 (15:57 +0100)]
mem-cache: Refactor the recvAtomic function
The recvAtomic function in the cache handles atomic requests. Over
time, recvAtomic has grown in complexity and code size. This change
factors out some of its functionality in a separate functiona. The new
functions handles atomic requests that miss.
Change-Id: If77d2de1e3e802e1da37f889f68910e700c59209
Reviewed-on: https://gem5-review.googlesource.com/10425
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Wed, 2 May 2018 10:51:06 +0000 (11:51 +0100)]
mem-cache: Refactor the cache recvTimingReq function
The recvTimingReq function in the cache handles timing requests. Over
time, recvTimingReq has grown in complexity and code size. This change
factors out some of its functionality in two separate functions. The
new functions handle timing requests that hit and timing requests that
miss separately.
Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418
Reviewed-on: https://gem5-review.googlesource.com/10424
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Tue, 1 May 2018 13:26:14 +0000 (14:26 +0100)]
mem-cache: Refactor the cache recvTimingResp function
The recvTimingResp function in the cache handles timing
responses. Over time, recvTimingResp has grown in complexity and code
size. This change factors out some of its functionality to a separate
function. The new function iterates through the in-service targets and
handles them accordingly.
Change-Id: I0ef28288640f6be1b30452b0664d32432e692ea6
Reviewed-on: https://gem5-review.googlesource.com/10423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Thu, 31 May 2018 12:05:42 +0000 (14:05 +0200)]
mem-cache: Fix RandomReplData
Random replacement policy's data was being instantiated with
the incorrect class.
Change-Id: Ib573a6b5a63868d6069997c6279bec3b10c6b9b9
Reviewed-on: https://gem5-review.googlesource.com/10623
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Brandon Potter [Fri, 27 Apr 2018 18:56:11 +0000 (14:56 -0400)]
gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry
GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It
wrapped the class and included an extra member "valid". This member was
intended to report on the validity of the entry, however it introduced
bugs when folks forgot to set field properly in the code. So, instead of
keeping the extra field which we might forget to set, we track validity by
using nullptr for invalid tlb entries (as the tlb entries are dynamically
allocated). This saves on the extra class definition and prevents bugs
creeping into the code since the checks are intrinsically tied into
accessing any of the X86ISA::TlbEntry members.
This changeset fixes the issues introduced by
a8d030522,
a4e722725, and
2a15bfd79.
Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2
Reviewed-on: https://gem5-review.googlesource.com/10481
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Michael LeBeane [Fri, 27 Apr 2018 23:49:26 +0000 (19:49 -0400)]
dev: Exit correctly in dist-gem5 for SE mode
Do not allow the exit() syscall to terminate gem5 when running in dist-gem5
mode. The exit must be coordinated by the distributed interface instead.
Change-Id: I57f47610b59fe9e18ba3a1667fb5e45cecac1a81
Reviewed-on: https://gem5-review.googlesource.com/10461
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Mohammad Alian <m.alian1369@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Wed, 2 May 2018 13:41:22 +0000 (14:41 +0100)]
mem-cache: Determine if an MSHR has requests from another cache
To decide whether we allocate upon receiving a response we need to
determine if any of the currently serviced requests (non-deferred
targets) is comming from another cache. This change adds support for
tracking this information in the MSHR.
Change-Id: If1db93c12b6af5813b91b9d6b6e5e196d327f038
Reviewed-on: https://gem5-review.googlesource.com/10422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Wed, 9 May 2018 16:52:37 +0000 (17:52 +0100)]
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.
Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 9 May 2018 14:59:38 +0000 (15:59 +0100)]
arch-arm: Remove unusued MISCREG_A64_UNIMPL
In case the decoder fails to find a suitable MiscReg during a MSR/MRS
in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra
MISCREG_A64_UNIMPL register.
Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Mon, 14 May 2018 13:48:52 +0000 (14:48 +0100)]
arch-arm: MPIDR.MT = 1 in a multithreaded system
MPIDR.MT Indicates whether the lowest level of affinity consists of
logical PEs that are implemented using a multithreading type approach
Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10502
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 9 May 2018 16:56:03 +0000 (17:56 +0100)]
arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined
In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:
<op1> is in the range 0 - 7
<CRn> can take the values 11, 15
<CRm> is in the range 0 - 15
<op2> is in the range 0 - 7
Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Thu, 15 Feb 2018 15:15:22 +0000 (15:15 +0000)]
cpu: Avoid unnecessary dynamic_pointer_cast in atomic model
In the atomic model a dynamic_pointer_cast is performed at every tick to
check if the fault is a SyscallRetryFault. This was happening even when
there was no generated fault.
Change-Id: I7f4afeffffdf4f988230e05286602d8d9a919c6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10101
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 20 Apr 2018 08:50:29 +0000 (09:50 +0100)]
arch-arm: Implement ARMv8.1 TTBR1_EL2 register
This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for
getting the translation table base address when a Host Operating System
is running at EL2. (HCR_EL2.E2H = 1)
Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10382
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Mon, 9 Apr 2018 12:25:46 +0000 (13:25 +0100)]
arch-arm: Add E2H bit to HCR_EL2 System register
This patch adds the EL2 Host bit to the HCR_EL2 register. Enables a
configuration where a Host Operating System is running in EL2, and the
Host Operating System's applications are running in EL0.
Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10381
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Wed, 23 May 2018 23:47:31 +0000 (16:47 -0700)]
x86: Add op classes to the MediaOps.
The ISA parser had been assuming these microops were all FloatAddOp
which is usually not correct.
Change-Id: Ic54881d16f16b50c3d6a8c74b94bff9ae3b1f43e
Reviewed-on: https://gem5-review.googlesource.com/10541
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Tariq Azmy <tariqslayer01@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Wendy Elsasser [Tue, 28 Mar 2017 22:15:14 +0000 (17:15 -0500)]
mem: Add support for more flexible DRAM timing and topologies
This patch has 2 main aspects:
1) Add new parameter to adjust write-to-write delay
2) Enable support of more than 64 banks per controller
Changes for new parameter:
Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L.
This parameter can be used to set a unique delay between writes and
between reads.
To incorporate this parameter in the controller, modified the DRAMCtrl
class to have separate variables for read and write column delays.
Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS
as well as the new tCCD_L_WR parameter.
Changes to support more than 64 banks:
Modified the logic selecting the next command (reorderQueue
and minBankPrep functions). Replaced the unint64_t variables with
a vector of uint32_t elements. There is a uint32_t element defined
per ranks to allow up to 32 banks per rank. This will automatically
scale with ranks without issue.
Change will allow analysis of memory sub-systems beyond the current
landscape.
Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10103
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Wendy Elsasser [Fri, 7 Apr 2017 02:40:16 +0000 (21:40 -0500)]
mem: Optimize self-refresh entry
Self-refresh is entered during a refresh event, when the
rank was previously in a precharge power-down state.
The original code would enter self-refresh after a refresh
was issued. The device subsequently will issue a refresh
on self-refresh entry. On self-refresh exit, the controller
will issue another refresh command.
Devices require at least one additional refresh to be issued
between self-refresh exit and re-entry. This ensures that enough
refreshes occur in the case when the device narrowly missed a
refresh on self-refresh exit.
To minimize the number of refresh operations and still maintain
the device requirement, the current logic does the following:
1) The controller will still enter self-refresh from a refresh
event, when the previous state was precharge power-down.
However, the refresh itself will be bypassed and the controller
will immediately issue a self-refresh entry.
2) On a self-refresh exit, the controller will immediately
issue a refresh command (per the original logic). This ensures
the devices requirements are met and is a convenient way to
kick off the command state machine.
Change-Id: I1c4b0dcbfa3bdafd755f3ccd65e267fcd700c491
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10102
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Thu, 10 May 2018 10:44:47 +0000 (11:44 +0100)]
mem-cache: Move reference count stats update to blk invalidation
The tags in the cache keep track of the number of references to the
blocks as well as the average number of references between an
insertion and the next invalidation. Previously the stats where
updated only on block insertion and invalidations were ignored. This
changes moves the update of the counters to the block invalidation
function.
Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612
Reviewed-on: https://gem5-review.googlesource.com/10428
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Nikos Nikoleris [Thu, 10 May 2018 10:38:48 +0000 (11:38 +0100)]
mem-cache: Remove isTouched field from the CacheBlk
At the moment isTouched is used in the warm-up detection mechanism but
it keeps track of the same information as isValid(). This change
removes it and substitutes its use by isValid().
Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62
Reviewed-on: https://gem5-review.googlesource.com/10427
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Nikos Nikoleris [Thu, 10 May 2018 10:30:21 +0000 (11:30 +0100)]
mem-cache: Move replacements stat to the base cache class
Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110
Reviewed-on: https://gem5-review.googlesource.com/10426
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Tue, 15 May 2018 07:30:40 +0000 (08:30 +0100)]
base: Add M5 flag for [[nodiscard]] attribute
This change adds the M5_NODISCARD keyword to allow use of the
[[nodiscard]] attribute with compilers that support C++17. Currently,
C++17 is not a requirement and therefore the M5_NODISCARD has not
effect and does not break compilation for older compilers.
Change-Id: Ifc5c8f34764da3c7291066dcb2ff908c97738c3d
Reviewed-on: https://gem5-review.googlesource.com/10441
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Nikos Nikoleris [Tue, 1 May 2018 11:02:14 +0000 (12:02 +0100)]
mem-cache: Simplify writeback for the tempBlock in recvTimingResp
When we use the tempBlock to fill-in, we have to write it back and
invalidate it at the end of current transaction. This patch simplifies
the writeback flow by treating it as a regular writeback.
Change-Id: I257be7bbff211e2832ad001a4e991daf67704485
Reviewed-on: https://gem5-review.googlesource.com/10421
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Mon, 26 Feb 2018 21:58:13 +0000 (21:58 +0000)]
arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE
SYS_GET_CMDLINE was declared as having 1 parameter when it is really
supposed to have two parameters.
Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8
Reported-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10022
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Andreas Sandberg [Wed, 21 Feb 2018 12:07:01 +0000 (12:07 +0000)]
arch-arm: Add support for semihosting STDIO redirection
The Arm Semihosting layer currently assumes that the guest application
shares STDIO with gem5. This makes it hard to distinguish application
output from gem5's output and makes it impossible to redirect STDIN
when running in interactive mode. Add support for custom STDIO
redirection when instantiating the Semihosting model.
Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10021
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tony Gutierrez [Fri, 27 Apr 2018 18:58:07 +0000 (14:58 -0400)]
style: fix amd license and style issues
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5
Reviewed-on: https://gem5-review.googlesource.com/10463
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tony Gutierrez [Thu, 3 May 2018 18:03:20 +0000 (14:03 -0400)]
gpu-compute: Cleanup the scheduler a bit
Change-Id: If2c626544f208e15c91be975dee9253126862ced
Reviewed-on: https://gem5-review.googlesource.com/10222
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Alec Roelke [Sun, 10 Dec 2017 19:15:51 +0000 (14:15 -0500)]
arch-riscv: Update CSR implementations
This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. As interrupts, faults, and privilege levels are not yet
supported, there are no meaninful side effects that are implemented.
Performance counters are also not yet implemented, as they do not have
specifications. Currently they act as cycle counters.
Note that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
based on privilege will come in a future patch.
Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
Reviewed-on: https://gem5-review.googlesource.com/7441
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Giacomo Travaglini [Wed, 2 May 2018 23:14:42 +0000 (00:14 +0100)]
sim: Remove trailing dot when assigning a master's name
This patch fixes the master's name allocation in the system. The error
was occurring when a submaster was not specified in getMasterId: a
trailing separation dot was still added to the master's name.
Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10301
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Andreas Sandberg [Tue, 20 Feb 2018 17:52:25 +0000 (11:52 -0600)]
base, dev: Fix port message for vnc and terminal
When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:
Listening for system connection on port 5900
Listening for system connection on port 3456
The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.
Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10026
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Matt Sinclair [Fri, 4 May 2018 05:53:07 +0000 (01:53 -0400)]
arch-x86, arch-power: fix calls to bits and insertBits
The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit. This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.
Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Daniel R. Carvalho [Fri, 13 Apr 2018 15:12:36 +0000 (17:12 +0200)]
mem-cache: Create block insertion function
Create a block insertion function to be used when inserting
blocks. This resets the number of references to 1 (the
insertion is taken into account), sets the insertion tick,
and set secure state.
Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e
Reviewed-on: https://gem5-review.googlesource.com/9824
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Wed, 25 Apr 2018 17:23:17 +0000 (18:23 +0100)]
arch-arm: Map ID_x_EL1 registers to AArch32 version
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those
registers must be initialized even when the highest Exception Level is
using AArch64.
Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
projects / gem5.git / log