mesa.git
7 years agoi965/vec4: fix scratch writes for 64bit data
Iago Toral Quiroga [Tue, 28 Jun 2016 10:03:09 +0000 (12:03 +0200)]
i965/vec4: fix scratch writes for 64bit data

Mostly the same stuff as usual: we ned to shuffle the data before we
write and we need to emit two 32-bit write messages (with appropriate
32-bit writemask channels set) for a full dvec4 scratch write.

v2: use byte_offset() instead of offset().

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix scratch reads for 64bit data
Iago Toral Quiroga [Tue, 28 Jun 2016 10:02:24 +0000 (12:02 +0200)]
i965/vec4: fix scratch reads for 64bit data

v2: Setup for a 64-bit scratch read by checking the type size of the
    correct register

v3: Use byte_offset() instead of offset()

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix scratch offset for 64bit data
Iago Toral Quiroga [Wed, 17 Feb 2016 09:05:02 +0000 (10:05 +0100)]
i965/vec4: fix scratch offset for 64bit data

A vec4 is 16 bytes and a dvec4 is 32 bytes so for doubles we have
to multiply the reladdr by 2. The reg_offset part is in units of 16
bytes and is used to select the low/high 16-byte chunk of a full
dvec4, so we don't want to multiply that part of the address.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: do not split scratch read/write opcodes
Iago Toral Quiroga [Tue, 28 Jun 2016 09:54:07 +0000 (11:54 +0200)]
i965/vec4: do not split scratch read/write opcodes

64-bit scratch read/writes require to shuffle data around so we need
to have access to the full 64-bit data. We will do the right thing
for these when we emit the messages.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Do not use DepCtrl with 64-bit instructions
Iago Toral Quiroga [Thu, 23 Jun 2016 08:40:47 +0000 (10:40 +0200)]
i965/vec4: Do not use DepCtrl with 64-bit instructions

The BDW PRM says that it is not supported, but it seems that gen7 is also
affected, since doing DepCtrl on double-float instructions leads to
GPU hangs in some cases, which is probably not surprising knowing that
this is not supported in new hardware iterations. The SKL PRMs do not
mention this restriction, so it is probably fine.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms
Iago Toral Quiroga [Thu, 23 Jun 2016 08:35:50 +0000 (10:35 +0200)]
i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms

v2:
   - Add Broxton as Intel's internal PRMs says that it is needed (Matt).

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: don't copy propagate misaligned registers
Samuel Iglesias Gonsálvez [Wed, 22 Jun 2016 13:13:45 +0000 (15:13 +0200)]
i965/vec4: don't copy propagate misaligned registers

This means we would copy propagate partial reads or writes and that can affect
the result.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: don't propagate single-precision uniforms into 4-wide instructions
Iago Toral Quiroga [Wed, 13 Jul 2016 07:11:35 +0000 (09:11 +0200)]
i965/vec4: don't propagate single-precision uniforms into 4-wide instructions

Otherwise we end up producing code that violates the register region
restriction that says that when execsize == width and hstride != 0
the vstride can't be 0.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Prevent copy propagation from violating pre-gen8 restrictions
Iago Toral Quiroga [Thu, 23 Jun 2016 06:34:53 +0000 (08:34 +0200)]
i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions

In gen < 8 instructions that write more than one register need to read
more than one register too. Make sure we don't break that restriction
by copy propagating from a uniform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: prevent copy-propagation from values with a different type size
Iago Toral Quiroga [Thu, 16 Jun 2016 11:41:48 +0000 (13:41 +0200)]
i965/vec4: prevent copy-propagation from values with a different type size

Because the meaning of the swizzles and writemasks involved is different,
so replacing the source would lead to different semantics.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: don't constant propagate 64-bit immediates
Connor Abbott [Thu, 13 Aug 2015 22:44:14 +0000 (15:44 -0700)]
i965/vec4: don't constant propagate 64-bit immediates

v2: Also check if the instruction source target is 64-bit. (Samuel)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Fix SSBO stores for 64-bit data
Iago Toral Quiroga [Fri, 12 Feb 2016 13:05:11 +0000 (14:05 +0100)]
i965/vec4: Fix SSBO stores for 64-bit data

In this case we need to shuffle the 64-bit data before we write it
to memory, source from reg_offset + 1 to write components Z and W
and consider that each DF channel is twice as big.

v2: use byte_offset() instead of offset().

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Fix SSBO loads for 64-bit data
Iago Toral Quiroga [Wed, 13 Jul 2016 11:34:55 +0000 (13:34 +0200)]
i965/vec4: Fix SSBO loads for 64-bit data

Same requirements as for UBO loads.

v2:
  - use byte_offset() instead of offset() (Iago)
  - keep the const. offset as an immediate like the original code did (Juan)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Fix UBO loads for 64-bit data
Iago Toral Quiroga [Wed, 13 Jul 2016 10:10:18 +0000 (12:10 +0200)]
i965/vec4: Fix UBO loads for 64-bit data

We need to emit 2 32-bit load messages to load a full dvec4. If only
1 or 2 double components are needed dead-code-elimination will remove
the second one.

We also need to shuffle the result of the 32-bit messages to form
valid 64-bit SIMD4x2 data.

v2:
 - use byte_offset() instead of offset() (Iago)
 - keep the const. offset as an immediate like the original code did (Juan)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Add a shuffle_64bit_data helper
Iago Toral Quiroga [Wed, 22 Jun 2016 09:44:15 +0000 (11:44 +0200)]
i965/vec4: Add a shuffle_64bit_data helper

SIMD4x2 64bit data is stored in register space like this:

r0.0:DF  x0 y0 z0 w0
r1.0:DF  x1 y1 z1 w1

When we need to write data such as this to memory using 32-bit write
messages we need to shuffle it in this fashion:

r0.0:DF  x0 y0 x1 y1
r0.1:DF  z0 w0 z1 w1

and emit two 32-bit write messages, one for r0.0 at base_offset
and another one for r0.1 at base_offset+16.

We also need to do the inverse operation when we read using 32-bit messages
to produce valid SIMD4x2 64bit data from the data read. We can achieve this
by aplying the exact same shuffling to the data read, although we need to
apply different channel enables since the layout of the data is reversed.

This helper implements the data shuffling logic and we will use it in
various places where we read and write 64bit data from/to memory.

v2 (Curro):
  - Use the writemask helper and don't assert on the original writemask
    being XYZW.
  - Use the Vec4 IR builder to simplify the implementation.

v3 (Iago):
  - Use byte_offset() instead of offset().

v3:
  - Fix typo (Matt)
  - Clarify the example and fix indention (Matt).

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: support multiple dispatch widths and groups in the IR builder.
Iago Toral Quiroga [Wed, 28 Sep 2016 11:03:00 +0000 (13:03 +0200)]
i965/vec4: support multiple dispatch widths and groups in the IR builder.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Lower 64-bit MAD
Iago Toral Quiroga [Wed, 8 Jun 2016 09:04:34 +0000 (11:04 +0200)]
i965/vec4: Lower 64-bit MAD

The previous patch made sure that we do not generate MAD instructions
for any NIR's 64-bit ffma, but there is nothing preventing i965 from
producing MAD instructions as a result of lowerings or optimization
passes. This patch makes sure that any 64-bit MAD produced inside the
driver after translating from NIR is also converted to MUL+ADD before
we generate code.

v2:
  - Use a copy constructor to copy all relevant instruction fields from
    the original mad into the add and mul instructions

v3:
  - Rename the lowering and fix commit log (Matt)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: do not emit 64-bit MAD
Iago Toral Quiroga [Wed, 8 Jun 2016 09:05:51 +0000 (11:05 +0200)]
i965/vec4/nir: do not emit 64-bit MAD

RepCtrl=1 does not work with 64-bit operands so we need to use RepCtrl=0.

In that situation, the regioning generated for the sources seems to be
equivalent to <4,4,1>:DF, so it will only work for components XY, which
means that we have to move any other swizzle to a temporary so that we can
source from channel X (or Y) in MAD and we also need to split the instruction
(we are already scalarizing DF instructions but there is room for
improvement and with MAD would be more restricted in that area)

Also, it seems that MAD operations like this only write proper output for
channels X and Y, so writes to Z and W also need to be done to a temporary
using channels X/Y and then move that to channels Z or W of the actual dst.

As a result the code we produce for native 64-bit MAD instructions is rather
bad, and much worse than just emitting MUL+ADD. For reference, a simple case
of a fully scalarized dvec4 MAD operation requires 15 instructions if we use
native MAD and 8 instructions if we emit ADD+MUL instead. There are some
improvements that we can do to the emission of MAD that might bring the
instruction count down in some cases, but it comes at the expense of a more
complex implementation so it does not seem worth it, at least initially.

This patch makes translation of NIR's 64-bit FMMA instructions produce MUL+ADD
instead of MAD. Currently, there is nothing else in the vec4 backend that emits
MAD instructions, so this is sufficient and it helps optimization passes see
MUL+ADD from the get go.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Skip swizzle to subnr in 3src instructions with DF operands
Iago Toral Quiroga [Wed, 1 Jun 2016 06:35:37 +0000 (08:35 +0200)]
i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands

We make scalar sources in 3src instructions use subnr instead of
swizzles because they don't really use swizzles.

With doubles it is more complicated because we use vstride=0 in
more scenarios in which they don't produce scalar regions. Also
RepCtrl=1 is not allowed with 64-bit operands, so we should avoid
this.

v2: Fix typo (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix indentation in pack_uniform_registers
Iago Toral Quiroga [Mon, 30 May 2016 07:08:04 +0000 (09:08 +0200)]
i965/vec4: fix indentation in pack_uniform_registers

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix pack_uniform_registers for doubles
Iago Toral Quiroga [Wed, 29 Jun 2016 08:49:47 +0000 (10:49 +0200)]
i965/vec4: fix pack_uniform_registers for doubles

We need to consider the fact that dvec3/4 require two vec4 slots.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: teach register coalescing about 64-bit
Iago Toral Quiroga [Mon, 18 Jul 2016 10:04:13 +0000 (12:04 +0200)]
i965/vec4: teach register coalescing about 64-bit

Specifically, at least for now, we don't want to deal with the fact that
channel sizes for fp64 instructions are twice the size, so prevent
coalescing from instructions with a different type size.

Also, we should check that if we are coalescing a register from another
MOV we should be writing the same amount of data in both operations, otherwise
we end up wiring more or less than the original instruction. This can happen,
for example, when we have split fp64 MOVs with an exec size of 4 that only
write one register each and then a MOV with exec size of 8 that reads both.
We want to avoid the pass to think that it can coalesce from the first split
MOV alone. Ideally we would like the pass to see that it can coalesce from both
split MOVs instead, but for now we keep it simple.

Finally, the pass doesn't support coalescing of multiple registers but in the
case of normal SIMD4x2 double-precision instructions they naturally write two
registers (one per vertex) and there is no reason why we should not allow
coalescing in this case. Change the restriction to bail if we see instructions
that write more than 8 channels, where the channels can be 32-bit or 64-bit.

v2:
 - Make sure that scan_inst and inst write the same amount of data.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/disasm: fix subreg for dst in Align16 mode
Iago Toral Quiroga [Wed, 25 May 2016 12:29:39 +0000 (14:29 +0200)]
i965/disasm: fix subreg for dst in Align16 mode

There is a single bit for this, so it is a binary 0 or 1 meaning
offset 0B or 16B respectively.

v2:
  - Since brw_inst_dst_da16_subreg_nr() is known to be 1, remove it
    from the expression (Curro)

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement access to DF source components Z/W
Iago Toral Quiroga [Mon, 18 Jul 2016 11:43:00 +0000 (13:43 +0200)]
i965/vec4: implement access to DF source components Z/W

The general idea is that with 32-bit swizzles we cannot address DF
components Z/W directly, so instead we select the region that starts
at the the 16B offset into the register and use X/Y swizzles.

The above, however, has the caveat that we can't do that without
violating register region restrictions unless we probably do some
sort of SIMD splitting.

Alternatively, we can accomplish what we need without SIMD splitting
by exploiting the gen7 hardware decompression bug for instructions
with a vstride=0. For example, an instruction like this:

mov(8) r2.x:DF r0.2<0>xyzw:DF

Activates the hardware bug and produces this region:

Component: x0   y0   z0   w0   x1   y1   z1   w1
Register:  r0.2 r0.3 r0.2 r0.3 r1.2 r1.3 r1.2 r1.3

Where r0.2 and r0.3 are r0.z:DF for the first vertex of the SIMD4x2
execution and r1.2 and r1.3 are the same for the second vertex.

Using this to our advantage we can select r0.z:DF by doing
r0.2<0,2,1>.xyxy and r0.w by doing r0.2<0,2,1>.zwzw without needing
to split the instruction.

Of course, this only works for gen7, but that is the only hardware
platform were we implement align16/fp64 at the moment.

v2: Adapted to the fact that we now do this after converting to
    hardware registers (Iago)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: translate 64-bit swizzles to 32-bit
Iago Toral Quiroga [Tue, 24 May 2016 09:01:27 +0000 (11:01 +0200)]
i965/vec4: translate 64-bit swizzles to 32-bit

The hardware can only operate with 32-bit swizzles, which is a rather
limiting restriction. However, the idea is not to expose this to the
optimization passes, which would be a mess to deal with. Instead, we let
the bulk of the vec4 backend ignore this fact and we fix the swizzles right
at codegen time.

At the moment the pass only needs to handle single value swizzles thanks to
the scalarization pass that runs before it.

Notice that this only works for X/Y swizzles. We will add support for Z/W
swizzles in the next patch, since they need a bit more work.

v2 (Sam):
  - Do not expand swizzle of 64-bit immediate values.

v3:
  - Do this after translation to hardware registers instead of doing it right
    before so we don't need the force_vstride0 flag (Curro).
  - Squashed patch that included FIXED_GRF in the list of register files that
    need this translation (Iago).
  - Remove swizzle assignments for VGRF and UNIFORM files in
    convert_to_hw_regs(), they will be set by apply_logical_swizzle() (Iago).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add a scalarization pass for double-precision instructions
Iago Toral Quiroga [Tue, 24 May 2016 07:20:51 +0000 (09:20 +0200)]
i965/vec4: add a scalarization pass for double-precision instructions

The hardware only supports 32-bit swizzles, which means that we can
only access directly channels XY of a DF making access to channels ZW
more difficult, specially considering the various regioning restrictions
imposed by the hardware. The combination of both things makes handling
ramdom swizzles on DF operands rather difficult, as there are many
combinations that can't be represented at all, at least not without
some work and some level of instruction splitting depending on the case.

Writemasks are 64-bit in general, however XY and ZW writemasks also work
in 32-bit, which means these writemasks can't be represented natively,
adding to the complexity.

For now, we decided to try and simplify things as much as possible to
avoid dealing with all this from the get go by adding a scalarization
pass that runs after the main optimization loop. By fully scalarizing
DF instructions in align16 we avoid most of the complexity introduced
by the aforementioned hardware restrictions and we have an easier path
to an initial fully functional version for the vector backend in Haswell
and IvyBridge.

Later, we can improve the implementation so we don't necessarily
scalarize everything, iteratively adding more complexity and building
on top of a framework that is already working. Curro drafted some ideas
for how this could be done here:
https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82

v2:
  - Use a copy constructor for the scalar instructions so we copy all
    relevant instructions fields from the original instruction.

v3: Fix indention in one switch (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: split double-precision SEL
Iago Toral Quiroga [Fri, 17 Jun 2016 06:47:29 +0000 (08:47 +0200)]
i965/vec4: split double-precision SEL

There is a hardware bug affecting compressed double-precision SEL
instructions in align16 mode by which they won't read predication mask
properly. The bug does not affect other predicated instructions
and it does not affect SEL in Align1 mode either. This was found
empirically and verified by Curro in the simulator.

Fix this by splitting double-precision SEL in Align16 mode to use an
execution size of 4.

v2: Check that the dst type is 64-bit, since we can have 16-wide single
    precision bcsel instructions that also write 2 registers.

v3: Replace bcsel by SEL in all the comments as bcsel is the nir opcode
but SEL is the actual assembly instruction (Matt).

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: teach cmod propagation about different execution sizes
Iago Toral Quiroga [Thu, 15 Sep 2016 09:30:32 +0000 (11:30 +0200)]
i965/vec4: teach cmod propagation about different execution sizes

We can't propagate the conditional modifier from one instruction to
another of a different execution size / group, since that would change
the channels affected by the conditional.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: teach CSE about exec_size, group and doubles
Iago Toral Quiroga [Thu, 16 Jun 2016 11:49:55 +0000 (13:49 +0200)]
i965/vec4: teach CSE about exec_size, group and doubles

v2: adapt to changes in offset()

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/disasm: print NibCtrl for instructions with execsize < 8
Iago Toral Quiroga [Fri, 17 Jun 2016 06:21:19 +0000 (08:21 +0200)]
i965/disasm: print NibCtrl for instructions with execsize < 8

v2 (Curro):
  - Print it also for execsize < 4.
  - QtrCtrl is still in effect, so print 2 * qtr_ctl + nib_ctl + 1
  - Do not read the nib ctl from the instruction in gen < 7,
    the field only exists in gen7+.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: dump NibCtrl for instructions with execsize != 8
Iago Toral Quiroga [Wed, 29 Jun 2016 06:40:27 +0000 (08:40 +0200)]
i965/vec4: dump NibCtrl for instructions with execsize != 8

v2: do it in the same fashion as the FS backend for consistency (Curro)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions
Iago Toral Quiroga [Fri, 17 Jun 2016 06:49:44 +0000 (08:49 +0200)]
i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions

From the HSW PRM, Command Reference, QtrCtrl:

   "NibCtrl is only allowed for SIMD4 instructions with a DF (Double Float)
    source or destination type."

v2: Assert that the type is DF (Samuel)
v3: Don't set the default group to 0 and then set it only for 4-wide
    instructions. Instead, assert that exec size and group are always
    a correct match and then always set the default group from the
    instruction. (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add a SIMD lowering pass
Iago Toral Quiroga [Mon, 29 Aug 2016 08:41:45 +0000 (10:41 +0200)]
i965/vec4: add a SIMD lowering pass

Generally, instructions in Align16 mode only ever write to a single
register and don't need any form of SIMD splitting, that's why we
have never had a SIMD splitting pass in the vec4 backend. However,
double-precision instructions typically write 2 registers and in
some cases they run into certain hardware bugs and limitations
that we need to work around by splitting the instructions so we only
write to 1 register at a time. This patch implements a SIMD splitting
pass similar to the one in the scalar backend.

Because we only use double-precision instructions in Align16 mode
in gen7 (gen8+ is fully scalar and gens < 7 do not implement fp64)
the pass should be a no-op on any other generation.

For now the pass only handles the gen7 restriction where any
instruction that writes 2 registers also needs to read 2 registers.
This affects double-precision instructions reading uniforms, for
example. Later patches will extend the lowering pass adding a few
more cases.

v2:
 - Move the simd lowering pass after the main optimization loop and
   run copy-propagation and dce if it reports progress (Curro)
 - Compute number of registers written instead of fixing it to 1 (Iago)
 - Use group from backend_instruction (Iago)
 - Drop assertion that checked that we only split 8-wide instructions
   into 4-wide. (Curro)
 - Don't assume that instructions can only be 8-wide, we might want
   to use 16-wide instructions in the future too (Curro)
 - Wrap gen7 workarounds in a conditional to ease adding workarounds
   for other gens in the future (Curro)
 - Handle dst/src overlap hazard (Curro)
 - Use the horiz_offset() helper to simplify the implementation (Curro)
 - Drop the assertion that checks that each split instruction writes
   exactly one register (Curro)
 - Use the copy constructor to generate split instructions with all
   the relevant fields initialized to the values in the original
   instruction instead of copying only a handful of them manually (Curro)

v3 (Iago):
 - When copying to a temporary, allocate the number of registers required
   for the copy based on the size written of the lowered instruction
   instead of assuming that all lowered instructions produce single-register
   writes
 - Adapt to changes in offset()

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965: move the group field from fs_inst to backend_instruction.
Iago Toral Quiroga [Thu, 25 Aug 2016 10:02:43 +0000 (12:02 +0200)]
i965: move the group field from fs_inst to backend_instruction.

Just like the exec_size, we are going to need this in the vec4 backend
when we implement a simd splitting pass.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add a horiz_offset() helper
Iago Toral Quiroga [Thu, 25 Aug 2016 08:02:45 +0000 (10:02 +0200)]
i965/vec4: add a horiz_offset() helper

This will come in handy when we implement a simd lowering pass in a
follow-up patch.

v2: use byte_offset()

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: handle 32 and 64 bit channels in liveness analysis
Juan A. Suarez Romero [Fri, 10 Jun 2016 11:55:00 +0000 (13:55 +0200)]
i965/vec4: handle 32 and 64 bit channels in liveness analysis

Our current data flow analysis does not take into account that channels
on 64-bit operands are 64-bit. This is a problem when the same register
is accessed using both 64-bit and 32-bit channels. This is very common
in operations where we need to access 64-bit data in 32-bit chunks,
such as the double packing and packing operations.

This patch changes the analysis by checking the bits that each source
or destination datatype needs. Actually, rather than bits, we use
blocks of 32bits, which is the minimum channel size.

Because a vgrf can contain a dvec4 (256 bits), we reserve 8
32-bit blocks to map the channels.

v2 (Curro):
  - Simplify code by making the var_from_reg helpers take an extra
    argument with the register component we want.
  - Fix a couple of cases where we had to update the code to the new
    way of representing live variables.

v3:
  - Fix indent in multiline expressions (Matt)
  - Fix comment's closing tag (Matt)
  - Use DIV_ROUND_UP(inst->size_written, 16) instead of 2 * regs_written(inst)
    to avoid rounding issues. The same for regs_read(i). (Curro).
  - Add asserts in var_from_reg() to avoid exceeding the allocated
    registers (Curro).

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
7 years agoi965/vec4: dump the instruction execution size
Iago Toral Quiroga [Mon, 30 May 2016 11:36:30 +0000 (13:36 +0200)]
i965/vec4: dump the instruction execution size

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: use the IR's execution size
Iago Toral Quiroga [Mon, 29 Aug 2016 08:45:47 +0000 (10:45 +0200)]
i965/vec4: use the IR's execution size

In the vec4 backend the generator sets to 8 the execution size for all
instructions by default, however, to implement 64-bit floating-point we
will need to split certain instruction into smaller sizes so we need the
IR to convey this information like we do in the scalar backend. This patch
uses the execution size from the vec4 IR.

We will use this feature in a later patch when we implement a SIMD
splitting pass.

v2:
  - Drop the assertion on the execution size being 8 or 4 (Curro)
  - Use exec_size from backend_instruction (Curro)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix regs_read() for doubles
Iago Toral Quiroga [Mon, 30 May 2016 11:20:31 +0000 (13:20 +0200)]
i965/vec4: fix regs_read() for doubles

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix size_written for doubles
Iago Toral Quiroga [Mon, 30 May 2016 11:31:25 +0000 (13:31 +0200)]
i965/vec4: fix size_written for doubles

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965: move exec_size from fs_instruction to backend_instruction
Iago Toral Quiroga [Thu, 25 Aug 2016 09:49:53 +0000 (11:49 +0200)]
i965: move exec_size from fs_instruction to backend_instruction

We are going to need this in the vec4 backend too.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: use the new helper function to create double immediates
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 11:35:30 +0000 (13:35 +0200)]
i965/vec4: use the new helper function to create double immediates

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add a helper function to create double immediates
Iago Toral Quiroga [Wed, 9 Mar 2016 15:37:33 +0000 (16:37 +0100)]
i965/vec4: add a helper function to create double immediates

Gen7 hardware does not support double immediates so these need
to be moved in 32-bit chunks to a regular vgrf instead. Instead
of doing this every time we need to create a DF immediate,
create a helper function that does the right thing depending
on the hardware generation.

v2 (Curro):
  - Use swizzle() and writemask() helpers and make tmp const.

v3 (Iago):
  - Adapt to changes in offset()

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix optimize predicate for doubles
Iago Toral Quiroga [Thu, 18 Feb 2016 08:24:16 +0000 (09:24 +0100)]
i965/vec4: fix optimize predicate for doubles

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement fsign() for doubles
Iago Toral Quiroga [Fri, 5 Feb 2016 09:12:57 +0000 (10:12 +0100)]
i965/vec4: implement fsign() for doubles

v2: use a MOV with a conditional_mod instead of a CMP, like we do in d2b, to skip
    loading a double immediate.

v3: Fix comment (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement d2b
Iago Toral Quiroga [Wed, 17 Feb 2016 12:08:47 +0000 (13:08 +0100)]
i965/vec4: implement d2b

v2 (Curro):
  - Generate the flag register with a MOV with conditional_mod instead of a CMP
    instruction, which has the benefit that we can skip loading a DF
    0.0 constant.
  - Avoid the PICK_LOW_32BIT + MOV by using the flag result and a
    SEL to set the boolean result.

v3:
  - Fix comment (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement d2i, d2u, i2d and u2d
Iago Toral Quiroga [Wed, 17 Feb 2016 10:12:19 +0000 (11:12 +0100)]
i965/vec4: implement d2i, d2u, i2d and u2d

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement HW workaround for align16 double to float conversion
Iago Toral Quiroga [Wed, 29 Jun 2016 11:08:25 +0000 (13:08 +0200)]
i965/vec4: implement HW workaround for align16 double to float conversion

From the BDW PRM, Workarounds chapter:

   "DF->f format conversion for Align16 has wrong emask calculation when
    source is immediate."

Notice that Broadwell and later are strictly scalar at the moment though, so
this is not really necessary.

v2: Instead of moving the immediate to a vgrf and converting from there, just
    convert the double immediate to float in the compiler and move the result
    to the destination (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add helpers for conversions to/from doubles
Iago Toral Quiroga [Wed, 29 Jun 2016 11:07:35 +0000 (13:07 +0200)]
i965/vec4: add helpers for conversions to/from doubles

Use these helpers to implement d2f and f2d. We will reuse these helpers when
we implement things like d2i or i2d as well.

v2:
- Rename the helpers (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Rename DF to/from F generator opcodes
Iago Toral Quiroga [Wed, 17 Feb 2016 09:32:05 +0000 (10:32 +0100)]
i965/vec4: Rename DF to/from F generator opcodes

The opcodes are not specific for conversions to/from float since we need
the same for conversions to/from other 32-bit types. Rename the opcodes
accordingly and change the asserts to check the size of the types involved
instead.

v2:
- Rename to VEC4_OPCODE_TO_DOUBLE and VEC4_OPCODE_FROM_DOUBLE (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix register allocation for 64-bit undef sources
Iago Toral Quiroga [Mon, 15 Feb 2016 09:07:42 +0000 (10:07 +0100)]
i965/vec4: fix register allocation for 64-bit undef sources

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: make opt_vector_float ignore doubles
Iago Toral Quiroga [Fri, 12 Feb 2016 12:10:06 +0000 (13:10 +0100)]
i965/vec4: make opt_vector_float ignore doubles

The pass does not support doubles in its current form.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations
Iago Toral Quiroga [Fri, 12 Feb 2016 07:47:21 +0000 (08:47 +0100)]
i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations

v2: Make dst_reg_for_nir_reg() handle this for nir_register since we
    want to have the correct type set before we call offset().

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: fix indentation in get_nir_src()
Iago Toral Quiroga [Wed, 5 Oct 2016 08:54:35 +0000 (10:54 +0200)]
i965/vec4: fix indentation in get_nir_src()

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: implement double comparisons
Iago Toral Quiroga [Thu, 13 Aug 2015 22:34:24 +0000 (15:34 -0700)]
i965/vec4/nir: implement double comparisons

v2:
- Added newline before if() (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement double packing
Iago Toral Quiroga [Wed, 1 Jun 2016 07:57:06 +0000 (09:57 +0200)]
i965/vec4: implement double packing

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: implement double unpacking
Iago Toral Quiroga [Wed, 1 Jun 2016 07:58:00 +0000 (09:58 +0200)]
i965/vec4: implement double unpacking

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: don't copy propagate vector opcodes that operate in align1 mode
Iago Toral Quiroga [Thu, 11 Feb 2016 13:19:58 +0000 (14:19 +0100)]
i965/vec4: don't copy propagate vector opcodes that operate in align1 mode

Basically, ALIGN1 mode will ignore swizzles on the input vectors so we don't
want the copy propagation pass to mess with them.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT
Iago Toral Quiroga [Wed, 24 Aug 2016 09:21:57 +0000 (11:21 +0200)]
i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT

These align1 opcodes do partial writes of 64-bit data. The problem is that we
want to use them to write on the same register to implement packDouble2x32 and
from the point of view of DCE, since both opcodes write to the same register,
only the last one stands and decides to eliminate the first, which is
not correct, so prevent this from happening.

v2: Make a helper in vec4_instruction to know if the instruction is an
    align1 partial write. This will come in handy when we implement a
    simd splitting pass in a later patch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
Iago Toral Quiroga [Fri, 17 Jun 2016 10:19:35 +0000 (12:19 +0200)]
i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes

These opcodes will set the low/high 32-bit in each 64-bit data element
using Align1 mode. We will use this to implement packDouble2x32.

We use Align1 mode because in order to implement this in Align16 mode
we would need to use 32-bit logical swizzles (XZ for low, YW for high),
but the IR works in terms of 64-bit logical swizzles for DF operands
all the way up to codegen.

v2:
 - use suboffset() instead of get_element_ud()
 - no need to set the width on the dst

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
Iago Toral Quiroga [Tue, 31 May 2016 08:17:37 +0000 (10:17 +0200)]
i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes

These opcodes will pick the low/high 32-bit in each 64-bit data element
using Align1 mode. We will use this, for example, to do things like
unpackDouble2x32.

We use Align1 mode because in order to implement this in Align16 mode
we would need to use 32-bit logical swizzles (XZ for low, YW for high),
but the IR works in terms of 64-bit logical swizzles for DF operands
all the way up to codegen.

v2:
 - use suboffset() instead of get_element_ud()
 - no need to set the width on the dst

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add dst_null_df()
Iago Toral Quiroga [Fri, 5 Feb 2016 09:11:48 +0000 (10:11 +0100)]
i965/vec4: add dst_null_df()

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: We only support 32-bit integer ALU operations for now
Iago Toral Quiroga [Tue, 10 Nov 2015 09:20:25 +0000 (10:20 +0100)]
i965/vec4: We only support 32-bit integer ALU operations for now

Add asserts so we remember to address this when we enable 64-bit
integer support, as suggested by Connor and Jason.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/disasm: align16 DF source regions have a width of 2
Iago Toral Quiroga [Wed, 25 May 2016 06:21:23 +0000 (08:21 +0200)]
i965/disasm: align16 DF source regions have a width of 2

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: set correct register regions for 32-bit and 64-bit
Iago Toral Quiroga [Wed, 18 Nov 2015 13:00:58 +0000 (14:00 +0100)]
i965/vec4: set correct register regions for 32-bit and 64-bit

For 32-bit instructions we want to use <4,4,1> regions for VGRF
sources so we should really set a width of 4 (we were setting 8).

For 64-bit instructions we want to use a width of 2 because the
hardware uses 32-bit swizzles, meaning that we can only address 2
consecutive 64-bit components in a row. Also, Curro suggested that
the hardware is probably fixing the width to 2 for 64-bit instructions
anyway, so just go with that and use <2,2,1>.

v2:
 - No need to explicitly set the vertical stride of 64-bit regions to 2,
   brw_vecn_grf with a width of 2 will do that for us.
 - No need to adjust the width of dst registers.

v3 (Ian):
 - Make type_size and width const.

Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965: add brw_vecn_grf()
Connor Abbott [Thu, 13 Aug 2015 21:22:03 +0000 (14:22 -0700)]
i965: add brw_vecn_grf()

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: translate d2f/f2d
Iago Toral Quiroga [Thu, 13 Aug 2015 22:56:22 +0000 (15:56 -0700)]
i965/vec4: translate d2f/f2d

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add double/float conversion pseudo-opcodes
Iago Toral Quiroga [Thu, 13 Aug 2015 22:36:05 +0000 (15:36 -0700)]
i965/vec4: add double/float conversion pseudo-opcodes

These need to be emitted as align1 MOV's, since they need to have a
stride of 2 on the float register (whether src or dest) so that data
from another thread doesn't cross the middle of a SIMD8 register.

v2 (Iago):
- The float-to-double needs to align 32-bit data to 64-bit before doing the
conversion. This was doable in align16 when we tried to use an execsize
of 4, but with an execsize of 8 we would need another align1 opcode to do
that (since we need data to cross the middle of a SIMD register). Just
making the opcode handle this internally seems more practical that adding
another opcode just for this purpose and having the caller know about this
before converting.
- The double-to-float conversion produces 32-bit elements aligned to 64-bit
so we make the opcode re-pack the result to 32-bit and fit in one register,
as expected by SIMD4x2 operation. This still requires that callers reserve
two registers for the float data destination because we need to produce
64-bit aligned data first, and repack it later on the same destination
register, but it saves the need for a re-pack opcode only to achieve this
making the operation complete in a single opcode. Hopefully that is worth
the weirdness of the double register allocation...

Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4: add support for printing DF immediates
Connor Abbott [Thu, 13 Aug 2015 21:18:04 +0000 (14:18 -0700)]
i965/vec4: add support for printing DF immediates

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: fix emitting 64-bit immediates
Iago Toral Quiroga [Thu, 13 Aug 2015 22:30:34 +0000 (15:30 -0700)]
i965/vec4/nir: fix emitting 64-bit immediates

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: set the right type for 64-bit registers
Connor Abbott [Thu, 13 Aug 2015 21:35:46 +0000 (14:35 -0700)]
i965/vec4/nir: set the right type for 64-bit registers

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: support doubles in ALU operations
Iago Toral Quiroga [Wed, 25 May 2016 07:27:49 +0000 (09:27 +0200)]
i965/vec4/nir: support doubles in ALU operations

Basically, this involves considering the bit-size information to set
the appropriate type on both operands and destination.

v2 (Curro)
  - Don't use two temporaries (and write one of them twice ) to obtain
    the nir_alu_type.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: Add bit-size information to types
Iago Toral Quiroga [Mon, 2 Nov 2015 05:07:27 +0000 (00:07 -0500)]
i965/vec4/nir: Add bit-size information to types

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: allocate two registers for dvec3/dvec4
Connor Abbott [Mon, 29 Feb 2016 11:35:05 +0000 (12:35 +0100)]
i965/vec4/nir: allocate two registers for dvec3/dvec4

v2 (Curro):
  - Do not special-case for a bit-size of 64, divide the bit_size by 32
    instead.
  - Use DIV_ROUND_UP so we can handle sub-32-bit types.

v3 (Ian):
  - Make num_regs const.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/vec4/nir: simplify glsl_type_for_nir_alu_type()
Connor Abbott [Mon, 10 Aug 2015 18:35:34 +0000 (11:35 -0700)]
i965/vec4/nir: simplify glsl_type_for_nir_alu_type()

Less duplication, one one less case to handle for doubles and support
for sized NIR types.

v2: Fix call to get_instance by swapping rows and columns params (Iago)

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot
Samuel Iglesias Gonsálvez [Mon, 6 Jun 2016 13:49:52 +0000 (15:49 +0200)]
i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot

max_vector_size is used in the vec4 backend to pad out the uniform
components to match a size that is a multiple of a vec4. Double and dvec2
uniforms only require a single vec4 slot, not two.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965/fs: fix exec_size when emitting DIM instruction
Samuel Iglesias Gonsálvez [Fri, 23 Dec 2016 06:37:38 +0000 (07:37 +0100)]
i965/fs: fix exec_size when emitting DIM instruction

Otherwise, DIM instructions will be emitted with the default exec size
which could be 16 in some cases, that is not legal.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agost/mesa: get Version from gl_program rather than gl_shader_program
Timothy Arceri [Sun, 20 Nov 2016 13:29:29 +0000 (00:29 +1100)]
st/mesa: get Version from gl_program rather than gl_shader_program

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
7 years agoi965: stop passing gl_shader_program to brw_compile_gs() and gen6_gs_visitor()
Timothy Arceri [Mon, 7 Nov 2016 23:28:12 +0000 (10:28 +1100)]
i965: stop passing gl_shader_program to brw_compile_gs() and gen6_gs_visitor()

Instead we caan just use gl_program.

Reviewed-by: Eric Anholt <eric@anholt.net>
7 years agoi965: get InfoLog and LinkStatus via the shader program data pointer in gl_program
Timothy Arceri [Mon, 7 Nov 2016 23:25:57 +0000 (10:25 +1100)]
i965: get InfoLog and LinkStatus via the shader program data pointer in gl_program

This removes another dependency on gl_shader_program in the codegen
functions.

Reviewed-by: Eric Anholt <eric@anholt.net>
7 years agoi965: eliminate gen6_xfb_enabled field in brw_gs_prog_data
Timothy Arceri [Mon, 7 Nov 2016 23:05:42 +0000 (10:05 +1100)]
i965: eliminate gen6_xfb_enabled field in brw_gs_prog_data

We can just get this information from shader_info instead.

Note that passing gen6_gs_visitor() gl_program via _LinkedShaders
will go away in a later patch.

Reviewed-by: Eric Anholt <eric@anholt.net>
7 years agoi965: update brw_get_shader_time_index() not to take gl_shader_program
Timothy Arceri [Tue, 20 Dec 2016 10:37:23 +0000 (21:37 +1100)]
i965: update brw_get_shader_time_index() not to take gl_shader_program

This removes another dependency on gl_shader_program in the codegen
functions which will help allow us to use gl_program in the
CurrentProgram array rather than gl_shader_program.

Reviewed-by: Eric Anholt <eric@anholt.net>
7 years agogallium/hud: fix the windows build by disabling file dumping
Marek Olšák [Mon, 2 Jan 2017 22:16:48 +0000 (23:16 +0100)]
gallium/hud: fix the windows build by disabling file dumping

7 years agoglsl: Update ES 3.2 shader output restrictions.
Kenneth Graunke [Mon, 2 Jan 2017 10:56:52 +0000 (02:56 -0800)]
glsl: Update ES 3.2 shader output restrictions.

This disallows fancy varyings in tessellation and geometry shaders,
as required by ES 3.2.

Fixes:
dEQP-GLES31.functional.tessellation.user_defined_io.negative.per_patch_array_of_structs
dEQP-GLES31.functional.tessellation.user_defined_io.negative.per_patch_structs_containing_arrays

(Not a candidate for stable branches as it only disallows things which
should be working as desktop GL allows them.)

v2: Update error messages to not say "vertex shader" (caught by Iago).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
7 years agoi965/miptree: Create a disable CCS flag
Ben Widawsky [Tue, 20 Dec 2016 14:29:05 +0000 (14:29 +0000)]
i965/miptree: Create a disable CCS flag

Cc: Chad Versace <chadversary@chromium.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
7 years agoi965: Replace bool aux disable with enum
Ben Widawsky [Sun, 18 Dec 2016 18:31:25 +0000 (10:31 -0800)]
i965: Replace bool aux disable with enum

As CCS buffers are passed to KMS, it becomes useful to be able to
determine exactly what type of aux buffers are disabled. This was
previously not entirely needed (though the code was a little more
confusing), however it becomes very desirable after a recent patch from
Chad:

commit 1c8be049bea786c2c054a770025976beba5b8636
Author: Chad Versace <chadversary@chromium.org>
Date:   Fri Dec 9 16:18:11 2016 -0800

    i965/mt: Disable aux surfaces after making miptree shareable

The next patch will handle CCS and get rid of no_ccs.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
7 years agodocs: document GALLIUM_HUD_DUMP_DIR envvar
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:14 +0000 (22:58 +0100)]
docs: document GALLIUM_HUD_DUMP_DIR envvar

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
7 years agogallium/hud: set filedescriptor for fps graph
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:13 +0000 (22:58 +0100)]
gallium/hud: set filedescriptor for fps graph

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
7 years agogallium/hud: set filedescriptor for cpu graph
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:12 +0000 (22:58 +0100)]
gallium/hud: set filedescriptor for cpu graph

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
7 years agogallium/hud: move file initialization to a function
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:11 +0000 (22:58 +0100)]
gallium/hud: move file initialization to a function

The function will be used later to create the filedescriptor
for other metrics.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
7 years agogallium/hud: dump hud_driver_query values to files
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:09 +0000 (22:58 +0100)]
gallium/hud: dump hud_driver_query values to files

Dump values for every selected data source in GALLIUM_HUD.

Every data source has its own file and the filename is
equal to the data source identifier.

Set GALLIUM_HUD_DUMP_DIR to dump values to files in this directory.

No values are dumped if the environment variable is not set, the
directory doesn't exist or the user doesn't have write access.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
7 years agoanv,radv: disable StorageImageWriteWithoutFormat for now
Ilia Mirkin [Fri, 30 Dec 2016 05:39:30 +0000 (00:39 -0500)]
anv,radv: disable StorageImageWriteWithoutFormat for now

The SPIR-V capability isn't even marked as enabled, and there are no
tests in Vulkan-CTS. Per Jason Ekstrand, this won't work in anv as such
write-only surfaces require additional setup which is currently not
performed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
7 years agoi965: Avoid NULL pointer dereference when transform feedback is off.
Kenneth Graunke [Fri, 30 Dec 2016 23:35:02 +0000 (15:35 -0800)]
i965: Avoid NULL pointer dereference when transform feedback is off.

upload_3dstate_streamout can be called when there's no currently bound
transform feedback object.  In this case, we get the default object,
which has a NULL shader (previously gl_shader_program, now gl_program).

The old code did something sketchy, but which worked:

   const struct gl_transform_feedback_info *linked_xfb_info =
      &xfb_obj->shader_program->LinkedTransformFeedback;

Here, if shader_program is NULL, this would be a bogus pointer of 0x60.
But we never actually dereferenced it, so it worked out.

With Timothy's recent reworks, we actually end up dereferencing
xfb_obj->program along the way, which crashes since it's NULL.

The solution is to move this pointer initialization into the "active"
block, where we know it actually exists and won't be bogus.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99231
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
7 years agoglsl/mesa: add reference to gl_shader_program_data from gl_program
Timothy Arceri [Tue, 20 Dec 2016 10:37:25 +0000 (21:37 +1100)]
glsl/mesa: add reference to gl_shader_program_data from gl_program

We also add the stubs for the standalone compiler in this change.

By adding a reference here we can now refactor some code to use
gl_program where we were previously awkwardly using gl_shader_program.

Reviewed-by: Eric Anholt <eric@anholt.net>
7 years agomesa: make union in gl_program a struct and add FIXME
Timothy Arceri [Fri, 30 Dec 2016 20:45:35 +0000 (07:45 +1100)]
mesa: make union in gl_program a struct and add FIXME

i915 is mixing the use of these fields, for now change this to a
struct and add a FIXME.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99229

7 years agoi965/peephole_ffma: Use nir_builder
Jason Ekstrand [Sat, 24 Dec 2016 19:21:57 +0000 (11:21 -0800)]
i965/peephole_ffma: Use nir_builder

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agonir/split_var_copies: Use a nir_shader rather than a void *mem_ctx
Jason Ekstrand [Sat, 24 Dec 2016 19:03:01 +0000 (11:03 -0800)]
nir/split_var_copies: Use a nir_shader rather than a void *mem_ctx

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agonir/opt_peephole_select: Pass around the actual nir_shader
Jason Ekstrand [Sat, 24 Dec 2016 18:58:17 +0000 (10:58 -0800)]
nir/opt_peephole_select: Pass around the actual nir_shader

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agonir/conditional_if: Properly use the builder
Jason Ekstrand [Sat, 24 Dec 2016 18:39:19 +0000 (10:39 -0800)]
nir/conditional_if: Properly use the builder

We were passing around a void *mem_ctx and using that to initialize the
builder which was wrong since that pointed to ralloc_parent(impl) which
is the shader but the builder is supposed to be initialized with the
nir_function_impl.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agonir/lower_var_copies: Use a shader rather than a void *mem_ctx
Jason Ekstrand [Sat, 24 Dec 2016 18:34:33 +0000 (10:34 -0800)]
nir/lower_var_copies: Use a shader rather than a void *mem_ctx

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>