intel/tools/error: Do ascii85 decode first.

The dashes "---" may occur within an ascii85 block, but only an ascii85
block starts with ':' or '~'.

Ported from Chris Wilson's intel-gpu-tools commit:
bceec7e1d8a160226b783c6344eae8cbf4ece144

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

c11/haiku: Define missing timespec_get on Haiku

Reviewed-by: Brian Paul <brianp@vmware.com>

egl/haiku: Correct invalid void* conversion in calloc

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

meson: Remove build_by_default from amd code

This is the same logic as the previous two patches.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: Don't build intel shared components by default

It's a neat idea, and still useful in some cases, but the intel common
code is used by i965 and anvil only, this is a little clearer.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: don't use build_by_default for specific gallium drivers

Using build_by_default : false is convenient for dependencies that can
be pulled in by various diverse components of the build system, the
gallium hardware/software drivers and state trackers do not fit that
description. Instead, these should be guarded using the variable that tracks
whether that driver should be enabled.

This leaves a few helper libraries: trace, rbug, etc, and the generic
winsys bits as `build_by_default : false` because there are a large
number of gallium components that pull them in.

v2: - remove build_by_default from winsys convenience libs as well.
v3: - Always put drivers before winsys for consistency

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>

r600/shader: handle bitfield extract semantics properly.

Fixes:
tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldExtract.shader_test

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: handle bitfieldInsert corner case.

This handles the bits >= 32 corner case in bitfieldInsert.

Fixes:
tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldInsert.shader_test.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: add gs tri strip adjacency fix.

Like
radeonsi: generate GS prolog to (partially) fix triangle strip adjacency rotation

evergreen hw suffers from the same problem, so rotate the
geometry inputs to fix this.

This fixes:
./bin/glsl-1.50-geometry-primitive-types GL_TRIANGLE_STRIP_ADJACENCY
on evergreen.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: fix isoline tess factor component swapping.

As per radeonsi, the tess factor components for isolines
are reversed.

Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600/shader: reserve first register of vertex shader.

r0 in input into vertex shaders contains things like vertexid,
we need to reserve it even if we have no inputs.

This fixes a bunch of tessellation piglits.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

meson: Move -Dvulkan-drivers handling higher in the file

The window-system auto-detection code (specifically for glx) relies on
with_any_vk being available.  This fixes the Vulkan-only build.  Also,
this puts it up near the handling of -Ddri-drivers and -Dgallium-drivers
which seems to make a bit more sense.

Fixes: 118a7f044191d4ab15ac9 "meson: add support for xlib glx"
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

meson: Stop requiring platforms for Vulkan

It should be perfectly valid to build a completely headless Vulkan
driver.  We don't need to require a platform.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

r600: don't emit atomic save if we have no atomic counters.

Otherwise we end up emitting the fence.

Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glx/dri3: Fix passing renderType into glXCreateContext

Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would
fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>

glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)

This is perfectly legal in GL 3.0+.

Fixes piglit/glx-create-context-current-no-framebuffer.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>

glx: Lower GLX opcode lookup into SendMakeCurrentRequest

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>

aubinator: Don't skip the first field in each subgroup

The previous iteration algorithm would advance the field pointer right
after we advance the group.  This meant that you would end up with
skipping the first field of the group.  In the common case, where the
only field is a struct (e.g. 3DSTATE_VERTEX_BUFFERS), it would get
skipped entirely.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/genxml: Delete empty groups

They serve no purpose other than to just fill empty space in the packet
so each dword has something.  Just disallowing empty groups is a bit
easier on some of the tools.  This does not change the generated packing
headers in any way.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Don't crash on invalid heap sizes when the PCI ID is overriden

nir/spirv: tg4 requires a sampler

Gather operations in both GLSL and SPIR-V require a sampler. Fixes
gathers returning garbage when using separate texture/samplers (on AMD,
was using an invalid sampler descriptor).

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

spirv: Use correct type for sampled images

We should use the result type of the OpSampledImage opcode, rather than
the type of the underlying image/samplers.

This resolves an issue when using separate images and shadow samplers
with glslang. Example:

    layout (...) uniform samplerShadow s0;
    layout (...) uniform texture2D res0;
    ...
    float result = textureLod(sampler2DShadow(res0, s0), uv, 0);

For this, for the combined OpSampledImage, the type of the base image
was being used (which does not have the Depth flag set, whereas the
result type does), therefore it was not being recognised as a shadow
sampler. This led to the wrong LLVM intrinsics being emitted by RADV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

spirv: add DO NOT EDIT warning on generated spirv_info.c

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

loader/dri3: Improve dri3 thread-safety

It turned out that with recent changes that call into dri3 from glFinish(),
it appears like different thread end up waiting for X events simultaneously,
causing deadlocks since they steal events from eachoter and update the dri3
counters behind eachothers backs.

This patch intends to improve on that. It allows at most one thread at a
time to wait on events for a single drawable. If another thread intends to
do the same, it's put to sleep until the first thread finishes waiting, and
then it rechecks counters and optionally retries the waiting. Threads that
poll for X events never pulls X events off the event queue if there are
other threads waiting for events on that drawable. Counters in the
dri3 drawable structure are protected by a mutex. Finally, the mutex we
introduce is never held while waiting for the X server to avoid
unnecessary stalls.

This does not make dri3 drawables completely thread-safe but at least it's a
first step.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102358
Fixes: d5ba75f8881 "st/dri2 Plumb the flush_swapbuffer functionality through to dri3"
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

etnaviv: automake,meson: include common_3d.xml.h in the sources lists

v2: include the file also in the meson.build (Eric Engestrom).

Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

egl: EXT_pixel_format_float plumbing

Patch adds support and capability to match with new surface attribute,
component type. Currently no configs with floating point type are exposed.

With this change, following dEQP test starts to pass:

   dEQP-EGL.functional.choose_config.color_component_type_ext.dont_care
   dEQP-EGL.functional.choose_config.color_component_type_ext.fixed
   dEQP-EGL.functional.choose_config.color_component_type_ext.float

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>

radv: add unlikely() around radv_save_descriptors()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: optimize calling radv_cmd_buffer_trace_emit()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: optimize calling radv_save_pipeline()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: use vk_zalloc instead of vk_alloc+memset

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove unnecessary memset() in radv_AllocateCommandBuffers()

This should not be needed, if the allocation fails an error is
returned and the host should handle it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove useless initializations in radv_create_cmd_buffer()

There is a memset() above.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove useless memset() in radv_CreateFence()

All radv_fence fields are initialized here.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: use vk_error() everywhere an error is returned

For consistency and it might help for debugging purposes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: make radv_emit_framebuffer_state() static

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not emit the framebuffer when restoring a pass

Instead just dirty RADV_CMD_DIRTY_FRAMEBUFFER and it will be
re-emitted if necessary before the next draw.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: prefetch VBO descriptors at the right place

Just after the vertex shader.

This seems to give a minor boost for, at least, Serious Sam
Fusion 2017 and Dawn of War 3. I don't see any real impacts
with The Talos Principle.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add radv_emit_prefetch_TC_L2_async() helper

Will be used for VBO descriptors prefetching.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: rename radv_emit_shaders_prefetch() to radv_emit_prefetch()

For consistency because this function will also prefetch VBO
descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

glsl/linker: use without_array() to retrieve type

This is what we do in the condition too, so it makes sense.

v2: Only compute without_array() once (Ilia).

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

radv: emit esgs ring size in one place.

This register is the same on all gpus so far, so emit it in one
place and also for the pre-gfx9 gpus set the value in the pipeline
creation.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: move calculating vs out info regs into pipeline.

This moves some calculations of register values into the pipeline
construction, it saves looking at outinfo in the cmd buffer emit.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

freedreno/a5xx: fix SSBO emit for non-zero offset

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: remove obsolete comment

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: don't create split/fo if only writing .x

In case an instruction only writes one register, and it is .x, we can
skip the extra level of fanout indirection.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: indirect grids

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: add global size compute cap

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: turn on std430 packing

Seems to fix dEQP compute related tests.. and matches what i965 does, so
perhaps there is some assumption that std430 packing is on by default
somewhere in NIR?

freedreno/a5xx: image support

freedreno/ir3: moar better scheduler

Add a new pass that inserts additional dependencies, rather than simply
relying on SSA srcs added in the nir->ir3 frontend.  This makes it
easier to deal with barriers, but the additional false deps also lets us
deal properly with ensuring a write depends on all previous reads.

Since conversion to barrier instructions is lossy (ie. just knowing the
instruction doesn't tell us enough about what other instructions the
barrier applies to), use barrier_class/barrier_conflict fields in the
ir3_instruction to retain this information.

This could probably be relaxed somewhat by considering *which* array/
buffer/image variable is being referenced.  Ie. a write to buffer A
can overtake a read from buffer B, if B is not coherent.  (right?)

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: move macros

I want to add a growable array to ir3_instruction, so we can append
false dependencies for purposes of scheduling barriers, atomics, and
dealing with write after read hazards.

Just code motion preparing for next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: image support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: shared variable support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: some SSBO cleanups/fixes

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: split out INSTR4F instructions

Atomic instructions take a different # of src args depending on .g or .l
variant, split these out into different helpers with INSTR*F() helper
macro that lets you specify instruction flag.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: cat6 encoding fixes

Instruction encoding/decoding fixes needed for images, shared variables,
etc.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add barriers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: invert is_same_type_mov() logic

Some instructions (like barriers) have no dst, which causes problems
with dereferencing a NULL dst.  Flip the logic around to reject opc's
that can't be a type of move first, to filter out those instructions.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add cat7 instructions

Needed for memory and execution barriers.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add SSBO get_buffer_size() support

Somehow I overlooked this when adding initial SSBO support.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: extract helper for common consts

User consts and driver consts such as UBO addresses and immediates are
handled the same for all shader stages, so split out a shared helper for
these, to make it easier to add more.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add image view state tracking

It is unfortunate that image state isn't a real CSO, since (at least for
a4xx/a5xx) it is a combination of sampler and "SSBO" image state, and it
would be useful to pre-compute the state block "register" values rather
than doing it at emit time.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

mesa/st/nir: assign driver_location for images

Signed-off-by: Rob Clark <robdclark@gmail.com>

st/program: fix compute shader nir references

In case the IR is NIR, the driver takes reference to the nir_shader.
Also, because there are no variants, we need to clone the shader,
instead of sharing the reference with gl_program, which would result
in a double free in _mesa_delete_program().

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

freedreno/ir3: rename ir3_compile -> ir3_context

Having both an ir3_compile (which was really context for compiling a
single shader variant) and ir3_compiler (which is the compiler object
that compiles all variants, ie. basically holds the RA regset) is a
bit confusing.

Signed-off-by: Rob Clark <robdclark@gmail.com>

intel/tools: Fix detection of enabled shader stages.

We renamed "Function Enable" to "Enable", which broke our detection
of whether shaders are enabled or not.  So, we'd see a bunch of HS/DS
packets with program offsets of 0, and think that was a valid TCS/TES.

Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

st/atifs: remove unrequired initialisation of gl_program fields

As far as I can tell these fields are only used to query arb
program info and are not related to ATI_fragment_shader.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Miklós Máté <mtmkls@gmail.com>

ac: add emit_vertex to the abi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: rework gs_vtx_offset handling

This simplifies things a bit and will enable it to work with the
common NIR -> LLVM code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir: add streams to nir data

This will be used by gallium drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/dri: fix deadlock when waiting on android fences

Android fences can't be deferred, because st/dri calls fence_finish
with ctx = NULL, so the driver can't flush u_threaded_context.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

meson: Guard freedreno build with with_gallium_freedreno.

This prevents build failures when libdrm_freedreno is unavailable,
which started happening after the ir3_compiler build was enabled.

(Patch by Rob, commit message by Ken).

Fixes: fecd04a66ae ("freedreno/ir3: fix standalone compiler meson build")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

docs: update calendar, add news item and link release notes for 17.2.5

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.2.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 96ad27f8fcf3979c577c052f725e2a80035295aa)

docs: add release notes for 17.2.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit ae52410bf08aa9c054651258f2fd0d0a2c9c5241)

i965/gen10: Use the correct form of | for the RCPFE workaround

Found by inspection

Fixes: d3d0fe4572f62474b86ef3a68405046c68b54062
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Make L3 configuration atom listen for TCS/TES program updates.

The L3 configuration code already considers the TCS and TES programs,
but failed to listen for TCS/TES program changes.

This was somehow missing.

Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in get_pipeline_state_l3_weights.")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

meson: build gallium-xlib based glx

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: add support for xlib glx

There is a bunch of churn in the main meson.build so that we can
correctly set the auto tristate of GLX. In particular, don't build
xlib-based glx when dri and gallium are disabled but vulkan is enabled,
in that case just turn glx off.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: move gl pkgconfig generation out of glx

Because the same generation logic is required by xlib glx and
gallium-xlib glx, it makes sense to pull it out.

v2: - Ensure that libgl is defined before trying to generate a pkgconfig
      file with it.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: move wayland-egl into egl folder

This ensure that it's properly guarded, but also makes the code clearer
by grouping related things together.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

meson: add nir_builder_opcodes_h to gallium_auxiliary

This creates a dependency on this header being generated before trying
to compile any of these targets, as well as passing the correct -I to
the compiler to ensure it's included correctly.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium/xlib: remove GL_{MAJOR,MINOR,TINY}

These variables were removed from autotools in 2008 (sha:
80f68e1b6a0e5bd2da799c), but they have lived on here. The Scons build
meanwhile doesn't set a patch/tiny version at all, just major and minor.
This patch removes the unused variables and simply sets the version,
leaving patch/tiny as 0 since that's what the autotools build as been
doing forever. This shouldn't change any behavior.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

radeonsi: get llvm types from ac

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glx/windows: Fix building libwindowsdri when libX11 headers are installed in a non-standard location

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Adam Jackson <ajax@redhat.com>

util: include unistd.h, which may be required for usleep prototype

This seems to be dropped in 222a2fb9 "util: move os_time.[ch] to src/util"

../../../src/util/os_time.c: In function ‘os_time_sleep’:
../../../src/util/os_time.c:104:4: error: implicit declaration of function ‘usleep’ [-Werror=implicit-function-declaration]

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

autotools: Set C++ visibility flags on Intel

These flags are set for C sources, but not C++. This causes symbol
visibility leaks from the C++ parts of the Intel compiler.

Fixes: 700bebb958e93f4d ("i965: Move the back-end compiler to src/intel/compiler")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

docs/releasing: improve the pre-announce template and examples

v2: Choose a proper rejection example (Emil).

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

docs/releasing: drop manually exported variables during smoke test

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

docs/releasing: drop custom LLVM_CONFIG if previously manually set

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

st/dri: fix android fence regression

Fixes piglit - egl_khr_fence_sync/android_native tests.
Broken by 884a0b2a9e55d4c1ca39475b50d9af598d7d7280.

Introduce state-tracker flush flags, analogous to the pipe ones. Use
the former when with stapi->flush().

Fixes: 884a0b2a9e5 ("st/dri: use stapi flush instead of pipe flush
when creating fences")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util/u_thread: fix compilation on Mac OS

Apparently, it doesn't have pthread barriers.

p_config.h (which was originally used to guard this code) uses the
__APPLE__ macro to detect Mac OS.

Fixes: f0d3a4de75 ("util: move pipe_barrier into src/util and rename to util_barrier")
Cc: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

util/u_queue: handle OS_TIMEOUT_INFINITE in util_queue_fence_wait_timeout

Fixes e.g. piglit/bin/bufferstorage-persistent read -auto

Fixes: e6dbc804a87a ("winsys/amdgpu: handle cs_add_fence_dependency for deferred/unsubmitted fences")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/u_threaded: fix end_query regression

Ouch...

Fixes: 244536d3d6b4 ("gallium/u_threaded: avoid syncs for get_query_result")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103653
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

swr: Fixed an uncommon freed-memory access during state validation

State validation is performed during clear and draw calls.  Validation
during clear was still accessing vertex buffer state.  When the currently
set vertex buffers are client arrays, this could lead to accessing freed
memory.  Such is the case with the VMD application.

Previously, vertex buffer validation depended on a dirty bit or the
draw info indicating an indexed draw.  This required special handling for
clears.  But, vertex buffer validation still occurred which was unnecessary
and wrong.

Now, only minimal validation is performed during clear, deferring the
remainder to the next draw.  And, by setting the dirty bit in swr_draw_vbo
for indexed draws, vertex buffer validation is only dependent upon a
single dirty bit.

This fixes a bug exposed by the VMD application when changing models.

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>

freedreno/ir3: fix standalone compiler meson build

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: correct # of dest components for intrinsics

Don't rely on intr->num_components having a valid value.  It doesn't
seem to anymore for non-vectorized intrinsics.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: remove bogus assert

The ssbo atomic instructions are not vectorized.  So num_components is
not expected to be valid.

Signed-off-by: Rob Clark <robdclark@gmail.com>

nir: handle get_buffer_size in nir_lower_atomics_to_ssbo

Overlooked initially, be we need to remap the SSBO index for this as
well.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>