Gabe Black [Mon, 16 Sep 2019 21:58:43 +0000 (14:58 -0700)]
fastmodel: Expose all CPU communication ports from the GIC.
The unconnected CPU ports/sockets still need to be connected for TLM to
be happy, so this change also adds a terminator module which finds all
unbound sockets, creates pair sockets for them to connect to, binds
everything together, and implements the target interface with a dummy
stub that will complain and crash gem5 if it ever gets called.
This will allow us to use the same GIC model to connect an arbitrary
number of cores, up to the architected limit of 256.
Change-Id: Iaa83fe4f023217dc91a3734b31f764fc4176130e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21500
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Thu, 3 Oct 2019 20:11:06 +0000 (13:11 -0700)]
misc: Updating contributing.md to discuss Gerrit guidelines
Change-Id: I2449d4b0384f33d9635fc2a314a24341816dab1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21419
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Mingyuan [Mon, 2 Sep 2019 22:48:03 +0000 (17:48 -0500)]
mem-cache: set the second chance to false when inserting a block
Modify second chance replacement policy so that entries are inserted
without a second chance. Previously, the second chance bit was set
to true when a cache line was inserted. So the cache line would gain
its second chance when inserting. This is wrong because the cache
block will only get a second chance when it hits.
Here's a quoted citation for the second chance replacement policy:
"Whenever the algorithm examines a page entry, it extracts the associated
usage bit and enters it into the high-order position of a k-bit shift
register after shifting the contents of the register one bit-position
lower. Then if the shift register is nonzero, the page is retained; if the
shift register is zero, the page is replaced by the new page. In either
case the usage bit for the page is turned off and the circular list
pointer is advanced."
(A Paging Experiment with the Multics System, FJ Corbato, 1968)
Change-Id: I0d07e56aa16c67dd36e0d490c3f457f91e46f320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20882
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Mingyuan [Mon, 2 Sep 2019 22:43:59 +0000 (17:43 -0500)]
mem-cache: Fixed a bug in MRU replacement policy
The lastTouchTick is set to 0 when instantiate. This will cause the
candidate[0] to get evicted over and over again in MRU replacement
policy. To resolve this, break the search loop whenever it finds a
cold cache line.
Change-Id: I33aa57ebe0efca15986f62c3ae10a146bd2b779f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20881
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Gabe Black [Wed, 11 Sep 2019 21:18:25 +0000 (14:18 -0700)]
x86: Stop using and delete the x86 IntDevice class.
Most of its functionality has been exported already. This change makes
the two classes which were inheriting IntDevice create an IntMasterPort
themselves.
Change-Id: I73d17cd79cf8252b0e26dd2576f552bf9054adf4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20825
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 2 Oct 2019 04:15:06 +0000 (21:15 -0700)]
arch,base: Separate the idea of a memory image and object file.
A memory image can be described by an object file, but an object file
is more than a memory image. Also, it makes sense to manipulate a
memory image to, for instance, change how it's loaded into memory. That
takes on larger implications (relocations, the entry point, symbols,
etc.) when talking about the whole object file, and also modifies
aspects which may not need to change. For instance if an image needs
to be loaded into memory at addresses different from what's in the
object file, but other things like symbols need to stay unmodified.
Change-Id: Ia360405ffb2c1c48e0cc201ac0a0764357996a54
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21466
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
JingQuJQ [Fri, 14 Jun 2019 02:29:56 +0000 (21:29 -0500)]
mem-ruby: Allow Ruby to use all replacement policies in Classic
Add support in Ruby to use all replacement policies in Classic.
Furthermore, if new replacement policies are added to the
Classic system, the Ruby system will recognize new policies
without any other changes in Ruby system. The following list
all the major changes:
* Make Ruby cache entries (AbstractCacheEntry) inherit from
Classic cache entries (ReplaceableEntry). By doing this,
replacement policies can use cache entries from Ruby caches.
AccessPermission and print function are moved from
AbstractEntry to AbstractCacheEntry, so AbstractEntry is no
longer needed.
* DirectoryMemory and all SLICC files are changed to use
AbstractCacheEntry as their cache entry interface. So do the
python files in mem/slicc/ast which check the entry
interface.
* "main='false'" argument is added to the protocol files where
the DirectoryEntry is defined. This change helps
differentiate DirectoryEntry from CacheEntry because they are
both the instances of AbstractCacheEntry now.
* Use BaseReplacementPolicy in Ruby caches instead of
AbstractReplacementPolicy so that Ruby caches will recognize
the replacement policies from Classic.
* Add getLastAccess() and useOccupancy() function to Classic
system so that Ruby caches can use them. Move lastTouchTick
to ReplacementData struct because it's needed by
getLastAccess() to return the correct value.
* Add a 2-dimensional array of ReplacementData in Ruby caches
to store information for different replacement policies. Note
that, unlike Classic caches, where policy information is
stored in cache entries, the policy information needs to be
stored in a new 2-dimensional array. This is due to Ruby
caches deleting the cache entry every time the corresponding
cache line get evicted.
Change-Id: Idff6fdd2102a552c103e9d5f31f779aae052943f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20879
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 2 Oct 2019 04:22:07 +0000 (21:22 -0700)]
arch,base: Stop loading the interpreter in ElfObject.
The interpreter is a separate object file, and while it's convenient to
hide loading it in the code which loads the main object file, it breaks
the conceptual abstraction since you only asked it to load the main
object file.
Also, this makes every object file format reimplement the idea of
loading the interpreter. Admittedly only ELF recognizes and sets up
an interpreter, but other formats conceptually could too.
This does move that limitted hypothetical redundancy out of the object
file formats and moves it into the process objects, but I think
conceptually that's where it belongs. It would also probably be pretty
easy to add a method to the base Process class that would handle
loading an image and also the interpreter image.
This change does not (yet) separate reading symbol tables.
Change-Id: I4a165eac599a9bcd30371a162379e833c4cc89b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21465
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Giacomo Travaglini [Mon, 30 Sep 2019 15:37:52 +0000 (16:37 +0100)]
arch-arm: Move generateDtb to ArmSystem
This is aligning with the fact that dtb autogeneration is already
possible with an ArmSystem.
Change-Id: I72149927ee70d29458f8718a03845bb293c12145
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21602
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 30 Sep 2019 10:06:08 +0000 (11:06 +0100)]
dev-arm, configs: Remove RealViewPBX platform
This is an old unused platform. We should support VExpress_GEM5 based
platforms only.
Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 1 Oct 2019 08:25:53 +0000 (01:25 -0700)]
arch, base: Stop assuming object files have three segments.
The ObjectFile class has hardcoded assumptions that there are three
segments, text, bss and data. There are some files which have one
"segment" like raw files, where the entire file's contents are
considered a single segment. There are also ELF files which can have
an arbitrary number of segments, and those segments can hold any
number of sections, including the text, data and/or bss sections.
Removing this assumption frees up some object file formats from having
to twist themselves to fit in that structure, possibly introducing
ambiguities when some segments may fulfill multiple roles.
Change-Id: I976e06a3a90ef852b17a6485e2595b006b2090d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21463
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 31 Aug 2019 00:02:43 +0000 (17:02 -0700)]
fastmodel: Export GICV3Comms directly.
This lets us avoid having to have two levels of bridging and twice as
many ports on both the CPU and GIC side. The direct communication ports
can be instantiated and connected using array syntax, where the bridges
require instantiating each bridge individually and wiring them up one
at a time with a lot of boilerplate/duplicate code.
Change-Id: I815ee47bcd19994e46a5220e0c23e89c497d7aa5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21050
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Bobby R. Bruce [Fri, 4 Oct 2019 20:25:44 +0000 (13:25 -0700)]
tests, misc: Updating TESTING.md to describe running unit tests
Previously we did not have any documentation discussing how gem5's GTests
were built and executed. TESTING.md has thereby been updated to highlight
how this is done. These unit tests should be run prior to each new
submission to Gerrit. This has been noted in TESTING.md also.
Change-Id: If5867fa0a2e4f6ea0921191a51e779c19a28117a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21479
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Tue, 8 Oct 2019 21:03:49 +0000 (14:03 -0700)]
tests: Migrated refcnt.cc test from src/unitttest to a gtest
refcnt.cc was previously tested in src/unittest/refcnttest.cc. This has
now been translated into a GTest as faithfully to the original as
possible.
Change-Id: I51f7a3d1e0a85b128c4eebd97cfe79b87406dc29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21499
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Chun-Chen TK Hsu [Tue, 8 Oct 2019 11:02:33 +0000 (19:02 +0800)]
system-arm: Initialize ICC_SRE_EL3 register of all CPUs
Fix a bug that only CPU0 initialized ICC_SRE_EL3 register.
Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Gabe Black [Wed, 2 Oct 2019 03:17:06 +0000 (20:17 -0700)]
arch-mips,arch-riscv,base: Get rid of the unused HexFile class.
A pointer to it was set up in the MIPS and RISCV system classes, but
nothing ever set that pointer. The class was put in base/loader, but
didn't have anything to do (as far as I can see) with loading anything
it had a loadSegments method, but was not a subclass of ObjectFile.
Change-Id: I4b711a31df20e20ffc306709227f60aa020fca15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21464
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sun, 29 Sep 2019 02:26:02 +0000 (19:26 -0700)]
base: Rename Section to Segment, and some of its members.
ELF is, in my opinion, the most important object file format gem5
currently understands, and in ELF terminolgy the blob of data that
needs to be loaded into memory to a particular location is called a
segment. A section is a software level view of what's in a region
of memory, and a single segment may contain multiple sections which
happen to follow each other in memory.
Change-Id: Ib810c5050723d5a96bd7550515b08ac695fb1b02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21462
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 29 Sep 2019 02:07:17 +0000 (19:07 -0700)]
base: Get rid of the unused global pointer in object files.
This was only ever read from Alpha, and nothing ever set it.
It defaulted to zero, so this change just propogates that value through
to the Alpha Process class.
Change-Id: I569cf9d61a37322dbd88de1038a2af74c64bbe7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21461
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Fri, 4 Oct 2019 06:42:35 +0000 (23:42 -0700)]
base: Ensure %p format arguments are printed as pointers.
If the %p format is used, char * arguments should be printed as the
hex value of their pointer, not as strings. Unfortunately blindly
passing them to an ostream using << will not do that. This change adds
some casting in that case to ensure that they're treated as numbers and
not as strings.
Change-Id: If02bae6d5e468b352266702fcba62b6beddffcbd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21459
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 28 Aug 2019 22:16:05 +0000 (15:16 -0700)]
fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.
This makes it easier to wire up CPUs to the interrupt controller, and
makes things more modular.
Change-Id: I8d3ab26e4bb588b8efb198ed145d0f58b7ee04cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21049
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Thu, 3 Oct 2019 20:39:41 +0000 (22:39 +0200)]
configs: Isolate ISA related object lists
Some objects are not compiled when using NULL ISA, and therefore
their object lists cannot exist.
Change-Id: I93ec576229916c892de50bb6c73cd602e18a3654
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21439
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Ciro Santilli [Mon, 30 Sep 2019 15:52:32 +0000 (16:52 +0100)]
kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR
Those registers are 32-bit instead of 64 in the KVM API.
The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains:
0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr
0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr
The register itself is 64-bit in the ARM manual, but the top 32 are
RES0.
This fixes the following error when running ARM KVM early in the
simulation:
panic: KVM: Failed to set register (0x60300000001000d4) value
(errno: 22)
Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ciro Santilli [Mon, 23 Sep 2019 14:43:52 +0000 (15:43 +0100)]
config: skip access to branchPred in ARM KVM
Prevents runtime error:
AttributeError: object 'ArmV8KvmCPU' has no attribute 'branchPred'
Change-Id: Ic5765fd560381cbacc2fa2fd2e6f79d98433c535
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21299
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 2 Oct 2019 02:26:12 +0000 (19:26 -0700)]
base: ELF segment types are not bitfields.
The ELF segment type had been checked by bitwise &-ing it with the
PT_LOAD constant to check if it was loadable. This is incorrect. The
value is a flat integer, with different values selecting different
types of segments.
Change-Id: I644dd985bda4ad2d992557c90ffe8048c0ae6aac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21460
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tommaso Marinelli [Wed, 2 Oct 2019 21:33:59 +0000 (23:33 +0200)]
kvm: Rename gettid() to build with glibc 2.30+
glibc 2.30 introduced the function gettid() in sys/types.h to return the
caller's thread ID. In order to avoid conflicts, the already present
gettid() functions have been renamed to sysGettid(). This fixes a
compilation error with X86 arch.
Change-Id: I76c971465fc4b50e4decde8303185439082b2378
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21379
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tommaso Marinelli [Thu, 3 Oct 2019 08:54:37 +0000 (10:54 +0200)]
mem: Remove unused variable
The variable *sys in dram_ctrl.cc was only used in an assert() check,
therefore it has been removed to allow building gem5.fast without
errors. A typo in a comment in abstract_mem.hh has also been corrected.
Change-Id: I2663545449ecfdb5a27c3574b79dd42beb4a49c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21380
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Ayaz Akram [Thu, 1 Aug 2019 20:22:48 +0000 (13:22 -0700)]
tests: Fix a minor bug in fixture.py
debug is a part of test_log object.
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Change-Id: I56d950483c1d86b76b4f652741d2323c1b078e3e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19768
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Thu, 3 Oct 2019 16:43:22 +0000 (09:43 -0700)]
dev, misc: Fixing "may be used unitialized" compilation error
When compiling using "scons build/X86/base", "error: 'tx_queue_size'
may be used uninitialized in this function" is received (cc1plus:
all warnings treated as errors). tx_queue_size is now initialized
to zero to avoid this compilation error.
Change-Id: I0e2a4fd9ad6053c4c4124c83da9a7919778bcc52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Mon, 15 Apr 2019 21:00:21 +0000 (14:00 -0700)]
sim-se: Fix invalid delete of params on clone
The params pointer is kept by the SimObject and should not be deleted
until gem5 exits. Added a to do to remember this object is leaked.
Change-Id: I46cc23a09e4e9b6bc2fdcd961148324c41820815
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18068
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Giacomo Travaglini [Thu, 12 Sep 2019 09:23:16 +0000 (10:23 +0100)]
arch-arm: Annotate CM flag in AA64 CM Instructions
DC ZVA instruction is not classified as a cache maintenance instruction,
and therefore its execution cannot cause this field to be set to 1.
Change-Id: I0f30db1e6fc629dc52293edfb2bac4cf99ee49cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21306
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Thu, 12 Sep 2019 09:23:16 +0000 (10:23 +0100)]
arch-arm: Set CM bit in DataAbort
The CM bit in a DataAbort ISS indicates whether the Data Abort came from
a cache maintenance or address translation instruction.
Change-Id: I8888520446550581c8dd0507a8989935db7047be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 19 Sep 2019 13:54:04 +0000 (14:54 +0100)]
sim: Mark System::getThreadContext method as const
Change-Id: Ic0ce1b098cfe0ce6ea37986a8a55002a5c18a66c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21304
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Marc Mari Barcelo [Wed, 18 Sep 2019 17:17:09 +0000 (18:17 +0100)]
dev-arm: Improve fault message on SMMUv3 translation fault
Change-Id: Ib1d7ae73951b52f2378f8bd50e804d3237f74074
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21303
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Marc Mari Barcelo [Wed, 18 Sep 2019 17:10:42 +0000 (18:10 +0100)]
dev-arm: Fix address used to update the SMMUv3 Walk Cache
Last level of SMMUv3 WalkCache should store the address without an offset.
Change-Id: I1046bd8210500c2c38802acd41a4403e52fd3c90
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21302
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 19 Sep 2019 13:43:36 +0000 (14:43 +0100)]
arch-arm: Create helper for sending events (SEV)
Events can be generated by devices, so we need an interface devices
can use to notify events to PEs.
Change-Id: I330575e7d116388d5f9260ef4400b0feaa861f3e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21301
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 29 Aug 2019 00:12:55 +0000 (17:12 -0700)]
fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.
This was to support port proxies and getInstPort and getDataPort. With
some recent upstream changes, getInstPort and getDataPort are only used
for CPU switching which we can't support (TLM ports are bound
permanently), and with the sendFunctional delegate for port proxies,
we don't need to have a traditional gem5 port lying around.
This gets rid of the "mem" port and all its plumbing.
Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Gabe Black [Wed, 28 Aug 2019 23:55:33 +0000 (16:55 -0700)]
fastmodel: Implement a custom sendFunctional for CortexA76x1.
Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Gabe Black [Wed, 11 Sep 2019 20:45:24 +0000 (13:45 -0700)]
x86: Switch from MessageReq and Resp to WriteReq and Resp.
Originally MessageReq was intended to mark a packet as a holding a
message destined for a particular recipient and which would not
interact with other packets.
This is similar to the way a WriteReq would behave if writing to a
device register which needs to be updated atomically. Also, while the
memory system *could* recognize a MessageReq and know that it didn't
need to interact with other packets, that was never implemented.
Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 28 Aug 2019 23:34:46 +0000 (16:34 -0700)]
fastmodel: Let the EVS set an attribute for getSendFunctional to return.
The iris CPU model doesn't necessarily know the best way to send
functional packets (what port? what type is that port?), but only has
a generic sc_module pointer to the EVS and so can't call specialized
methods on it. There also isn't any common base class for EVSes to cast
into in a generic way.
This attribute mechanism lets the EVS set up its own sendFunctional
implementation however it needs to using facilities that are built
into generic sc_objects.
Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Georg Kotheimer [Thu, 31 May 2018 09:24:18 +0000 (11:24 +0200)]
style: normalize filename in SortedIncludes.fix()
The filename affects the sorting result. Therefore check(),
which normalizes the filename, detects an invalid sorting
of includes, but fix() fails to fix the corresponding includes.
Change-Id: I7d5a941c9ebea853004922d19e3b84f8ded2afa6
Signed-off-by: Georg Kotheimer <georg.kotheimer@mailbox.tu-dresden.de>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10742
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Wed, 28 Aug 2019 09:53:31 +0000 (02:53 -0700)]
fastmodel: Add a gem5Cpu attribute to the CortexA76x1.
This attribute is to let the fast model EVS CPU find and talk to the
gem5 CPU in case it needs a pointer to one of its ThreadContexts for
instance.
Also move the code that finds the clock period attribute/event to the
constructor. gem5 guarantees that the EVS is constructed before its
pointer is passed to the iris CPU wrapper, and so the EVS will have
had a chance to install those controls if it's going to.
Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 28 Aug 2019 06:34:31 +0000 (23:34 -0700)]
fastmodel: Add a utility class which makes it easier to watch signals.
These signals come from the exported virtual subsystem and could signal
interrupts, etc. The new SignalReceiver class makes it easier to watch
those signals and perform some behavior when they change without having
to bring along a lot of systemc baggage.
Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 28 Aug 2019 00:20:30 +0000 (17:20 -0700)]
fastmodel: Pull out and simplify the interrupt mechanism in the GIC.
This change pulls out the SPI and PPI command structures and replaces
them with a custom protocol which can deliver a SPI or PPI without
having to bundle their parameters into a structure.
Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Mon, 12 Aug 2019 22:15:37 +0000 (00:15 +0200)]
mem-cache: Fix invalid whenReady
When a writeback needs to be allocated the whenReady field of the
block is not set, and therefore its access latency calculation
uses the previously invalidated value (MaxTick), significantly
delaying execution.
This is fixed by assuming that the data write portion of a write
access is done regardless of previous writes, and that only the
tag latency is important for the critical path latency calculation.
Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Tue, 3 Sep 2019 13:45:19 +0000 (15:45 +0200)]
configs: Port PlatformConfig to the common object list
Port PlatformConfig to use the common object list.
Change-Id: If62e596bf1f28b49994da3a2800450d163383755
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Tue, 3 Sep 2019 13:24:23 +0000 (15:24 +0200)]
configs: Port MemConfig to the common object list
Port MemConfig to use the common object list.
Change-Id: If421c2745ac3431718a5170314045b456fc64a90
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Tue, 3 Sep 2019 10:08:51 +0000 (12:08 +0200)]
configs: Port HWPConfig to the common object list
Port HWPConfig to use the common object list.
Change-Id: I86db6b872808f754193dbf5814dd6c951c8f1980
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20591
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Tue, 3 Sep 2019 09:59:18 +0000 (11:59 +0200)]
configs: Port BPConfig to use the common object list
Port BPConfig to use the common object list.
Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Tue, 3 Sep 2019 10:22:59 +0000 (12:22 +0200)]
configs: Port CPUConfig to use the common object list
Factor out ObjectList functionality from CPUConfig.
Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Tue, 3 Sep 2019 09:57:44 +0000 (11:57 +0200)]
configs: Create a basic ObjectList
There are multiple files that reimplement the same functionality
of listing and getting available modules for class instantiation.
Create a base class that can be derived and reduce code duplication.
Change-Id: I96bf47b1ffd10893691b0b95591969b38894dd65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20588
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Thu, 5 Sep 2019 12:45:52 +0000 (14:45 +0200)]
configs: Remove is_atomic_cpu check
Commit
224f2d50a9873d054f486d7661d947db76f4cf68 removed all instances
of is_atomic_cpu.
Change-Id: I1101fbdbc16dc5d093ab87d3817308176559a548
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20659
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Daniel R. Carvalho [Sat, 7 Sep 2019 10:17:04 +0000 (12:17 +0200)]
mem-ruby: Remove inexistent functions from Util
Remove forward declaration of inexistent functions from RubySlicc_Util.sm.
Change-Id: I548bd75cb570371fbdaccf914c5eb9a7b92313d1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21086
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sat, 7 Sep 2019 10:08:40 +0000 (12:08 +0200)]
mem-ruby: Make bitSelect use bits<Addr>
There is no need to replicate bits<Addr>' functionality.
As a side effect, ADDRESS_WIDTH is no longer used and was removed
Change-Id: Ia5679f3976c81f779665d82cb758850092f2a293
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21085
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sat, 7 Sep 2019 09:45:25 +0000 (11:45 +0200)]
mem-ruby: Fix maskLowOrderBits
The function was wrong when number = 63. Also, use the more reliable
src/base/bitfield.hh's mbits when posible.
maskLowOrderBits has only been kept because SLICC does not accept
a templated function.
Change-Id: I8dd680da02ceb9e614e2f9cbf8f1ac52cead8d45
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21084
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sat, 7 Sep 2019 09:14:57 +0000 (11:14 +0200)]
mem-ruby: Remove shiftLowOrderBits
There is no need to encapsulate a shift operation.
Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sat, 7 Sep 2019 08:55:45 +0000 (10:55 +0200)]
mem-ruby: Remove maskHighOrderBits
Function was not being used. If needed, src/base/bitfield.hh's
mbits can be used instead:
maskHighOrderBits(addr, pos) == mbits<Addr>(addr, 64-pos, 0)
Change-Id: I3abd041f8d256ec157ba7502182d8588721c2a05
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21082
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sat, 7 Sep 2019 08:23:21 +0000 (10:23 +0200)]
mem-ruby: Remove bitRemove
bitRemove is not being used anywhere. If needed, can be used
as src/base/bitfield.hh's bits:
bitRemove(addr, small, big) ==
((bits<Addr>(addr, 63, big + 1) << small) |
bits<Addr>(addr, small, 0))
Change-Id: I45fd3bc0271ccb659d6a94e3dd00ca095dfd6aa7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21081
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Thu, 12 Sep 2019 13:36:52 +0000 (14:36 +0100)]
cpu: Make use of DRAMCtrl::AddrMap in the traffic generators
Use the enum defined in the memory controller rather than custom
strings and int that are later converted to the DRAMCtrl::AddrMap
enum.
Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Tue, 24 Sep 2019 21:28:29 +0000 (14:28 -0700)]
misc: Added line wrapping functionality for Sim-Object desc
Descriptions were previously printed on one line, unless explicitly broken
when writing the description of the Sim-Object. In this commit, line
wrapping is enabled when printing these descriptions. Developers, when
writing the Sim-Object descriptions, may now over multiple lines with
triple double-quotes and still have the description output correctly when
viewing the Sim-Objects within the CLI.
E.g.: X86System previously had the following load_addr_mask component which
was output as:
load_addr_mask
default:
18446744073709551615
desc: Address to mask loading binaries with, if 0, system \
auto-calculates the mask to be the most restrictive, otherwise it obeys a \
custom mask.
This was defined by the developer via:
load_addr_mask = Param.UInt64(0xffffffffffffffff,
"Address to mask loading binaries with, if 0, system "
"auto-calculates the mask to be the most restrictive, "
"otherwise it obeys a custom mask.")
This is now displayed as:
load_addr_mask
default:
18446744073709551615
desc: Address to mask loading binaries with, if 0,
system auto-calculates the mask to be the most
restrictive, otherwise it obeys a custom mask.
JiraID: Gem5-57
Built: Linux (GCC)
Tested: Ran quick tests for X86, ARM, and RISC-V
Change-Id: If012304e50af60f6ba10c1fa2b44da8bac1c09cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21179
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Mon, 23 Sep 2019 17:18:28 +0000 (18:18 +0100)]
mem: Use new-style stats in the XBar models
Migrate to new-world stats with an explicit hierarchy in all of the
XBar models.
Change-Id: I18b6746a1303ca415638e6d382fb4757607f1123
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21141
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andreas Sandberg [Mon, 23 Sep 2019 17:16:26 +0000 (18:16 +0100)]
mem-cache: Switch to new-style stats
This change puts cache and tag stats into a Stats::Group struct. This
makes it easier to identify stat updates (they are prefixed with
stat.) and adds hierarchy information for output formats that need it.
Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Mon, 23 Sep 2019 17:20:23 +0000 (18:20 +0100)]
mem: Convert DRAM controller to new-style stats
Note that this changes the stat format used by the DRAM
controller. Previously, it would have a structure looking a bit like
this:
- system
- dram: Main DRAM controller
- dram_0: Rank 0
- dram_1: Rank 1
This structure can't be replicated with new-world stats since stats
are confined to the SimObject name space. This means that the new
structure looks like this:
- system
- dram: Main DRAM controller
- rank0: Rank 0
- rank1: Rank 1
Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Timothy Hayes [Fri, 27 Sep 2019 13:51:43 +0000 (14:51 +0100)]
ruby: 2x protocols has typo/syntax error that fails building
MOESI_hammer and MOESI_CMP_token contain incorrect lines.
Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21259
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Fri, 23 Aug 2019 02:34:24 +0000 (19:34 -0700)]
fastmodel: Add glue code which adapts fastmodels to run in gem5.
Fast Models are models written by ARM which emulate different
components of a computer system. They can be combined into small
subsystems and then exported as systemc modules.
To enable this code, you'll need to set USE_ARM_FASTMODEL variable to
true. This CL does not include the fast models themselves, or a license
to use them or the associated tools. To build these fast models, you'll
need to set some scons variables. These variables should be set as
described in the fast model distribution.
* PVLIB_HOME
* MAXCORE_HOME
* ARMLMD_LICENSE_FILE
Some minor patches to source filesdistributed with the fast model code
may be necessary since their use of systemc is not necessarily 100%
standards compliant.
Change-Id: Id53814b95d8aa320da4d4f2159be0736fc12eb73
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20799
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Mon, 23 Sep 2019 17:21:20 +0000 (18:21 +0100)]
sim: Convert power modelling framework to new-style stats
Change-Id: I1dd3ea3d37bb4464637222aa5bc5d88cc7d9b66a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21143
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Andreas Sandberg [Tue, 24 Sep 2019 09:41:17 +0000 (10:41 +0100)]
stats: Add a preDumpStats() callback to Stats::Group
Some objects need to know that we are about to dump stats to perform
prepare statistics. This is currently done by registering a callback
with the stat system. Expose this callback as a virtual method
in Stats::Group to make this pattern more convenient.
Change-Id: I5aa475b7d04c288e45f5f413ab7a1907b971dae5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21139
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Andreas Sandberg [Tue, 24 Sep 2019 17:46:23 +0000 (18:46 +0100)]
stats: Don't output index in vectors of length 1
New-world stats didn't implement the old gem5 quirk where the index of
an element in a vector of size 1 is ignored. This affects the object
path when printed in a stat file. Implement the same quirk as the
original code to make sure names of old- and new-world stats are
compatible.
Change-Id: I12696d40baaed2d0bb1ef061e87c3b1d0f4bb4b1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21163
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Andreas Sandberg [Tue, 24 Sep 2019 17:44:13 +0000 (18:44 +0100)]
stats: Correctly print new-style dist stat names
The text stat printer didn't output fully qualified names for
new-style dist stats. Fix that.
Change-Id: I61bc7403fbd760bbbb0641e8e593781e6d03a4ed
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21162
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Jing Qu [Thu, 19 Sep 2019 22:41:57 +0000 (17:41 -0500)]
mem-ruby: prevent cacheProbe being called multiple times
The cacheProbe() function will return the victim entry, and it gets
called for multiple times in trigger function in a single miss. This
will cause a problem when we try to add a new replacement policy to
the Ruby system. Certain policy, like RRIP, will modify the block
information every time the getVictim() function gets called. To
prevent future problems, we need to store the victim entry, so that
we only call it once in one miss.
Change-Id: Ic5ca05f789d9bbfb963b8e993ef707020f243702
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21099
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Mon, 23 Sep 2019 20:52:58 +0000 (13:52 -0700)]
ext: Updated Pybind11 to version 2.4.1.
This updates Pybind11 from version 2.2.1 to version 2.4.1. This fixes
warning/error received when "<experiment/optional>" is used when
compiling using c++14 with clang. It should be noted that
"ext/pybind11/include/pybind11/std.h" has been changed to include a fix
added by commit
ba42457254cc362eddc099f22b60d469cc6369e0. This is
necessary to avoid build errors.
Built: Linux (gcc, c++11) and MacOS (clang, c++14).
Tested: Ran quick tests for X86, ARM, and RISC-V.
Deprecates: https://gem5-review.googlesource.com/c/public/gem5/+/21019
Change-Id: Ie9783511cb6be50136076a55330e645f4f36d075
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21119
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Fri, 13 Sep 2019 17:23:33 +0000 (18:23 +0100)]
cpu: Fix checker cpu instantiation
This change uses the params as instantiated from the default
constructor to create the checker cpu. If any of these parameters are
invalid for the checker cpu, the simulation will exit with a warning.
Change-Id: I0e58ed096c9ea5f413f2e9b64d8d184d9b0fc84e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21079
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jordi Vaquero [Tue, 10 Sep 2019 22:11:27 +0000 (00:11 +0200)]
cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>
This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.
Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.
This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr<AtomicOpFunctor> and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.
Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 11 Sep 2019 20:32:35 +0000 (13:32 -0700)]
mem: Delete the now unused Message*Port classes.
This port type is no longer used.
Change-Id: If4abbb774819644bea58fd82e00dfdec8f79b5a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20822
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 11 Sep 2019 20:26:09 +0000 (13:26 -0700)]
x86: Templatize the IntMasterPort.
This makes the IntMasterPort usable with any class, making it possible
to avoid inheriting from IntDevice.
It also makes IntMasterPort inherit directly from QueuedMasterPort,
skipping over MessageMasterPort.
Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 11 Sep 2019 00:24:47 +0000 (17:24 -0700)]
x86: Templatize IntSlavePort.
This makes the device IntSlavePort calls back into based on a template
parameter so that IntDevice doesn't have to be in the inheritance
hierarchy to use it.
It also makes IntSlavePort inherit from SimpleTimingPort directly,
skipping over MessageSlavePort.
Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Tue, 10 Sep 2019 00:44:54 +0000 (17:44 -0700)]
x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.
This will let us accept several address ranges through our pio port
instead of just one, and that will in turn let us accept interrupt
requests and pio requests through the same port.
Change-Id: I70b78c8cd0edca7fe58b3d4cd241e41d9e0f2c20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20819
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jing Qu [Mon, 16 Sep 2019 23:30:28 +0000 (18:30 -0500)]
gpu-compute: Fix overriden errors
When building Gem5 with GPU protocols, overriden errors were thrown
from files in gpu-compute. After adding override to the files, the
errors were resolved and Gem5 builds successfully.
Change-Id: Iab3a0768caf82c226e8bbee5690a834bf92d1e03
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20939
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Fri, 6 Sep 2019 22:14:00 +0000 (15:14 -0700)]
dev, x86: Delete the now unused X86 specific interrupt pins/lines.
Change-Id: I3915f0ad673119b551dcc4c5cedec180a9b88735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20702
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Fri, 6 Sep 2019 22:22:22 +0000 (15:22 -0700)]
dev, x86: Convert x86 devices to the generic int pins.
Change-Id: I4551ad00cf205c31555c90b53e87bc206a8d8729
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20701
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Pouya Fotouhi [Mon, 26 Aug 2019 22:59:36 +0000 (17:59 -0500)]
arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts
Making the implementation of movntps/movntpd consistent with other
non-temporal instructions. We are ignoring the hint here, and
implementing those instructions as cacheable instructions.
This change adds a warning to let user know about this workaround.
Also, this change add the address check for second part of move.
Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andrea Mondelli [Tue, 17 Sep 2019 18:20:37 +0000 (14:20 -0400)]
dev: Terminal output's dump name conflicts
The recently Terminal dump options name introduced
in patch
1c72e90 conflict with MacOS stdio.h header.
From stdio.h:
#define stdin __stdinp
#define stdout __stdoutp
#define stderr __stderrp
To remove this conflict, the TerminalDump options are renamed.
Change-Id: I1b60fa1031328fc32d6a58bf7889b6e479d95219
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20959
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Wed, 18 Sep 2019 23:50:19 +0000 (16:50 -0700)]
arch-x86: Change warn to warn_once for NT instructions
Change-Id: I50353716f2a913b9b106b140644d95991879f662
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 19 Sep 2019 03:27:13 +0000 (20:27 -0700)]
python: Don't try to bind a stat group to the NULL simobject.
That is a SimObject like object which is used when a SimObject
parameter is purposefully left empty, vs. being accidentally left
empty through a typo or accidental ommission.
It doesn't have a getCCObject method, and attempting to use it anyway
causes gem5 to crash.
Change-Id: Ie86321fbdbcc41cf88b7009184423acd7b64484b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21059
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Wed, 18 Sep 2019 17:21:44 +0000 (10:21 -0700)]
misc: Update MAINTAINERS
Change-Id: I13ca12d4dd170ce3db03d851829df9bc62d1a74c
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20999
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 12 Aug 2019 10:55:54 +0000 (11:55 +0100)]
dev-arm: Conditionally enable HDLcd when doing DTB autogen
This is a preparation change for a real DTB autogen implementation
Change-Id: Ia0c1c5e65ea96036e55455eb4222cec12944d33a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20331
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 12 Aug 2019 18:56:00 +0000 (19:56 +0100)]
dev-arm: Add HDLcd DTB autogeneration
A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:
system/arm/dt/armv8.dts
Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 5 Sep 2019 09:52:47 +0000 (10:52 +0100)]
arch-arm: PSTATE.PAN changes should inval cached regs in TLB
Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Adrian Herrera [Thu, 12 Sep 2019 11:34:07 +0000 (12:34 +0100)]
system-arm: Add ITS node in platforms/vexpress_gem5_v2_base.dtsi
This is aligning sources with DTB autogeneration
Change-Id: Icf369eb85719c91da770398b45645d8b03d8abf3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 31 Jul 2019 08:41:48 +0000 (09:41 +0100)]
arch-arm: Fix Data Abort ISS when caused by Atomic operation
Data Aborts caused by an atomic instruction have a special rule for
their syndrome:
From a ISS point of view they count as read if a read to that address
would generate a fault; they count as writes otherwise (ISS.WnR bit)
This patch is implementing this in the TLB. For permission faults we
need to explicitly check if a read would trigger a fault
(e.g. checking for the AP bits) since permissions can allow read-only
accesses.
For other MMU exceptions (like translation faults) we are confident the
nature of the access doesn't affect the genration of a fault.
This means that if the access is atomic, we treat it as a read from an
ISS.WnR point of view.
Change-Id: Ia524aa6ae07f81513cdc26c516b5fd9b01a931c3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20981
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 6 Sep 2019 13:44:47 +0000 (14:44 +0100)]
arch-arm: ISV bit in DataAbort should check for translation stage
According to the ESR spec, the ISV bit is set to 1 only for stage 2
aborts.
Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 9 Sep 2019 11:56:48 +0000 (12:56 +0100)]
arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1
Change-Id: I6df0cdcbadca17f30d3de3bed887f75c739b00f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20979
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sat, 7 Sep 2019 00:14:59 +0000 (17:14 -0700)]
arch, x86: Rework the debug faults and microops.
This makes the non-fatal microops advance the PC, and adds missing
functions. The *_once Faults now also can be run once per *something*.
They would previously be run once per Fault invoke function which is
common to all M5WarnOnceFaults. The warn_once microop will now warn
once per message.
Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Fri, 13 Sep 2019 22:02:53 +0000 (15:02 -0700)]
systemc: Make TLM port wrappers for tlm_base_(target|initiator)_socket.
These are useful if using TLM sockets without using the standard TLM
protocol. For instance, when used with ARM's fast models, this can wrap
sockets which carry the opaque GICv3Comms protocol.
Change-Id: I329a919068f958abbde2cb83683d3a3ae2e05a20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20860
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 29 Aug 2019 00:03:42 +0000 (17:03 -0700)]
systemc: Expose the utility functions for payload->packet conversion.
These can be used anywhere someone needs to turn a packet into a
payload or vice-versa.
Change-Id: I26a1f134e6fbec81b230a2853cf79264e80bf2dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20859
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 14 Aug 2019 10:36:58 +0000 (11:36 +0100)]
dev-arm: Allow IOMMU binding to HDLcd
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 14 Aug 2019 10:36:22 +0000 (11:36 +0100)]
dev-arm: Store the IOMMU reference from within the SMMU::connect
Change-Id: I35718a71dc040ee4acad9eee2a07076ebb571304
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20840
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 14 Aug 2019 10:35:51 +0000 (11:35 +0100)]
dev: Enable DTB IOMMU binding with a DMA object
This happens by storing a iommu reference in the dma device, and by
calling the addIommuProperty method once doing dtb autogeneration for
the device
Change-Id: Ibd585addac686a9eeaba6959f459d81901087549
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20839
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 12 Sep 2019 00:12:54 +0000 (17:12 -0700)]
sparc: Fix a warning/error in tlb.cc.
gcc has started to not like memseting an ojbect to zero in some cases.
Cast the TlbEntry pointer to a void * before memsetting it to placate
gcc.
Change-Id: Iccb3c326fdb82f1f111329ff1a80bb6719cace47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20830
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 5 Sep 2019 00:10:02 +0000 (17:10 -0700)]
dev: Generalize the x86 int source/sink pins.
Sink pins are now templated based on the underlying device types, and
the pins themselves are based on the new, generalized Port mechanism.
Change-Id: I09c678c56f6eb6b4a167c12f221ae0241fe99c2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20700
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Thu, 1 Aug 2019 08:21:15 +0000 (10:21 +0200)]
mem-cache: Fix BDI size calculation
The bitmask field indicates to which base a delta refers, and in
the original paper it is fixed and proportional to the highest
number of bases allowed in the compressed data.
Change-Id: I271bf2e19e0765de52b933eaf6d4fcc2ce25d185
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19748
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>