git.libre-soc.org Git - nmigen.git/log

whitequark [Wed, 12 Dec 2018 10:52:32 +0000 (10:52 +0000)]

genlib.cdc.MultiReg: self.regs should be a private field.

whitequark [Wed, 12 Dec 2018 10:43:09 +0000 (10:43 +0000)]

fhdl.ast.Signal: implement width derivation from min/max.

whitequark [Wed, 12 Dec 2018 10:12:35 +0000 (10:12 +0000)]

genlib.cdc.MultiReg: pull in from Migen.

whitequark [Wed, 12 Dec 2018 10:11:16 +0000 (10:11 +0000)]

fhdl.ast.Signal: implement reset_less signals.

whitequark [Wed, 12 Dec 2018 10:08:56 +0000 (10:08 +0000)]

fhdl.ast.Signal: assign an internal name if tracer fails.

whitequark [Wed, 12 Dec 2018 10:00:00 +0000 (10:00 +0000)]

fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.

whitequark [Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)]

ClockDomain.{rst→reset}, for consistency with ResetInserter.

nmigen.compat.ClockDomain would alias this, for Migen compatibility.

whitequark [Tue, 11 Dec 2018 20:50:56 +0000 (20:50 +0000)]

Initial commit.