Pierre-Eric Pelloux-Prayer [Fri, 24 Apr 2020 10:17:04 +0000 (12:17 +0200)]
radeonsi: don't print gs_copy_shader stats for shaderdb
Fixes: dbc86fa3de6 ("radeonsi: dump shader stats when hitting the live cache")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
Samuel Pitoiset [Mon, 4 May 2020 10:01:41 +0000 (12:01 +0200)]
radv: enable shaderInt16 unconditionally with LLVM and only GFX8+ with ACO
The Vulkan spec says:
"shaderInt16 specifies whether 16-bit integers (signed and unsigned)
are supported in shader code. If this feature is not enabled, 16-bit
integer types must not be used in shader code."
I think it's just safe to enable it because 16-bit integers should
be fully supported with LLVM and also with ACO and GFX8+. On GFX8
and earlier generations, throughput of 16-bit int is same as 32-bit
but that should't change anything.
For GFX6-GFX7 ACO support, we have to implement conversions without
SDWA.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4874>
Pierre-Eric Pelloux-Prayer [Fri, 24 Apr 2020 09:58:12 +0000 (11:58 +0200)]
radeonsi: add workaround for issue 2647
For unknown reasons pixel shaders in KSP game get executed with
infinite interpolation coefficients and this causes an infinite
loop in the shader.
This commit adds a hacky workaround that kills pixel shaders if
invalid interp coeffs are detected and enables it for KSP.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2174
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2647
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4700>
Erik Faye-Lund [Fri, 24 Apr 2020 15:13:45 +0000 (17:13 +0200)]
zink: use nir_lower_uniforms_to_ubo
Instead of open-coding uniform -> UBO lowering, let's instead use the
one that already exists. This should make things a bit simpler going
forward.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
Louis-Francis Ratté-Boulianne [Fri, 14 Feb 2020 07:14:07 +0000 (02:14 -0500)]
nir: Always create UBO variable when lowering uniforms to ubo
Zink needs to know the sizes of UBOs, and for normal UBOs we get this
from the nir_var_mem_ubo variables. This allows us to treat all of these
the same way.
We're about to need the same information for the in-progress D3D12
driver, so let's do this in a central location instead of in the driver.
This version is also a bit more careful than the Zink version. In
particular, for two reasons:
1. We increase the variable bindings when we adjust the pre-existing
UBOs.
2. We increase shader->info.num_ubos when we insert a new UBO variable.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
Erik Faye-Lund [Wed, 29 Apr 2020 10:29:46 +0000 (12:29 +0200)]
mesa/st: consider NumUniformBlocks instead of num_ubos when binding
This is the number of uniform blocks at linking time, not after
finalizing shaders.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
Erik Faye-Lund [Tue, 28 Apr 2020 11:28:16 +0000 (13:28 +0200)]
compiler/glsl: explicitly store NumUniformBlocks
It's not great to use shader_info for this information, because it
might have gone through lowering of uniforms to UBOs, which can change
the number of UBOs. So let's make sure we know the size of the
UniformBlocks array from when the shader was linked instead.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
Danylo Piliaiev [Mon, 4 May 2020 14:49:26 +0000 (17:49 +0300)]
glsl: rename has_implicit_uint_to_int_conversion to *_int_to_uint_*
There is no uint to int implicit conversion in glsl, this is just
a typo in the name of this function. The correct one would be:
has_implicit_int_to_uint_conversion.
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4884>
Pierre-Eric Pelloux-Prayer [Mon, 20 Apr 2020 12:20:28 +0000 (14:20 +0200)]
driconf: add force_integer_tex_nearest option
And enable it for "GRID Autosport" and "DIRT: Showdown" games.
CC: 20.1 <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1258
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4647>
Pierre-Eric Pelloux-Prayer [Mon, 20 Apr 2020 12:17:53 +0000 (14:17 +0200)]
mesa: add gl_coontext::ForceIntegerTexNearest
Some applications incorrectly use GL_LINEAR* values for integers texture.
copyimage.c already implemented a tolerance for such app in prepare_target_err.
This commit adds a boolean that will treat GL_LINEAR* filters as
GL_NEAREST for integer textures.
CC: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4647>
Samuel Pitoiset [Mon, 4 May 2020 12:40:56 +0000 (14:40 +0200)]
aco: remove unecessary p_split_vector with v2b reg class
Should be fine now that RA take full registers for v2b if it's
not an SDWA instruction.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4879>
Joshua Ashton [Mon, 4 May 2020 12:33:42 +0000 (13:33 +0100)]
vulkan: Update Vulkan XML and headers to 1.2.140
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
Joshua Ashton [Mon, 4 May 2020 12:36:41 +0000 (13:36 +0100)]
turnip: Remove RANGE_SIZE usage
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
Joshua Ashton [Mon, 4 May 2020 10:53:03 +0000 (11:53 +0100)]
radv: Remove RANGE_SIZE usage
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
Joshua Ashton [Mon, 4 May 2020 10:52:55 +0000 (11:52 +0100)]
anv: Remove RANGE_SIZE usage
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
Mauro Rossi [Sat, 2 May 2020 07:31:02 +0000 (09:31 +0200)]
android: iris: add iris_seqno.{c,h} to Makefile.sources
Fixes the following undefined symbol building errors:
ld.lld: error: undefined symbol: iris_seqno_init
>>> referenced by iris_batch.c:187 (external/mesa/src/gallium/drivers/iris/iris_batch.c:187)
>>> iris_batch.o:(iris_init_batch) in archive out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/libmesa_pipe_iris.a
Fixes: e31b703c ("iris: Place a seqno at the end of every batch")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Marek Olšák [Sat, 2 May 2020 14:56:20 +0000 (10:56 -0400)]
ac/surface: fix MSAA crash with FORCE_SWIZZLE_MODE on gfx9
Fixes: 3dc2ccc14c0e035 "ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE"
Closes: #2884
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4862>
Alyssa Rosenzweig [Mon, 4 May 2020 18:40:26 +0000 (14:40 -0400)]
pan/bit: Add IMATH packing tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:13:29 +0000 (14:13 -0400)]
pan/bit: Factor out identity swizzle helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:09:39 +0000 (14:09 -0400)]
pan/bit: Use swizzle helper for round
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:07:53 +0000 (14:07 -0400)]
pan/bit: Remove test names
We already have the disasm which is authoritative.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:37:21 +0000 (14:37 -0400)]
pan/bit: Interpret v4i8 ops
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:29:03 +0000 (14:29 -0400)]
pan/bit: Interpret IMATH
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:40:09 +0000 (14:40 -0400)]
pan/bi: Don't schedule <32-bit IMATH to FMA
The ops don't exist.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:38:12 +0000 (14:38 -0400)]
pan/bi: Add SUB.v2i16/SUB.v4i8 opcodes to disasm
Like their ADD counterparts. Only on ADD.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:37:04 +0000 (14:37 -0400)]
pan/bi: Pack ADD IADD/ISUB for 8/16/32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:28:47 +0000 (14:28 -0400)]
pan/bi: Pack FMA IADD/ISUB 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:04:35 +0000 (14:04 -0400)]
pan/bi: Use IMATH for nir_op_iadd
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Alyssa Rosenzweig [Mon, 4 May 2020 18:00:13 +0000 (14:00 -0400)]
pan/bi: Rename BI_ISUB to BI_IMATH
We'll use this for iadd, etc too which share similar characteristics.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
Eric Anholt [Fri, 1 May 2020 23:26:24 +0000 (16:26 -0700)]
freedreno/ir3: Define the bindful uniform/nonuniform desc modes for cat6 a6xx.
These come from the disasm tests, and fix our disasm of blob's
uniform/nonuniform cat6 operands. We also now include human-readable names
for all the modes we know about (though bindless gets distinguished by its
.baseN, like Connor's original disasm).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
Eric Anholt [Fri, 1 May 2020 21:37:27 +0000 (14:37 -0700)]
freedreno/ir3: Sync some new changes from envytools.
With this I also brought in a few new control flow instruction disasm
tests that I'd made back when I wrote the disasm test, but which were too
far from correct to include until now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
Eric Anholt [Fri, 24 Apr 2020 20:44:40 +0000 (13:44 -0700)]
freedreno/ir3: Add some more tests of cat6 disasm.
I put these together from traces I had while trying to do LDC for GL.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
Marek Olšák [Thu, 30 Apr 2020 07:57:50 +0000 (03:57 -0400)]
Revert "ac: reassociate FP expressions for inexact instructions for radeonsi"
This reverts commit
cf2f3c27533d8721abed4cdd4dfb00d4d53e8a0f.
It breaks shadows in Unigine Superposition.
Fixes: cf2f3c27533d8721abed4cdd4dfb00d4d53e8a0f
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4837>
Alyssa Rosenzweig [Sat, 2 May 2020 01:39:23 +0000 (21:39 -0400)]
pan/bit: Add ICMP tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 20:38:23 +0000 (16:38 -0400)]
pan/bit: Add more 16-bit fmod tests
Swizzles and more abs.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 20:13:09 +0000 (16:13 -0400)]
pan/bit: Add swizzles to round tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Sat, 2 May 2020 01:42:53 +0000 (21:42 -0400)]
pan/bi: Don't pack ICMP on FMA
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Sat, 2 May 2020 01:37:59 +0000 (21:37 -0400)]
pan/bi: Pack ADD ICMP 16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Sat, 2 May 2020 00:58:45 +0000 (20:58 -0400)]
pan/bi: Pack ADD ICMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Sat, 2 May 2020 00:48:51 +0000 (20:48 -0400)]
pan/bi: Structify ADD ICMP 16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:53:25 +0000 (18:53 -0400)]
pan/bi: Pack ADD.DISCARD
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:36:51 +0000 (18:36 -0400)]
pan/bi: Handle discard/branch in get_component_count
No dest requires special handling.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:36:42 +0000 (18:36 -0400)]
pan/bi: Fuse conditions into discard_if
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:31:22 +0000 (18:31 -0400)]
pan/bi: Add float-only mode to condition fusing
Useful for discards.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:26:18 +0000 (18:26 -0400)]
pan/bi: Emit discard (not if)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:24:11 +0000 (18:24 -0400)]
pan/bi: Handle discard_if in NIR->BIR naively
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:13:54 +0000 (18:13 -0400)]
pan/bi: Unwrap BRANCH into CONDITIONAL class
We can simplify the IR considerably and unify more conditions, which
gives conditional discard for free.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:07:55 +0000 (18:07 -0400)]
pan/bi: Remove BI_GENERIC
Goofy.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 22:06:49 +0000 (18:06 -0400)]
pan/bi: Structify DISCARD
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Mon, 4 May 2020 15:02:33 +0000 (11:02 -0400)]
pan/bi: Fix DISCARD ops in disasm
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 21:34:47 +0000 (17:34 -0400)]
pan/bi: Disable CSEL4 emit for now
We need proper scheduling for 4-src ops to work, so for now disable
condition fusing so we cap at 3-src at a performance penalty. A bit of a
hack but I'd rather not build hacks into a scheduler that will be
rewritten soon anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 20:38:11 +0000 (16:38 -0400)]
pan/bi: Fix incorrectly flipped swizzle
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 20:38:02 +0000 (16:38 -0400)]
pan/bi: Fix missing swizzle
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 20:37:51 +0000 (16:37 -0400)]
pan/bi: Fix double-abs flipping
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 20:12:55 +0000 (16:12 -0400)]
pan/bi: Set clause type for gl_FragCoord.z
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 18:55:04 +0000 (14:55 -0400)]
pan/bi: Lower gl_FragCoord
We accept a sysval and emit various forms for each component.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 18:54:40 +0000 (14:54 -0400)]
pan/bi: Passthrough direct ld_var addresses
Don't bother wasting a constant.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 18:54:20 +0000 (14:54 -0400)]
pan/bi: Print bad instruction on src packing fail
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 18:53:58 +0000 (14:53 -0400)]
pan/bi: Futureproof COMBINE lowering against non-u32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 18:13:10 +0000 (14:13 -0400)]
pan/bi: Abort on unhandled intrinsics
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 18:12:06 +0000 (14:12 -0400)]
pan/bi: Abort on unknown op packing
We're stable enough this is better than just nop'ing it out.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 15:37:21 +0000 (11:37 -0400)]
pan/bi: Add clause type for gl_FragCoord.zw load
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Alyssa Rosenzweig [Fri, 1 May 2020 16:05:01 +0000 (12:05 -0400)]
panfrost: Setup gl_FragCoord as sysval on Bifrost
..rather than a varying.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Christian Gmeiner [Tue, 28 Apr 2020 14:24:38 +0000 (16:24 +0200)]
etnaviv: do not use int filter when anisotropic filtering is used
The blob does not use this combination. This change moves the
decision if int filter gets used to state emit time.
Fixes: 7aaa0e59086 ("etnaviv: add anisotropic filter support")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4872>
Christian Gmeiner [Sun, 3 May 2020 06:54:47 +0000 (08:54 +0200)]
etnaviv: fix SAMP_ANISOTROPY register value
This caused some serious problems like shredded output, ~1fps and GPU hungs.
Fixes: 7aaa0e59086 ("etnaviv: add anisotropic filter support")
Reported-by: Lukas F. Hartmann <lukas@mntmn.com>
Tested-by: Lukas F. Hartmann <lukas@mntmn.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4872>
Jason Ekstrand [Tue, 21 Apr 2020 22:00:39 +0000 (17:00 -0500)]
vulkan/wsi: Make wsi_swapchain inherit from vk_object_base
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Tue, 21 Apr 2020 20:51:01 +0000 (15:51 -0500)]
vulkan: Add run-time object type asserts in handle casts
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Wed, 22 Apr 2020 15:47:00 +0000 (10:47 -0500)]
anv: Refactor setting descriptors with immutable sampler
Don't call anv_sampler_from_handle if the handle may be invalid.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Tue, 21 Apr 2020 20:03:58 +0000 (15:03 -0500)]
vulkan,anv: Move the DEFINE_HANDLE_CASTS macros to vk_object.h
We've already got these duplicated a bunch of places. They should
really probably live in common code. The new versions take two more
arguments:
1. The struct member which gets you from __driver_type to the
vk_object_base. This requires drivers which use this to also use
vk_object_base.
2. The VkObjectType enum which represents that object type.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Tue, 21 Apr 2020 17:33:16 +0000 (12:33 -0500)]
vulkan,anv: Add a base object struct type
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Wed, 22 Apr 2020 17:23:24 +0000 (12:23 -0500)]
anv: Allocate CPU-side memory for events
As discrete graphics looms, we really need to stop storing CPU data
structures in GPU memory. One of the most egregious instances of this
was VkEvent where we had a CPU data structure living inside a dynamic
state pool allocation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Wed, 22 Apr 2020 17:19:41 +0000 (12:19 -0500)]
anv: Stop clflushing events
They're allocated out of the dynamic state pool which is snooped.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Tue, 21 Apr 2020 17:42:59 +0000 (12:42 -0500)]
vulkan,anv: Add a common base object type for VkDevice
We should keep this very minimal; I don't know that we need to go all
struct gl_context on it. However, this gives us at least a tiny base on
which we can start building some common functionality.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Jason Ekstrand [Tue, 21 Apr 2020 16:29:21 +0000 (11:29 -0500)]
vulkan: Allow destroying NULL debug report callbacks
Fixes: 086cfa5652 "anv: implementation of VK_EXT_debug_report extension"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
Tapani Pälli [Thu, 30 Apr 2020 10:03:48 +0000 (13:03 +0300)]
st/mesa: destroy only own program variants when program is released
Earlier commit tried to achieve this but actually did more. This makes
sure the variants for other contexts continue to live.
Fixes: de3d7dbed52 ("mesa/st: release variants for active programs before unref")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2865
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4831>
Pierre-Eric Pelloux-Prayer [Mon, 4 May 2020 08:50:47 +0000 (10:50 +0200)]
radeonsi: fix export count
Fixes: 17acff01a00 ("radeonsi: skip vs output optimizations for some outputs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2877
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4871>
Erik Faye-Lund [Wed, 29 Apr 2020 16:39:12 +0000 (18:39 +0200)]
vtn/opencl: native sqrt support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Wed, 29 Apr 2020 16:31:44 +0000 (18:31 +0200)]
vtn/opencl: native rsqrt support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Wed, 29 Apr 2020 16:30:08 +0000 (18:30 +0200)]
vtn/opencl: native recip support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Wed, 29 Apr 2020 16:28:26 +0000 (18:28 +0200)]
vtn/opencl: native powr support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Wed, 29 Apr 2020 16:25:43 +0000 (18:25 +0200)]
vtn/opencl: native divide support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Wed, 29 Apr 2020 16:23:11 +0000 (18:23 +0200)]
vtn/opencl: native variants of sin/cos
These obviously map directly to nir opcodes.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Mon, 16 Mar 2020 12:00:27 +0000 (13:00 +0100)]
vtn/opencl: add native_tan-support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Erik Faye-Lund [Mon, 16 Mar 2020 11:57:48 +0000 (12:57 +0100)]
compiler/nir: move tan-calculation to helper
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4811>
Dmitriy Nester [Thu, 30 Apr 2020 13:25:04 +0000 (16:25 +0300)]
mesa: check draw buffer completeness on glClearBufferfv/glClearBufferuiv
From OpenGL 4.6, section 9.4.4 "Effects of Framebuffer Completeness on
Framebuffer Operations", page 332:
"An INVALID_FRAMEBUFFER_OPERATION error is generated by attempts to render
to or read from a framebuffer which is not framebuffer complete.
This error is generated regardless of whether fragments are actually read
from or written to the framebuffer. For example, it is generated when a
rendering command is called and the framebuffer is incomplete, even if
RASTERIZER_DISCARD is enabled."
Signed-off-by: Dmytro Nester <dmytro.nester@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4833>
Marek Olšák [Sat, 2 May 2020 20:01:44 +0000 (16:01 -0400)]
Revert "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"
This reverts commit
f6d87ec8a908250af5e805c8042524ac360094a2.
It breaks RADV.
Fixes: f6d87ec8a908250af5e805c8042524ac360094a2 "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4864>
Dave Airlie [Fri, 1 May 2020 03:28:56 +0000 (13:28 +1000)]
i965: disable shadow batches when batch debugging.
If you want to dump batch state, it needs to have the relocs processed
but the relocs don't get processed on the shadow batch.
Choose debugging over speed here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4846>
Dave Airlie [Fri, 1 May 2020 01:22:20 +0000 (11:22 +1000)]
i965: add support for gen 5 pipelined pointers to dump
I wanted to see inside these, so added support to the dumper.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4846>
Bas Nieuwenhuizen [Sat, 2 May 2020 11:59:59 +0000 (13:59 +0200)]
radv: Extend tiling flags to 64-bit.
SCANOUT is bit 63 ....
Fixes: bfd9e7ff243 "radv: Use new scanout gfx9 metadata flag."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2879
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4859>
Rhys Perry [Fri, 1 May 2020 16:14:51 +0000 (17:14 +0100)]
aco: add message to static_assert
static_assert without a message is only supported with C++17 and later.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: c99107ece02b64916031883889b9e010c99e2435
('aco: add explicit padding for all Instruction sub-structs')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4850>
Rhys Perry [Fri, 1 May 2020 15:42:05 +0000 (16:42 +0100)]
aco: remove use of f-strings
f-strings require Python 3.6 but 3.5 is still maintained and used.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2839
Fixes: 2ab45f41 ("aco: implement sub-dword swaps")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4850>
Nataraj Deshpande [Tue, 28 Apr 2020 19:42:45 +0000 (12:42 -0700)]
anv: Disable extensions based on Android versions
This extends commit
2243f0cd for anv with additional
extensions for Pie and Q versions.
Fixes tests with 9_R11 CTS:
dEQP-VK.api.info.android#no_unknown_extensions
dEQP-VK.api.info.device#extensions.
v2: Use snake_case function name (Jason Ekstrand)
Drop Change-Id in commit (Kristian H. Kristensen)
v3: Resolve meson-clang error for ANDROID_API_LEVEL.
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4827>
Nataraj Deshpande [Tue, 28 Apr 2020 00:43:08 +0000 (17:43 -0700)]
anv: Limit vulkan version to 1.1 for Android
Current Android dessert versions such as Pie, Q reject
vulkan version > 1.1. Clamp the vulkan versions to 1.1
for platforms running these Android desserts.
Fixes android.graphics.cts.VulkanFeaturesTest and
dEQP-VK.api.info.device#properties.
v2: Limit version with '!ANDROID' (Eric Engestrom and Tapani Pälli)
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4781>
Caio Marcelo de Oliveira Filho [Tue, 28 Apr 2020 21:03:47 +0000 (14:03 -0700)]
iris: Implement ARB_compute_variable_group_size
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
Caio Marcelo de Oliveira Filho [Tue, 28 Apr 2020 20:28:02 +0000 (13:28 -0700)]
intel: Let drivers call brw_nir_lower_cs_intrinsics()
The motivating factor is: this lowering may cause
nir_intrinsic_load_local_group_size intrinsics to be added to the
shader, and by moving this around we make possible for the drivers to
lower that intrinsic by themselves.
Iris will do just that in a later patch for implementing variable
group size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
Caio Marcelo de Oliveira Filho [Tue, 28 Apr 2020 20:09:27 +0000 (13:09 -0700)]
intel/fs: Add and use a new load_simd_width_intel intrinsic
Intrinsic to get the SIMD width, which not always the same as subgroup
size. Starting with a small scope (Intel), but we can rename it later
to generalize if this turns out useful for other drivers.
Change brw_nir_lower_cs_intrinsics() to use this intrinsic instead of
a width will be passed as argument. The pass also used to optimized
load_subgroup_id for the case that the workgroup fitted into a single
thread (it will be constant zero). This optimization moved together
with lowering of the SIMD.
This is a preparation for letting the drivers call it before the
brw_compile_cs() step.
No shader-db changes in BDW, SKL, ICL and TGL.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
Caio Marcelo de Oliveira Filho [Tue, 28 Apr 2020 16:47:45 +0000 (09:47 -0700)]
intel/fs: Add an option to lower variable group size in backend
Adding this since Iris will handle variable group size parameters by
itself.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
Caio Marcelo de Oliveira Filho [Wed, 29 Apr 2020 04:04:04 +0000 (21:04 -0700)]
intel/fs: Clean up variable group size handling in backend
Just use the information from NIR shader_info.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4794>
Kenneth Graunke [Mon, 5 Aug 2019 20:18:39 +0000 (13:18 -0700)]
iris: Implement PIPE_FLUSH_DEFERRED support.
(Co-authored with Chris Wilson.)
Frequently, games create fences and later check them with a timeout of
0 to see if that work has completed yet. They do not want the work to
be flushed immediately upon fence creation.
This is what PIPE_FLUSH_DEFERRED does - it inhibits the flush at fence
creation time, but still guarantees that a flush will occur later on
once fence_finish() is called.
Since syncpts can only occur at batch boundaries, when deferring a
flush, we have to wait for the syncpt at the end of the batch being
constructed. This is later than desired, but safe if blocking. To
avoid extra delays, we additionally insert a PIPE_CONTROL to write an
availability bit at the exact point of the fence. We can poll this
on the CPU, allowing us to check whether the fence has gone by, even
if the batch hasn't completed. It can also let us skip kernel calls.
Improves performance in Bioshock Infinite by 10% on Icelake GT2 on
-ForceCompatLevel=5 settings. Thanks to Felix Degrood and Mark Janes
for helping notice the extraneous stalls and batches, Marek Olšák for
adding deferred flush support to Gallium to solve this issue, and
Chris Wilson for reworking a lot of the internals of this work.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
Kenneth Graunke [Wed, 29 Apr 2020 20:53:50 +0000 (13:53 -0700)]
iris: Detect DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT kernel support
We will use this for implementing deferred flushes in the next commit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
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