Daily bump.

From-SVN: r237936

re PR fortran/71687 (ICE in omp_add_variable, at gimplify.c:5821)

PR fortran/71687
* f95-lang.c (struct binding_level): Add reversed field.
(clear_binding_level): Adjust initializer.
(getdecls): If reversed is clear, set it and nreverse the names
chain before returning it.
(poplevel): Use getdecls.
* trans-decl.c (gfc_generate_function_code, gfc_process_block_locals):
Use nreverse to pushdecl decls in the declaration order.

* gfortran.dg/gomp/pr71687.f90: New test.

From-SVN: r237926

const-float128-ped.c: Require __float128 effective target and options.

2016-07-01  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.dg/const-float128-ped.c: Require __float128 effective
target and options.
* gcc.dg/const-float128.c: Likewise.
* gcc.dg/torture/float128-cmp-invalid.c: Require
__float128 and base_quadfloat_support effective targets, and
__float128 options.
* gcc.dg/torture/float128-div-underflow.c: Likewise.
* gcc.dg/torture/float128-extend-nan.c: Likewise.
* gcc.dg/torture/float128-nan.c: Likewise.
* gcc.dg/torture/fp-int-convert-float128-timode-2.c: Likewise.
* gcc.dg/torture/fp-int-convert-float128-timode-3.c: Likewise.
* gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise.
* lib/target-supports.exp (check_effective_target___float128):
New.
(add_options_for___float128): New.
(check_effective_target_base_quadword_support): New.

From-SVN: r237924

update changelog

From-SVN: r237921

re PR target/71720 (initialization of a vector of floats generates incorrect code for -mcpu=power9)

[gcc]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/71720
* config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
the insns, use vsx_xxspltw_v4sf_direct which does not check for
little endian.

[gcc/testsuite]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/71720
* gcc.target/powerpc/pr71720.c: New test.

From-SVN: r237920

re PR fortran/71717 (A gfortran silent "wrong code" bug in the transition from 4.9.0 -> 4.9.1, using OpenMP.)

PR fortran/71717
* trans-openmp.c (gfc_omp_privatize_by_reference): Return false
for GFC_DECL_ASSOCIATE_VAR_P with POINTER_TYPE.

* testsuite/libgomp.fortran/associate3.f90: New test.

From-SVN: r237916

check initializer to be zero in .bss-like sections

Just like gas, which has recently learned to reject such initializers,
gcc shouldn't accept such either.

gcc/
2016-07-01  Jan Beulich  <jbeulich@suse.com>

* varasm.c (get_variable_section): Validate initializer in
named .bss-like sections.

gcc/testsuite/
2016-07-01  Jan Beulich  <jbeulich@suse.com>

* gcc.dg/bss.c: New.

From-SVN: r237913

altivec.md (*altivec_vpermr_<mode>_internal): Exchange the order of the second and third operands in the vpermr instruction...

gcc/ChangeLog:

2016-07-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal):
Exchange the order of the second and third operands in the vpermr
instruction tmeplate.

From-SVN: r237912

re PR target/71698 (ICE related to decimal float when compiling with -mcpu=power9)

gcc/
PR target/71698
* config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow
TDmode values.

gcc/testsuite/
PR target/71698
* gcc.target/powerpc/pr71698.c: New test.

From-SVN: r237911

re PR target/71151 ([avr] -fmerge-constants and -fdata-sections/-ffunction-sections results in string constants in .progmem.gcc_sw section)

gcc/testsuite/
PR target/71151
* gcc.target/avr/pr71151-common.h (foo): Use macro SECTION_NAME
instead of ".foo" for its section name.
* gcc.target/avr/pr71151-2.c (SECTION_NAME): Define appropriately
depending on MCU's flash size.
* gcc.target/avr/pr71151-3.c (SECTION_NAME): Dito.
* gcc.target/avr/pr71151-4.c (SECTION_NAME): Dito.
* gcc.target/avr/pr71151-5.c (SECTION_NAME): Dito.
* gcc.target/avr/pr71151-6.c (SECTION_NAME): Dito.
* gcc.target/avr/pr71151-7.c (SECTION_NAME): Dito.
* gcc.target/avr/pr71151-8.c (SECTION_NAME): Dito.

From-SVN: r237910

strcpy arg optimised out

For functions that return an argument unchanged, like strcat,
find_call_crossed_cheap_reg attempts to find an assignment between
a pseudo reg and the arg reg before the call, so that uses of the
pseudo after the call can instead use the return value.  The exit
condition on the loop looking at previous insns was wrong.  Uses of
the arg reg don't matter.  What matters is the insn setting the arg
reg as any assignment involving the arg reg prior to that insn is
likely a completely unrelated use of the hard reg.

PR rtl-optimization/71709
* ira-lives.c (find_call_crossed_cheap_reg): Exit loop on arg reg
being set, not referenced.

From-SVN: r237909

ix86: fix PR/65105 testcase 2

I cannot see how without allowing the compiler to use SSE2 instructions
(as is done by all other tests for this PR scanning for particular
instructions) this test could ever have succeeded anywhere.

gcc/testsuite/
2016-07-01  Jan Beulich  <jbeulich@suse.com>

* gcc.target/i386/pr65105-2.c: Add -msse2.

From-SVN: r237908

re PR tree-optimization/70729 (Loop marked with omp simd pragma is not vectorized)

PR tree-optimization/70729

gcc/
* tree-vectorizer.c (adjust_simduid_builtins): Nullify safelen field
of loop since it can be not valid after transformation.

From-SVN: r237907

[ARM] Delete thumb_reload_in_h

* config/arm/arm.c (thumb_reload_in_hi): Delete.
* config/arm/arm-protos.h (thumb_reload_in_hi): Delete prototype.

From-SVN: r237906

arm.c (arm_function_ok_for_sibcall): Add another check for NULL decl.

* config/arm/arm.c (arm_function_ok_for_sibcall): Add another check
for NULL decl.

From-SVN: r237903

Daily bump.

From-SVN: r237902

re PR target/71677 (PowerPC ISA 3.0 DImode load/store needs a fix)

2016-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/71677
* config/rs6000/constraints.md (wY constraint): New constraint to
match the requirements for the LXSD and STXSD instructions.
* config/rs6000/predicates.md (offsettable_mem_14bit_operand): New
predicate to match the requirements for the LXSD and STXSD
instructions.
* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case):
Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y'
to make sure that the bottom 2 bits of offset are 0, the address
form is offsettable, and no updating is done in the address mode.
(mov<mode>_hardfloat64, FMOVE64 case): Likewise.
(movdi_internal32): Likewise
(movdi_internal64): Likewise.

From-SVN: r237898

re PR tree-optimization/71707 (ICE in get_stridx_plus_constant)

PR tree-optimization/71707
* tree-ssa-strlen.c (get_stridx_plus_constant): Handle already present
strinfo even for ADDR_EXPR ptr.

* gcc.dg/strlenopt-29.c: New test.

From-SVN: r237889

re PR fortran/71704 (ICE with -fopenmp and some omp constructs)

PR fortran/71704
* parse.c (matchs, matcho): Move right before decode_omp_directive.
If spec_only, only gfc_match the keyword and if successful, goto
do_spec_only.
(matchds, matchdo): Define.
(decode_omp_directive): Add spec_only local var and set it.
Use matchds or matchdo macros instead of matchs or matcho
for declare target, declare simd, declare reduction and threadprivate
directives.  Return ST_GET_FCN_CHARACTERISTICS if a non-declarative
directive could be matched.
(next_statement): For ST_GET_FCN_CHARACTERISTICS restore
gfc_current_locus from old_locus even if there is no label.

* gfortran.dg/gomp/pr71704.f90: New test.

From-SVN: r237888

re PR fortran/71705 (ICE in lower_omp_target, at omp-low.c:16136)

PR fortran/71705
* trans-openmp.c (gfc_trans_omp_clauses): Set TREE_ADDRESSABLE on
decls in to/from clauses.

* gfortran.dg/gomp/pr71705.f90: New test.

From-SVN: r237887

altivec.md (darn_32): Change the condition to TARGET_P9_MISC instead of TARGET_MODULO.

gcc/ChangeLog:

2016-06-30  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* config/rs6000/altivec.md (darn_32): Change the condition to
TARGET_P9_MISC instead of TARGET_MODULO.
(darn_raw): Replace TARGET_MODULO with TARGET_P9_MISC in the
condition expression.
(darn): Replace TARGET_MODULO with TARGET_P9_MISC in the
condition expression.
* config/rs6000/dfp.md (UNSPEC_DTSTSFI): New unspec constant.
(DFP_TEST): New code iterator.
(dfptstsfi_<code>_mode>): New define_expand.
(*dfp_sgnfcnc_<mode>): New define_insn.
* config/rs6000/rs6000-builtin.def (BU_P9_MISC_0): Move this macro
definition next to BU_P9_MISC_1 definition and change the MASK
value to RS6000_BTM_P9_MISC.
(BU_P9_MISC_1): Change the MASK value to RS6000_BTM_P9_MISC.
(BU_P9_64BIT_MISC_0): Likewise.
(BU_P9_DFP_MISC_0): New macro definition.
(BU_P9_DFP_MISC_1): New macro definition.
(BU_P9_DFP_MISC_2): New macro definition.
(BU_P9_DFP_OVERLOAD_1): New macro definition.
(BU_P9_DFP_OVERLOAD_2): New macro definition.
(BU_P9_DFP_OVERLOAD_3): New macro definition.
(TSTSFI_LT_DD): New BU_P9_DFP_MISC_2.
(TSTSFI_LT_TD): Likewise.
(TSTSFI_EQ_DD): Likewise.
(TSTSFI_EQ_TD): Likewise.
(TSTSFI_GT_DD): Likewise.
(TSTSFI_GT_TD): Likewise.
(TSTSFI_OV_DD): Likewise.
(TSTSFI_OV_TD): Likewise.
(TSTSFI_LT): New BU_P9_DFP_OVERLOAD_2.
(TSTSFI_LT_DD): Likewise.
(TSTSFI_LT_TD): Likewise.
(TSTSFI_EQ): Likewise.
(TSTSFI_EQ_DD): Likewise.
(TSTSFI_EQ_TD): Likewise.
(TSTSFI_GT): Likewise.
(TSTSFI_GT_DD): Likewise.
(TSTSFI_GT_TD): Likewise.
(TSTSFI_OV): Likewise.
(TSTSFI_OV_DD): Likewise.
(TSTSFI_OV_TD): Likewise.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
overloaded test significance functions.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
OPTION_MASK_P9_MISC into the representation of this mask.
(POWERPC_MASKS): Add OPTION_MASK_P9_MISC into the representation
of this mask.
* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Set the
RS6000_BTM_P9_MISC flag in the return value if TARGET_P9_MISC is
non-zero.
(rs6000_expand_binop_builtin): Enforce that argument 0 of the exp
argument is a 6-bit unsigned literal value if the icode argument
represents a DFP test significance built-in call.
(rs6000_invalid_builtin): Add support for the RS6000_BTM_P9_MISC
flag used independently and in combination with the
RS6000_BTM_64BIT flag.
(rs6000_opt_masks): Add entry for power9-misc command-line option.
(rs6000_builtin_mask_names): Add entry for power9-misc
command-line option.
* config/rs6000/rs6000.h: Redefine TARGET_P9_MISC as 0 if
HAVE_AS_POWER9 is not a defined macro.  Define MASK_P9_MISC and
RS6000_BTM_P9_MISC macros.
* config/rs6000/rs6000.opt: Add support for the -mpower9-misc
option and change the description of the -mpower9-vector option to
enable only vector instructions, removing its erroneously claimed
support for scalar instructions.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Document
the ISA 3.0 digital floating point test significance built-in
functions.

gcc/testsuite/ChangeLog:

2016-06-30  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* gcc.target/powerpc/dfp/dfp.exp: New dejagnu test script.
* gcc.target/powerpc/dfp/dtstsfi-0.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-1.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-10.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-11.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-12.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-13.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-14.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-15.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-16.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-17.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-18.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-19.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-2.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-20.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-21.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-22.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-23.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-24.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-25.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-26.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-27.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-28.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-29.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-3.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-30.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-31.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-32.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-33.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-34.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-35.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-36.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-37.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-38.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-39.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-4.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-40.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-41.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-42.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-43.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-44.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-45.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-46.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-47.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-48.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-49.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-5.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-50.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-51.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-52.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-53.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-54.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-55.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-56.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-57.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-58.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-59.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-6.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-60.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-61.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-62.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-63.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-64.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-65.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-66.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-67.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-68.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-69.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-7.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-70.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-71.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-72.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-73.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-74.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-75.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-76.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-77.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-78.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-79.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-8.c: New test.
* gcc.target/powerpc/dfp/dtstsfi-9.c: New test.

From-SVN: r237885

This patch sets the branch cost to the same most optimal setting for all Cortex cores...

This patch sets the branch cost to the same most optimal setting for all Cortex
cores, reducing codesize and improving performance due to using more CSEL
instructions.  Set the autoprefetcher model in Cortex-A72 to weak like the
others.  Enable AES fusion in Cortex-A35.  As a result generated code is now
more similar as well as more optimal across Cortex cores.

    gcc/
* config/aarch64/aarch64.c (cortexa35_tunings):
Enable AES fusion.  Use cortexa57_branch_cost.
(cortexa53_tunings): Use cortexa57_branch_cost.
(cortexa72_tunings): Use cortexa57_branch_cost.
Use AUTOPREFETCHER_WEAK.
(cortexa73_tunings): Use cortexa57_branch_cost.

From-SVN: r237884

[AArch64][2/2] (Re)Implement vcopy<q>_lane<q> intrinsics

2016-06-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            James Greenhalgh  <james.greenhalgh@arm.com>

* config/aarch64/arm_neon.h (vcopyq_lane_f32, vcopyq_lane_f64,
vcopyq_lane_p8, vcopyq_lane_p16, vcopyq_lane_s8, vcopyq_lane_s16,
vcopyq_lane_s32, vcopyq_lane_s64, vcopyq_lane_u8, vcopyq_lane_u16,
vcopyq_lane_u32, vcopyq_lane_u64): Reimplement in C.
(vcopy_lane_f32, vcopy_lane_f64, vcopy_lane_p8, vcopy_lane_p16,
vcopy_lane_s8, vcopy_lane_s16, vcopy_lane_s32, vcopy_lane_s64,
vcopy_lane_u8, vcopy_lane_u16, vcopy_lane_u32, vcopy_lane_u64,
vcopy_laneq_f32, vcopy_laneq_f64, vcopy_laneq_p8, vcopy_laneq_p16,
vcopy_laneq_s8, vcopy_laneq_s16, vcopy_laneq_s32, vcopy_laneq_s64,
vcopy_laneq_u8, vcopy_laneq_u16, vcopy_laneq_u32, vcopy_laneq_u64,
vcopyq_laneq_f32, vcopyq_laneq_f64, vcopyq_laneq_p8, vcopyq_laneq_p16,
vcopyq_laneq_s8, vcopyq_laneq_s16, vcopyq_laneq_s32, vcopyq_laneq_s64,
vcopyq_laneq_u8, vcopyq_laneq_u16, vcopyq_laneq_u32, vcopyq_laneq_u64):
New intrinsics.

* gcc.target/aarch64/vect_copy_lane_1.c: New test.

Co-Authored-By: James Greenhalgh <james.greenhalgh@arm.com>
From-SVN: r237883

[AArch64][1/2] Add support INS (element) instruction to copy lanes between vectors

2016-06-30  James Greenhalgh  <james.greenhalgh@arm.com>
            Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

* config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
New define_insn.
(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.

* gcc.target/aarch64/vget_set_lane_1.c: New test.

Co-Authored-By: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
From-SVN: r237882

Fix bogus option suggestions for RejectNegative options (PR driver/71651)

gcc/ChangeLog:
PR driver/71651
* gcc.c (driver::build_option_suggestions): Pass "option" to
add_misspelling_candidates.
* opts-common.c (add_misspelling_candidates): Add "option" param;
use it to avoid adding negated forms for options marked with
RejectNegative.
* opts.h (add_misspelling_candidates): Add "option" param.

gcc/testsuite/ChangeLog:
PR driver/71651
* gcc.dg/spellcheck-options-12.c: New test case.

From-SVN: r237880

65913.cc: Require atomic-builtins rather than specific target.

2016-06-30  Thomas Preud'homme  <thomas.preudhomme@arm.com>

libstdc++-v3/
    * testsuite/29_atomics/atomic/65913.cc: Require atomic-builtins rather
    than specific target.

From-SVN: r237879

re PR middle-end/71693 (ICE: verify_gimple failed (type mismatch in shift expression, -O0, -O1, -O2, -O3))

PR middle-end/71693
* fold-const.c (fold_binary_loc) <case RROTATE_EXPR>: Cast
TREE_OPERAND (arg0, 0) and TREE_OPERAND (arg0, 1) to type
first when permuting bitwise operation with rotate.  Cast
TREE_OPERAND (arg0, 0) to type when cancelling two rotations.

* gcc.c-torture/compile/pr71693.c: New test.

From-SVN: r237875

Daily bump.

From-SVN: r237869

Offer suggestions for misspelled --param names.

gcc/ChangeLog:
* opts.c (handle_param): Use find_param_fuzzy to offer suggestions
for misspelled param names.
* params.c: Include spellcheck.h.
(find_param_fuzzy): New function.
* params.h (find_param_fuzzy): New prototype.
* spellcheck.c (struct edit_distance_traits<const char *>): Move
to...
* spellcheck.h (struct edit_distance_traits<const char *>):
...here.

gcc/testsuite/ChangeLog:
* gcc.dg/spellcheck-params.c: New testcase.
* gcc.dg/spellcheck-params-2.c: New testcase.

From-SVN: r237865

predicates.md (const_0_to_7_operand): New predicate, recognize 0..7.

[gcc]
2016-06-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config/rs6000/predicates.md (const_0_to_7_operand): New
predicate, recognize 0..7.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
support for doing extracts from V16QImode, V8HImode, V4SImode
under ISA 3.0.
* config/rs6000/vsx.md (VSX_EXTRACT_I): Mode iterator for ISA 3.0
vector extract support.
(VSX_EXTRACT_PREDICATE): Mode attribute to validate element number
for ISA 3.0 vector extract.
(VSX_EX): Constraints to use for ISA 3.0 vector extract.
(vsx_extract_<mode>, VSX_EXTRACT_I): Add support for doing
extracts of a constant element number from small integer vectors
on 64-bit ISA 3.0 systems.
(vsx_extract_<mode>_di): Likewise.
* config/rs6000/rs6000.h (TARGET_VEXTRACTUB): New target macro to
say when we can do ISA 3.0 vector extracts.
* config/rs6000/rs6000.md (stfiwx): Allow DImode in Altivec
registers, using the stxsiwx instruction.

[gcc/testsuite]
2016-06-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

* gcc.target/powerpc/p9-extract-1.c: New file to test ISA 3.0
vector extract instructions.
* gcc.target/powerpc/p9-extract-2.c: Likewise.

From-SVN: r237864

re PR fortran/71686 (ICE on broken character continuation)

2016-06-29  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

PR fortran/71686
* gfortran.dg/unexpected_eof_2.f90: New test.
* gfortran.dg/unexpected_eof_3.f90: New test.

From-SVN: r237861

re PR fortran/71686 (ICE on broken character continuation)

2016-06-29  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

PR fortran/71686
* scanner.c (gfc_next_char_literal): Only decrement nextc if it
is not NULL.

From-SVN: r237860

Add qdf24xx base tuning support.

gcc/
* config/aarch64/aarch64-cores.def (qdf24xx): Use qdf24xx tuning.
* config/aarch64/aarch64.c (qdf24xx_addrcost_table,
qdf24xx_regmove_cost, qdf24xx_tunings): New.
* config/arm/aarch64-cost-tables.h (qdf24xx_extra_costs): New.
* config/arm/arm-cores.def (qdf24xx): Use qdf24xx tuning.
* config/arm/arm.c (arm_qdf24xx_tune): New.

gcc/testsuite/
* gcc.dg/asr_div1.c: Add aarch64 specific dg-options.

From-SVN: r237857

openmp.c (match_oacc_clause_gang): Rename to ...

gcc/fortran/
* openmp.c (match_oacc_clause_gang): Rename to ...
(match_oacc_clause_gwv): this.  Add support for OpenACC worker and
vector clauses.
(gfc_match_omp_clauses): Use match_oacc_clause_gwv for
OMP_CLAUSE_{GANG,WORKER,VECTOR}.  Propagate any MATCH_ERRORs for
invalid OMP_CLAUSE_{ASYNC,WAIT,GANG,WORKER,VECTOR} clauses.
(gfc_match_oacc_wait): Propagate MATCH_ERROR for invalid
oacc_expr_lists.  Adjust the first and needs_space arguments to
gfc_match_omp_clauses.

gcc/testsuite/
* gfortran.dg/goacc/asyncwait-2.f95: Updated expected diagnostics.
* gfortran.dg/goacc/asyncwait-3.f95: Likewise.
* gfortran.dg/goacc/asyncwait-4.f95: Add test coverage.

From-SVN: r237854

re PR tree-optimization/15256 ([tree-ssa] Optimize manual bitfield manipilation.)

2016-06-29  Richard Biener  <rguenther@suse.de>

PR middle-end/15256
* gcc.dg/tree-ssa/forwprop-34.c: New testcase.

From-SVN: r237852

Increase loop alignment on Cortex cores to 8 and set function alignment to 16.

This makes things consistent across big.LITTLE cores, improves performance of
benchmarks with tight loops and reduces performance variations due to small
changes in code layout.

    gcc/
        * config/aarch64/aarch64.c (cortexa53_tunings):
        Increase loop alignment to 8.  Set function alignment to 16.
        (cortexa35_tunings): Likewise.
        (cortexa57_tunings): Increase loop alignment to 8.
        (cortexa72_tunings): Likewise.
        (cortexa73_tunings): Likewise.

From-SVN: r237851

re PR ada/48835 (porting GNAT to m68k-linux)

PR ada/48835
PR ada/61954
* gcc-interface/gigi.h (enum standard_datatypes): Add ADT_realloc_decl
(realloc_decl): New macro.
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Use local
variable for the entity type and translate it as void pointer if the
entity has convention C.
(gnat_to_gnu_entity) <E_Function>: If this is not a definition and the
external name matches that of malloc_decl or realloc_decl, return the
correspoding node directly.
(gnat_to_gnu_subprog_type): Likewise for parameter and return types.
* gcc-interface/trans.c (gigi): Initialize void_list_node here, not...
Initialize realloc_decl.
* gcc-interface/utils.c (install_builtin_elementary_types): ...here.
(build_void_list_node): Delete.
* gcc-interface/utils2.c (known_alignment) <CALL_EXPR>: Return the
alignment of the system allocator for malloc_decl and realloc_decl.
Do not take alignment from void pointer types either.

From-SVN: r237850

[ARM] Fix, add tests for FP16 aapcs.

testsuite/
* gcc.target/arm/aapcs/neon-vect10.c: Require
-mfloat-ab=hard.  Replace arm_neon_fp16_ok with arm_neon_fp16_hw.
* gcc.target/arm/aapcs/neon-vect9.c: Likewise.
* gcc.target/arm/aapcs/vfp18.c: Likewise.
* gcc.target/arm/aapcs/vfp19.c: Likewise.
* gcc.target/arm/aapcs/vfp20.c: Likewise.
* gcc.target/arm/aapcs/vfp21.c: Likewise.
* gcc.target/arm/fp16-aapcs-1.c: Require
-mfloat-ab=hard.  Also simplify the test.
* gcc.target/arm/fp16-aapcs-2.c: New.

From-SVN: r237849

misc.c (LANG_HOOKS_WARN_UNUSED_GLOBAL_DECL): Reorder.

* gcc-interface/misc.c (LANG_HOOKS_WARN_UNUSED_GLOBAL_DECL): Reorder.
(LANG_HOOKS_INIT_TS): Likewise.

From-SVN: r237848

[Testsuite] Selectors and options directives for ARM VFP FP16 support.

gcc/
* doc/sourcebuild.texi (Effective-Target keywords): Add entries
for arm_fp16_ok and arm_fp16_hw.
(Add Options): Add entries for arm_fp16, arm_fp16_ieee and
arm_fp16_alternative.

testsuite/
* lib/target-supports.exp (add_options_for arm_fp16): Reword
comment.
(add_options_for_arm_fp16_ieee): New.
(add_options_for_arm_fp16_alternative): New.
(effective_target_arm_fp16_ok_nocache): Add to comment.  Fix a
long-line.
(effective_target_arm_fp16_hw): New.

From-SVN: r237847

re PR tree-optimization/71655 (GCC trunk ICE on westmere target)

gcc/

PR tree-optimization/71655
* tree-vect-stmts.c (vectorizable_comparison): Swap definition
types when swapping operands.

gcc/testsuite/

PR tree-optimization/71655
* g++.dg/pr71655.C: New test.

From-SVN: r237846

Mark -fstack-protect as optimization flag.

PR middle-end/71585
* common.opt (flag_stack_protect): Mark the flag as optimization
flag.
* ipa-inline-transform.c (inline_call): Remove unnecessary call
of build_optimization_node.
* gcc.dg/pr71585.c: New test.
* gcc.dg/pr71585-2.c: New test.
* gcc.dg/pr71585-3.c: New test.

From-SVN: r237845

re PR tree-optimization/70729 (Loop marked with omp simd pragma is not vectorized)

gcc/

2016-06-29  Yuri Rumyantsev  <ysrumyan@gmail.com>

PR tree-optimization/70729
* tree-ssa-loop-im.c (ref_indep_loop_p_1): Consider memory reference as
independent in loops having positive safelen value.
* tree-vect-loop.c (vect_transform_loop): Clear-up safelen value since
it may be not valid after vectorization.

gcc/testsuite/

2016-06-29  Yuri Rumyantsev  <ysrumyan@gmail.com>

PR tree-optimization/70729
* g++.dg/vect/pr70729.cc: New test.

From-SVN: r237844

Improve diagnostic messages of "#pragma omp cancel", "#pragma omp cancellation point" parsing

gcc/c/
* c-parser.c (c_parser_pragma) <PRAGMA_OMP_CANCELLATION_POINT>:
Move pragma context checking into...
(c_parser_omp_cancellation_point): ... here, and improve
diagnostic messages.
* c-typeck.c (c_finish_omp_cancel)
(c_finish_omp_cancellation_point): Improve diagnostic messages.
gcc/cp/
* parser.c (cp_parser_pragma) <PRAGMA_OMP_CANCELLATION_POINT>:
Move pragma context checking into...
(cp_parser_omp_cancellation_point): ... here, and improve
diagnostic messages.
* semantics.c (finish_omp_cancel, finish_omp_cancellation_point):
Improve diagnostic messages.
gcc/testsuite/
* c-c++-common/gomp/cancel-1.c: Extend.

From-SVN: r237843

Rename PRAGMA_OMP_DECLARE_REDUCTION to PRAGMA_OMP_DECLARE

gcc/c-family/
* c-pragma.h (enum pragma_kind): Rename
PRAGMA_OMP_DECLARE_REDUCTION to PRAGMA_OMP_DECLARE.  Adjust all
users.

From-SVN: r237842

re PR tree-optimization/71625 (missing strlen optimization on different array initialization style)

PR tree-optimization/71625
* tree-ssa-strlen.c (get_addr_stridx): Add PTR argument.  Assume list
is sorted by ascending list->offset.  If PTR is non-NULL and there is
previous strinfo, call get_stridx_plus_constant.
(get_stridx): Pass exp as second argument to get_addr_stridx.
(addr_stridxptr): Add missing list = list->next, so that there can be
more than one entries in the list.  Bump limit from 16 to 32.  Ensure
the list is sorted by ascending list->offset.
(get_stridx_plus_constant): Adjust so that it can be also called with
ADDR_EXPR instead of SSA_NAME as PTR.
(handle_char_store): Pass NULL_TREE as second argument to
get_addr_stridx.

* gcc.dg/strlenopt-28.c: New test.

From-SVN: r237841

re PR tree-optimization/68961 (Test case gcc.target/powerpc/pr60203.c fails since r231674)

2016-06-29  Richard Biener  <rguenther@suse.de>

PR rtl-optimization/68961
* simplify-rtx.c (simplify_subreg): Handle VEC_CONCAT like CONCAT.

From-SVN: r237840

re PR middle-end/71002 (-fstrict-aliasing breaks Boost's short string optimization implementation)

2016-06-29  Richard Biener  <rguenther@suse.de>

PR middle-end/71002
* alias.c (component_uses_parent_alias_set_from): Handle
type punning through union accesses by using the union alias set.
* gimple.c (gimple_get_alias_set): Remove union type punning case.

c-family/
* c-common.c (c_common_get_alias_set): Remove union type punning case.

fortran/
* f95-lang.c (LANG_HOOKS_GET_ALIAS_SET): Remove (un-)define.
(gfc_get_alias_set): Remove.

* g++.dg/torture/pr71002.C: Adjust testcase.

From-SVN: r237839

match.pd ((T)(T2)x -> (T)x): Remove restriction on final precision not matching mode precision.

2016-07-29  Richard Biener  <rguenther@suse.de>

* match.pd ((T)(T2)x -> (T)x): Remove restriction on final
precision not matching mode precision.

From-SVN: r237838

pa.md (call_symref_64bit_post_reload): Don't call pa_output_arg_descriptor.

* config/pa/pa.md (call_symref_64bit_post_reload): Don't call
pa_output_arg_descriptor.
(call_val_symref_64bit_post_reload): Likewise.
(call_val_powf_64bit_post_reload): Likewise.
(sibcall_internal_symref_64bit): Likewise.
(sibcall_value_internal_symref_64bit): Likewise.

From-SVN: r237837

Daily bump.

From-SVN: r237836

re PR c/71685 (Segmentation fault in gcc when compiling the attached file.)

PR c/71685
* c-typeck.c (c_build_qualified_type): Don't clear
C_TYPE_INCOMPLETE_VARS for the main variant.

* gcc.dg/pr71685.c: New test.

From-SVN: r237830

PR c/71552 - Confusing error for incorrect struct initialization

gcc/c/ChangeLog:

PR c/71552
* c-typeck.c (output_init_element): Diagnose incompatible types
before non-constant initializers.

gcc/testsuite/ChangeLog:

PR c/71552
* gcc.dg/init-bad-9.c: New test.

From-SVN: r237829

abs128-1.c: Require VSX.

2016-06-28  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.target/powerpc/abs128-1.c: Require VSX.
* gcc.target/powerpc/copysign128-1.c: Likewise.
* gcc.target/powerpc/inf128-1.c: Likewise.
* gcc.target/powerpc/nan128-1.c: Likewise.

From-SVN: r237828

re PR middle-end/71626 (ICE at -O1 and above on x86_64-linux-gnu (in output_constant_pool_2, at varasm.c:3837))

PR middle-end/71626
* config/i386/i386.c (ix86_expand_vector_move): For SUBREG of
a constant, force its SUBREG_REG into memory or register instead
of whole op1.

* gcc.c-torture/execute/pr71626-1.c: New test.
* gcc.c-torture/execute/pr71626-2.c: New test.

From-SVN: r237826

re PR target/58655 ([avr] -mfract-convert-truncate not documented)

PR target/58655
* config/avr/avr.opt (-mfract-convert-truncate): Update description.
* doc/invoke.texi (AVR Options): Document it.

From-SVN: r237825

linux.h: Do not include arch/icache.h

gcc/ChangeLog
* config/tilegx/linux.h: Do not include arch/icache.h
(CLEAR_INSN_CACHE): Provide inlined definition directly.
* config/tilepro/linux.h: Do not include arch/icache.h
(CLEAR_INSN_CACHE): Provide inlined definition directly.

libgcc/ChangeLog
* config/tilepro/atomic.h: Do not include arch/spr_def.h and
asm/unistd.h.
(SPR_CMPEXCH_VALUE): Define for tilegx.
(__NR_FAST_cmpxchg): Define for tilepro.
(__NR_FAST_atomic_update): Define for tilepro.
(__NR_FAST_cmpxchg64): Define for tilepro.

From-SVN: r237824

re PR target/71656 (ICE in reload when generating code for -mcpu=power9 -mpower9-dform-vector)

PR target/71656
* gcc.target/powerpc/pr71656-2.c: Fix syntax errors.

From-SVN: r237823

This patch fixes a bug in the bswap pass.

This patch fixes a bug in the bswap pass.  In big-endian BIT_FIELD_REF uses
big-endian bit numbering so we need to adjust the bit position.
The existing version could potentially generate incorrect code however GCC
doesn't emit a BIT_FIELD_REF to access the low byte in a register, so the
symbolic number never matches in big-endian.

    gcc/
* tree-ssa-math-opts.c (find_bswap_or_nop_1): Adjust bitnumbering
for big-endian BIT_FIELD_REF.

From-SVN: r237822

rs6000.md ('type' attribute): Add htmsimple/dfp types.

* config/rs6000/rs6000.md ('type' attribute): Add htmsimple/dfp types.
('size' attribute): Add '128'.
Include power9.md.
(*mov<mode>_hardfloat32, *mov<mode>_hardfloat64, *movdi_internal32,
*movdi_internal64, *movdf_update1): Set size attribute to '64'.
(add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2,
copysign<mode>3, neg<mode>2_hw, abs<mode>2_hw, *nabs<mode>2_hw,
*fma<mode>4_hw, *fms<mode>4_hw, *nfma<mode>4_hw, *nfms<mode>4_hw,
extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw,
*xscvqp<su>wz_<mode>, *xscvqp<su>dz_<mode>, *xscv<su>dqp_<mode>,
*trunc<mode>df2_odd): Set size attribute to '128'.
(*cmp<mode>_hw): Change type to veccmp and set size attribute to '128'.
* config/rs6000/power6.md (power6-fp): Include dfp type.
* config/rs6000/power7.md (power7-fp): Likewise.
* config/rs6000/power8.md (power8-fp): Likewise.
* config/rs6000/power9.md: New file.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add power9.md.
* config/rs6000/htm.md (*tabort, *tabort<wd>c, *tabort<wd>ci,
*trechkpt, *treclaim, *tsr, *ttest): Change type attribute to
htmsimple.
* config/rs6000/dfp.md (extendsddd2, truncddsd2, extendddtd2,
trunctddd2, adddd3, addtd3, subdd3, subtd3, muldd3, multd3, divdd3,
divtd3, *cmpdd_internal1, *cmptd_internal1, floatdidd2, floatditd2,
ftruncdd2, fixdddi2, ftrunctd2, fixtddi2, dfp_ddedpd_<mode>,
dfp_denbcd_<mode>, dfp_dxex_<mode>, dfp_diex_<mode>, dfp_dscli_<mode>,
dfp_dscri_<mode>): Change type attribute to dfp.
* config/rs6000/crypto.md (crypto_vshasigma<CR_char>): Change type
attribute to vecsimple.
* config/rs6000/rs6000.c (power9_cost): Update costs, cache size
and prefetch streams.
(rs6000_option_override_internal): Remove temporary code setting
tuning to power8.  Don't set rs6000_sched_groups for power9.
(last_scheduled_insn): Change to rtx_insn *.
(divide_cnt, vec_load_pendulum): New variables.
(rs6000_adjust_cost): Add Power9 to test for store->load separation.
(rs6000_issue_rate): Set issue rate for Power9.
(is_power9_pairable_vec_type): New.
(power9_sched_reorder2): New.
(rs6000_sched_reorder2): Call new function for Power9 specific
reordering.
(insn_must_be_first_in_group): Remove Power9.
(insn_must_be_last_in_group): Likewise.
(force_new_group): Likewise.
(rs6000_sched_init): Fix initialization of last_scheduled_insn.
Initialize divide_cnt/vec_load_pendulum.
(_rs6000_sched_context, rs6000_init_sched_context,
rs6000_set_sched_context): Handle context save/restore of new
variables.

From-SVN: r237820

tree-ssa-alias.c (nonoverlapping_component_refs_of_decl_p): Properly handle DECL_BIT_FIELD_REPRESENTATIVE occuring as COMPONENT_REF operand.

2016-06-28  Richard Biener  <rguenther@suse.de>

* tree-ssa-alias.c (nonoverlapping_component_refs_of_decl_p):
Properly handle DECL_BIT_FIELD_REPRESENTATIVE occuring as
COMPONENT_REF operand.
(nonoverlapping_component_refs_p): Likewise.
* stor-layout.c (start_bitfield_representative): Mark
DECL_BIT_FIELD_REPRESENTATIVE as DECL_NONADDRESSABLE_P.

From-SVN: r237818

Makefile.in: Don't cat ../stage_current if it does not exist.

* Makefile.in: Don't cat ../stage_current if it does not exist.
c/
* Make-lang.in: Don't cat ../stage_current if it does not exist.
cp/
* Make-lang.in: Don't cat ../stage_current if it does not exist.
lto/
* Make-lang.in: Don't cat ../stage_current if it does not exist.

From-SVN: r237817

extend.texi (__builtin_add_overflow_p): Clarify behavior when last argument is a bit-field.

* doc/extend.texi (__builtin_add_overflow_p): Clarify behavior when
last argument is a bit-field.

From-SVN: r237816

re PR rtl-optimization/71673 (FAIL: c-c++-common/torture/builtin-arith-overflow-p-19.c -O2  (internal compiler error))

PR rtl-optimization/71673
* internal-fn.c (expand_arith_overflow_result_store): Use
OPTAB_LIB_WIDEN instead of OPTAB_DIRECT as last argument to
expand_simple_binop.

From-SVN: r237815

re PR middle-end/66867 (Suboptimal code generation for atomic_compare_exchange)

PR middle-end/66867
* builtins.c (expand_ifn_atomic_compare_exchange_into_call,
expand_ifn_atomic_compare_exchange): New functions.
* internal-fn.c (expand_ATOMIC_COMPARE_EXCHANGE): New function.
* tree.h (build_call_expr_internal_loc): Rename to ...
(build_call_expr_internal_loc_array): ... this.  Fix up type of
last argument.
* internal-fn.def (ATOMIC_COMPARE_EXCHANGE): New internal fn.
* predict.c (expr_expected_value_1): Handle IMAGPART_EXPR of
ATOMIC_COMPARE_EXCHANGE result.
* builtins.h (expand_ifn_atomic_compare_exchange): New prototype.
* gimple-fold.h (optimize_atomic_compare_exchange_p,
fold_builtin_atomic_compare_exchange): New prototypes.
* gimple-fold.c (optimize_atomic_compare_exchange_p,
fold_builtin_atomic_compare_exchange): New functions..
* tree-ssa.c (execute_update_addresses_taken): If
optimize_atomic_compare_exchange_p, ignore &var in 2nd argument
of call when finding addressable vars, and if such var becomes
non-addressable, call fold_builtin_atomic_compare_exchange.

From-SVN: r237814

rs6000: Fix split of ashdi3_extswsli_dot for memory (PR71670)

The splitter for ashdi3_extswsli_dot for cr0 with memory uses emit_insn
gen_ashdi3_extswsli_dot, which does not work because that emits a scratch,
while the splitter runs after reload so there should be a real register
instead.  We can laboriously fix that up, or emit using
gen_ashdi3_extswsli_dot2 instead.  This patch does the latter.

PR target/71670
* config/rs6000/rs6000.md (ashdi3_extswsli_dot): Use
gen_ashdi3_extswsli_dot2 instead of gen_ashdi3_extswsli_dot.

gcc/testsuite/
PR target/71670
* gcc.target/powerpc/pr71670.c: New testcase.

From-SVN: r237813

rs6000.md ('type' attribute): Add veclogical,veccmpfx,vecexts,vecmove insn types.

* config/rs6000/rs6000.md ('type' attribute): Add
veclogical,veccmpfx,vecexts,vecmove insn types.
(*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr,
copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal,
p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple.
(*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw,
*nabs<mode>2_hw): Change type to vecmove.
(*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal,
*boolcc<mode>3_internal, *eqv<mode>3_internal,
*one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal,
*ieee_128bit_vsx_abs<mode>2_internal,
*ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2,
*ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit,
*ieee128_mtvsrd_32bit): Change type to veclogical.
(mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
*movdi_internal32, *movdi_internal64): Update insn types.
* config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
vsx_extract_<mode>): Change type to veclogical.
(*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove.
(vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>,
*vsx_sign_extend_si_v2di): Change type to vecexts.
* config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change
type to veclogical.
(*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>,
*altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p,
*altivec_vcmpgtu<VI_char>_p): Change type to veccmpfx.
(*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove.
* config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr,
negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple.
* config/rs6000/40x.md (ppc405-float): Add fpsimple.
* config/rs6000/440.md (ppc440-fp): Add fpsimple.
* config/rs6000/476.md (ppc476-fp): Add fpsimple.
* config/rs6000/601.md (ppc601-fp): Add fpsimple.
* config/rs6000/603.md (ppc603-fp): Add fpsimple.
* config/rs6000/6xx.md (ppc604-fp): Add fpsimple.
* config/rs6000/7xx.md (ppc750-fp): Add fpsimple.
(ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx.
* config/rs6000/7450.md (ppc7450-fp): Add fpsimple.
(ppc7450-vecsimple): Add veclogical, vecmove.
(ppc7450-veccmp): Add veccmpfx.
* config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical,
vecmove.
(ppc8540_vector_compare): Add veccmpfx.
* config/rs6000/a2.md (ppca2-fp): Add fpsimple.
* config/rs6000/cell.md (cell-fp): Add fpsimple.
(cell-vecsimple): Add veclogical, vecmove.
(cell-veccmp): Add veccmpfx.
* config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple.
* config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove,
veccmpfx.
* config/rs6000/mpc.md (mpccore-fp): Add fpsimple.
 * config/rs6000/power4.md (power4-fp): Add fpsimple.
(power4-vecsimple): Add veclogical, vecmove.
(power4-veccmp): Add veccmpfx.
* config/rs6000/power5.md (power5-fp): Add fpsimple.
* config/rs6000/power6.md (power6-fp): Add fpsimple.
(power6-vecsimple): Add veclogical, vecmove.
(power6-veccmp): Add veccmpfx.
* config/rs6000/power7.md (power7-fp): Add fpsimple.
(power7-vecsimple): Add veclogical, vecmove, veccmpfx.
* config/rs6000/power8.md (power8-fp): Add fpsimple.
(power8-vecsimple): Add veclogical, vecmove, veccmpfx.
* config/rs6000/rs64.md (rs64a-fp): Add fpsimple.
* config/rs6000/titan.md (titan_fp): Add fpsimple.
* config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add
fpsimple.
* config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE.

From-SVN: r237812

re PR target/71656 (ICE in reload when generating code for -mcpu=power9 -mpower9-dform-vector)

gcc/
PR target/71656
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
OPTION_MASK_P9_DFORM_VECTOR.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
disable -mpower9-dform-vector when using reload.
(quad_address_p): Remove 'gpr_p' argument and all associated code.
New 'strict' argument.  Update all callers.  Add strict addressing
support.
(rs6000_legitimate_offset_address_p): Remove call to
virtual_stack_registers_memory_p.
(rs6000_legitimize_reload_address): Add quad address support.
(rs6000_legitimate_address_p): Move call to quad_address_p above
call to virtual_stack_registers_memory_p.  Adjust quad_address_p args
to account for new strict usage.
(rs6000_output_move_128bit): Adjust quad_address_p args to account
for new strict usage.
* config/rs6000/predicates.md (quad_memory_operand): Likewise.

gcc/testsuite/
PR target/71656
* gcc.target/powerpc/pr71656-1.c: New test.
* gcc.target/powerpc/pr71656-2.c: New test.

From-SVN: r237811

Daily bump.

From-SVN: r237810

vsx.md (UNSPEC_P9_MEMORY): New unspec to support loading and storing byte/half-word values in the vector...

[gcc]
2016-06-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config/rs6000/vsx.md (UNSPEC_P9_MEMORY): New unspec to support
loading and storing byte/half-word values in the vector registers.
(vsx_sign_extend_hi_<mode>): Enable the generator function.
(p9_lxsi<wd>zx): New insns to load zero-extended bytes and
half-words on ISA 3.0 to the vector registers.
(p9_stxsi<wd>zx): New insns to store zero-extended bytes and
half-words on ISA 3.0 from the vector registers.
* config/rs6000/rs6000.md (FP_ISA3): New iterator to optimize
converting char/half-word items to floating point on ISA 3.0.
(float<QHI:mode><FP_ISA3:mode>2): On ISA 3.0 generate the lxsihzx
and lxsibzx instructions if we are converting an 8-bit or 16-bit
item from memory to floating point.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): On ISA 3.0 generate the stxsihx
and stxsibx instructions to store floating point values converted
to 8 or 16-bit integers.
(fixuns_trunc<mode>si2): Likewise.

[gcc/testsuite]
2016-06-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

* gcc.target/powerpc/p9-fpcvt-1.c: New test to test ISA 3.0 load
byte/half-word to vector registers and store byte/half-word from
vector register instructions.
* gcc.target/powerpc/p9-fpcvt-2.c: Likewise.

From-SVN: r237806

re PR libstdc++/71640 (include/c++/7.0.0/bits/hashtable.h:293:7: error: too many template parameters in template redeclaration)

2016-06-27  François Dumont  <fdumont@gcc.gnu.org>

PR libstdc++/71640
* include/bits/hashtable.h: Remove _Unique_keya parameter in _Insert
friend declaration.

From-SVN: r237803

[ARM][testsuite] Add missing guards to fp16 AdvSIMD tests

2016-06-27  Christophe Lyon  <christophe.lyon@linaro.org>

* gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add ifdef
around fp16 code.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c:
Add arm_neon_fp16_ok effective target.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c: Likewise.

From-SVN: r237798

Daily bump.

From-SVN: r237797

i386.c (ix86_spill_class): Disable condition to always return NO_REGS.

* config/i386/i386.c (ix86_spill_class): Disable condition to
always return NO_REGS.

From-SVN: r237793

re PR rtl-optimization/70902 (GCC freezes while compiling for 'skylake-avx512' target)

PR target/70902
PR target/71453
PR target/71555
PR target/71596
PR target/71657
* config/i386/i386.c (TARGET_SPILL_CLASS): #if 0 out the definition.
(ix86_spill_class): Disable to always return NO_REGS.

From-SVN: r237792

predict-12.c: New testcase.

* gcc.dg/predict-12.c: New testcase.

* predict.c: Include gimple-pretty-print.h
(predicted_by_loop_heuristics_p): Check also
PRED_LOOP_EXIT_WITH_RECURSION
(predict_loops): Find self recursive calls and use special purpose
predictors for them; dump log about decisions.
(pass_profile::execute): Dump info about #of iterations.
* predict.def (PRED_LOOP_EXIT_WITH_RECURSION,
(PRED_LOOP_GUARD_WITH_RECURSION): New predictors.

From-SVN: r237791

pa.c (pa_output_indirect_call): Rework to combine output_asm_insn calls and shorten long lines.

* config/pa/pa.c (pa_output_indirect_call): Rework to combine
output_asm_insn calls and shorten long lines.  Output .CALL
argument descriptor using pa_output_arg_descriptor.  Add various
inline $$dyncall and other optimizations.
(pa_attr_length_indirect_call): Adjust ordering and lengths.

From-SVN: r237790

re PR fortran/71649 (Internal compiler error)

2016-06-25  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

PR fortran/71649
* module.c (create_intrinsic_function): Check for NULL values and
return after giving error.

PR fortran/71649
* gfortran.dg/pr71649.f90: New test.

From-SVN: r237789

Daily bump.

From-SVN: r237788

Add missing ChangeLog entries for r237765

From-SVN: r237784

re PR tree-optimization/71643 (internal compiler error: in redirect_eh_edge_1, at tree-eh.c:2318 after r237427)

PR tree-optimization/71643
* tree-ssa-tail-merge.c (find_clusters_1): Ignore basic blocks with
EH preds.

* tree-ssa-tail-merge.c (deps_ok_for_redirect_from_bb_to_bb): Don't
leak a bitmap if dep_bb is NULL.

* g++.dg/opt/pr71643.C: New test.

From-SVN: r237783

re PR tree-optimization/71631 (Wrong constant folding)

PR tree-optimization/71631
* tree-ssa-reassoc.c (reassociate_bb): Pass true as last argument
to rewrite_expr_tree even if negate_result, move new_lhs var
declaration and initialization earlier, for powi_result set afterwards
new_lhs to lhs.  For negate_result, use new_lhs instead of tmp
if new_lhs != lhs, and don't shadow gsi var.

* gcc.c-torture/execute/pr71631.c: New test.

From-SVN: r237782

predict.c (predict_paths_leading_to, [...]): Add in_loop parameter.

* predict.c (predict_paths_leading_to, predict_paths_leading_to_edge):
Add in_loop parameter.
(predict_loops): Add loop guard heuristics.
* predict.def (PRED_LOOP_GUARD): New heuristics.

* gcc.dg/predict-11.c: New testcase.
* gfortran.dg/predict-2.f90: New testcase.

From-SVN: r237781

predict.c: Include ipa-utils.h

* predict.c: Include ipa-utils.h
(tree_bb_level_prediction): Predict recursive calls.
(tree_estimate_probability_bb): Skip inexpensive calls for call
predictor.
* predict.def (PRED_RECURSIVE_CALL): New.

* gcc.dg/predict-10.c: New test.

From-SVN: r237780

Daily bump.

From-SVN: r237779

P0145R2: Refining Expression Order for C++ (complex LHS of =).

gcc/c-common/
* c-common.c (verify_tree) [COMPOUND_EXPR]: Fix handling on LHS of
MODIFY_EXPR.
gcc/cp/
* typeck.c (cp_build_modify_expr): Leave COMPOUND_EXPR on LHS.

From-SVN: r237775

rs6000-builtin.def (BU_FLOAT128_2): New #define.

[gcc]

2016-06-24  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/rs6000-builtin.def (BU_FLOAT128_2): New #define.
(BU_FLOAT128_1): Likewise.
(FABSQ): Likewise.
(COPYSIGNQ): Likewise.
(RS6000_BUILTIN_NANQ): Likewise.
(RS6000_BUILTIN_NANSQ): Likewise.
(RS6000_BUILTIN_INFQ): Likewise.
(RS6000_BUILTIN_HUGE_VALQ): Likewise.
* config/rs6000/rs6000.c (rs6000_fold_builtin): New prototype.
(TARGET_FOLD_BUILTIN): New #define.
(rs6000_builtin_mask_calculate): Add TARGET_FLOAT128 entry.
(rs6000_invalid_builtin): Add handling for RS6000_BTM_FLOAT128.
(rs6000_fold_builtin): New target hook implementation, handling
folding of 128-bit NaNs and infinities.
(rs6000_init_builtins): Initialize const_str_type_node; ensure all
entries are filled in to avoid problems during bootstrap
self-test; define builtins for 128-bit NaNs and infinities.
(rs6000_opt_mask): Add entry for float128.
* config/rs6000/rs6000.h (RS6000_BTM_FLOAT128): New #define.
(RS6000_BTM_COMMON): Include RS6000_BTM_FLOAT128.
(rs6000_builtin_type_index): Add RS6000_BTI_const_str.
(const_str_type_node): New #define.
* config/rs6000/rs6000.md (copysign<mode>3 for IEEE128): Convert
to a define_expand that dispatches to either copysign<mode>3_soft
or copysign<mode>3_hard.
(copysign<mode>3_hard): Rename from copysign<mode>3.
(copysign<mode>3_soft): New define_insn.
* doc/extend.texi: Document new builtins.

[gcc/testsuite]

2016-06-24  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.target/powerpc/abs128-1.c: New.
* gcc.target/powerpc/copysign128-1.c: New.
* gcc.target/powerpc/inf128-1.c: New.
* gcc.target/powerpc/nan128-1.c: New.

From-SVN: r237774

Fix get_target_expr for bit-field expressions.

* tree.c (get_target_expr_sfinae): Handle bit-fields.
(build_target_expr): Call mark_rvalue_use.

From-SVN: r237773

cfgloop.c (flow_loop_dump): Cast nit to uint64_t and print it using PRIu64 instead of lu.

* cfgloop.c (flow_loop_dump): Cast nit to uint64_t and print it using
PRIu64 instead of lu.

From-SVN: r237772

re PR debug/71642 (ICE:  in gen_type_die_with_usage, at dwarf2out.c:22729)

PR debug/71642
* tree-inline.c (remap_decl): When fixing up DECL_ORIGINAL_TYPE, just
copy the type name.

From-SVN: r237771

re PR tree-optimization/71647 (aligned(x:32) in #pragma omp simd does not work)

PR tree-optimization/71647
* omp-low.c (lower_rec_input_clauses): Convert
omp_clause_aligned_alignment (c) to size_type_node for the
last argument of __builtin_assume_aligned.

* gcc.target/i386/pr71647.c: New test.

From-SVN: r237769

Call tls_get_addr via GOT for GNU TLS if possible

There are extensions to x86-64 psABI:

https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI

and i386 psABI:

https://groups.google.com/forum/#!topic/ia32-abi/awsRSvJOJfs

to call tls_get_addr via GOT.  X86 assembler and linker in binutils 2.27
implemented

call *__tls_get_addr@GOTPCREL(%rip)

in 64-bit and

call *___tls_get_addr@GOT(%reg)

in 32-bit to access global and local thread loal variables in shared
library.  We check if 32-bit x86 assembler and linker work with

call *___tls_get_addr@GOT(%reg)

as 32-bit and 64-bit assembler and linker are enabled togther.

In 32-bit, since any integer register except EAX, which is used to pass
parameter to ___tls_get_addr, and ESP, can be used as GOT base, a new
register class, TLS_GOTBASE_REGS, along with a new constraint, Yb, are
added.  They are used to improve register allocation for 32-bit dynamic
TLS patterns.

gcc/

* configure.ac (calling ___tls_get_addr via GOT): New
assembler/linker check.
(HAVE_AS_IX86_TLS_GET_ADDR_GOT): New.  Defined to 1 if 32-bit
assembler and linker supports calling ___tls_get_addr via GOT.
Otherise, defined to 0.
* config.in: Regenerated.
* configure: Likewise.
* config/i386/constraints.md (Yb): New constraint.
* config/i386/i386.h (reg_class): Add TLS_GOTBASE_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
* config/i386/i386.md (*tls_global_dynamic_32_gnu): Replace
the b constraint with the Yb constraint.  Call ___tls_get_addr
via GOT for GNU TLS with -fno-plt if HAVE_AS_IX86_TLS_GET_ADDR_GOT
is 1.
(*tls_local_dynamic_base_32_gnu): Likewise.
(*tls_global_dynamic_64_<mode>): Call _tls_get_addr via GOT for
GNU TLS with -fno-plt if HAVE_AS_IX86_TLS_GET_ADDR_GOT is 1.
(*tls_local_dynamic_base_64_<mode>): Likewise.

gcc/testsuite/

* gcc.target/i386/noplt-gd-1.c: New test.
* gcc.target/i386/noplt-gd-2.c: Likewise.
* gcc.target/i386/noplt-gd-3.c: Likewise.
* gcc.target/i386/noplt-ld-1.c: Likewise.
* gcc.target/i386/noplt-ld-2.c: Likewise.
* gcc.target/i386/noplt-ld-3.c: Likewise.
* lib/target-supports.exp
(check_effective_target_tls_get_addr_via_got): New.

From-SVN: r237765

* gcc.dg/vect/vect-bool-cmp.c: Revert unwanted change.

From-SVN: r237764

Dump profile-based number of iterations

* analyze_brprob.py: Parse and display average number
of loop iterations.
* cfgloop.c (flow_loop_dump): Dump average number of loop iterations.
* cfgloop.h: Change 'struct loop' to 'const struct loop' for a
few functions.
* cfgloopanal.c (expected_loop_iterations_unbounded): Set a new
argument to true if the expected number of iterations is
loop-based.

From-SVN: r237762

vect-nb-iter-ub-1.c: Remove default vector testsuite compile flags.

2016-06-24  Uros Bizjak  <ubizjak@gmail.com>

* gcc.dg/vect/vect-nb-iter-ub-1.c: Remove default vector
testsuite compile flags.
* gcc.dg/vect/vect-nb-iter-ub-2.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-3.c: Ditto.

2016-06-24  Uros Bizjak  <ubizjak@gmail.com>

* g++dg/vect/pr36684.cc: Add dg-do compile.
* gcc.dg/vect/O3-pr70130.c: Remove dg-do run.
* gcc.dg/vect/pr70021.c: Ditto.
* gcc.dg/vect/pr70138-1.c: Ditto.
* gcc.dg/vect/pr70138-2.c: Ditto.
* gcc.dg/vect/pr70354-1.c: Ditto.
* gcc.dg/vect/pr70354-2.c: Ditto.
* gcc.dg/vect/pr71259.c: Ditto.
* gcc.dg/vect/pr71416-1.c: Ditto.
* gcc.dg/vect/slp-43.c: Ditto.
* gcc.dg/vect/slp-45.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-1.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-2.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-3.c: Ditto.
* gfortran.dg/vect/pr69980.f90: Ditto.

2016-06-24  Uros Bizjak  <ubizjak@gmail.com>

* gcc.dg/vect/O3-pr70130.c: Include tree-vect.h and call check_vect.
* gcc.dg/vect/bb-slp-30.c: Ditto.
* gcc.dg/vect/costmodel/i386/costmodel-vect-33.c: Ditto.
* gcc.dg/vect/fast-math-bb-slp-call-3.c: Ditto.
* gcc.dg/vect/pr45902.c: Ditto.
* gcc.dg/vect/pr48172.c: Ditto.
* gcc.dg/vect/pr48377.c: Ditto.
* gcc.dg/vect/pr49038.c: Ditto.
* gcc.dg/vect/pr49771.c: Ditto.
* gcc.dg/vect/pr52091.c: Ditto.
* gcc.dg/vect/pr53185-2.c: Ditto.
* gcc.dg/vect/pr56826.c: Ditto.
* gcc.dg/vect/pr60276.c: Ditto.
* gcc.dg/vect/pr62021.c: Ditto.
* gcc.dg/vect/pr63530.c: Ditto.
* gcc.dg/vect/pr65518.c: Ditto.
* gcc.dg/vect/pr65947-1.c: Ditto.
* gcc.dg/vect/pr65947-10.c: Ditto.
* gcc.dg/vect/pr65947-11.c: Ditto.
* gcc.dg/vect/pr65947-12.c: Ditto.
* gcc.dg/vect/pr65947-13.c: Ditto.
* gcc.dg/vect/pr65947-2.c: Ditto.
* gcc.dg/vect/pr65947-3.c: Ditto.
* gcc.dg/vect/pr65947-4.c: Ditto.
* gcc.dg/vect/pr65947-5.c: Ditto.
* gcc.dg/vect/pr65947-6.c: Ditto.
* gcc.dg/vect/pr65947-7.c: Ditto.
* gcc.dg/vect/pr65947-8.c: Ditto.
* gcc.dg/vect/pr65947-9.c: Ditto.
* gcc.dg/vect/pr71416-1.c: Ditto.
* gcc.dg/vect/pr71439.c: Ditto.
* gcc.dg/vect/slp-widen-mult-half.c: Ditto.
* gcc.dg/vect/vect-bswap16.c: Ditto.
* gcc.dg/vect/vect-bswap32.c: Ditto.
* gcc.dg/vect/vect-bswap64.c: Ditto.
* gcc.dg/vect/vect-live-1.c: Ditto.
* gcc.dg/vect/vect-live-2.c: Ditto.
* gcc.dg/vect/vect-live-3.c: Ditto.
* gcc.dg/vect/vect-live-4.c: Ditto.
* gcc.dg/vect/vect-live-5.c: Ditto.
* gcc.dg/vect/vect-live-slp-1.c: Ditto.
* gcc.dg/vect/vect-live-slp-2.c: Ditto.
* gcc.dg/vect/vect-live-slp-3.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-1.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-2.c: Ditto.
* gcc.dg/vect/vect-nb-iter-ub-3.c: Ditto.
* gcc.dg/vect/vect-neg-store-1.c: Ditto.
* gcc.dg/vect/vect-neg-store-2.c: Ditto.
* gcc.dg/vect/vect-outer-pr69720.c: Ditto.
* gcc.dg/vect/vect-reduc-mul_1.c: Ditto.
* gcc.dg/vect/vect-reduc-mul_2.c: Ditto.
* gcc.dg/vect/vect-reduc-or_1.c: Ditto.
* gcc.dg/vect/vect-reduc-or_2.c: Ditto.
* gcc.dg/vect/vect-widen-mult-const-s16.c: Ditto.
* gcc.dg/vect/vect-widen-mult-const-u16.c: Ditto.
* gcc.dg/vect/vect-widen-mult-half-u8.c: Ditto.
* gcc.dg/vect/vect-widen-mult-half.c: Ditto.

From-SVN: r237761

float128-cmp-invalid.c (main): Use __builtin_nanq.

* gcc.dg/torture/float128-cmp-invalid.c (main): Use __builtin_nanq.

From-SVN: r237760

tree-vect.h (check_vect): Handle __SSE4_2__.

* gcc.dg/vect/tree-vect.h (check_vect): Handle __SSE4_2__.

From-SVN: r237759

configure.ac (HAVE_AS_GOTOF_IN_DATA): Use $as_ix86_gas_32_opt to assemble for 32bit target.

* configure.ac (HAVE_AS_GOTOF_IN_DATA): Use $as_ix86_gas_32_opt to
assemble for 32bit target.
(HAVE_AS_IX86_TLSGDPLT): Use $as_ix86_gas_32_opt to assemble
and $ld_ix86_gld_32_opt to link for 32bit target.
(HAVE_AS_IX86_TLSLDMPLT): Ditto.
* configure: Regenerate.

From-SVN: r237758

[ARM][1/4] Replace uses of int_log2 by exact_log2

* config/arm/arm.c (int_log2): Delete definition and prototype.
(shift_op): Use exact_log2 instead of int_log2.
(vfp3_const_double_for_fract_bits): Likewise.

From-SVN: r237757

Enable non-PIC noplt tests on 32-bit x86 target

Since non-PIC noplt works on 32-bit x86 target now with assembler/linker
support, enable non-PIC noplt tests on 32-bit x86 target.  main in
noplt-2.c and noplt-4.c are renamed to bar to avoid stack re-alignment
in main for 32-bit target, which disables tailcall optimization.

* gcc.target/i386/noplt-1.c: Don't disable for ia32.  Scan for
ia32 if R_386_GOT32X relocation is supported.
* gcc.target/i386/noplt-3.c: Likewise.
* gcc.target/i386/noplt-2.c: Likewise.
(main): Renamed to ...
(bar): This.
* gcc.target/i386/noplt-4.c: Likewise.
(main): Renamed to ...
(bar): This.
* gcc.target/i386/pr67400-3.c: Don't disable for ia32.
* gcc.target/i386/pr67400-5.c: Likewise.

From-SVN: r237756