Kenneth Graunke [Wed, 20 Jan 2016 00:46:03 +0000 (16:46 -0800)]
nir/spirv/glsl450: Implement Frexp.
Kenneth Graunke [Tue, 19 Jan 2016 23:56:50 +0000 (15:56 -0800)]
nir/spirv/glsl450: Blindly implement Atan2.
This is untested and probably broken.
We already passed the atan2 CTS tests before implementing this opcode.
Presumably, glslang or something was giving us a plain Atan opcode
instead of Atan2. I don't know why.
Kenneth Graunke [Tue, 19 Jan 2016 22:30:02 +0000 (14:30 -0800)]
nir/spirv/glsl450: Implement Atan.
Kenneth Graunke [Tue, 19 Jan 2016 20:15:36 +0000 (12:15 -0800)]
nir/spirv/glsl450: Implement Asin and Acos.
Jason Ekstrand [Tue, 19 Jan 2016 20:02:53 +0000 (12:02 -0800)]
anv/pipeline: Fix point size
Jason Ekstrand [Tue, 19 Jan 2016 01:45:12 +0000 (17:45 -0800)]
getX/state: Set LOD pre-clamp to OpenGL mode
This gets us another couple hundred sampler tests
Jason Ekstrand [Tue, 5 Jan 2016 21:53:05 +0000 (13:53 -0800)]
isl/device: Add a flag for bit 6 swizzling
Jason Ekstrand [Mon, 18 Jan 2016 23:42:41 +0000 (15:42 -0800)]
anv/gem: Add a helper for getting bit6 swizzling information
Jason Ekstrand [Tue, 19 Jan 2016 00:01:00 +0000 (16:01 -0800)]
nir/spirv: Patch through image qualifiers
Jason Ekstrand [Tue, 5 Jan 2016 22:03:58 +0000 (14:03 -0800)]
nir/spirv: Implement ImageQuerySize for storage iamges
SPIR-V only has one ImageQuerySize opcode that has to work for both
textures and storage images. Therefore, we have to special-case that one a
bit and look at the type of the incoming image handle.
Jason Ekstrand [Mon, 18 Jan 2016 23:00:01 +0000 (15:00 -0800)]
nir/spirv: Insert movs around image intrinsics
Image intrinsics always take a vec4 coordinate and always return a vec4.
This simplifies the intrinsics a but but also means that they don't
actually match the incomming SPIR-V. In order to compensate for this, we
add swizzling movs for both source and destination to get the right number
of components.
Jason Ekstrand [Mon, 18 Jan 2016 22:07:46 +0000 (14:07 -0800)]
anv/meta: Improve meta clear cleanup a bit
Jason Ekstrand [Mon, 18 Jan 2016 22:04:13 +0000 (14:04 -0800)]
anv: Misc allocation scope fixes
Jason Ekstrand [Mon, 18 Jan 2016 22:03:20 +0000 (14:03 -0800)]
anv/meta: Add a meta allocator that uses SCOPE_DEVICE
The Vulkan spec requires all allocations that happen for device creation to
happen with SCOPE_DEVICE. Since meta calls into other things that allocate
memory, the easiest way to do this is with an allocator.
Jason Ekstrand [Mon, 18 Jan 2016 21:05:02 +0000 (13:05 -0800)]
anv/meta: Initialize a handle to null
Jason Ekstrand [Mon, 18 Jan 2016 20:16:31 +0000 (12:16 -0800)]
gen8: Fix border color
The border color packet is specified as a 64-byte aligned address relative
to dynamic state base address. The way the packing functions are currently
set up, we need to provide it with (offset >> 6) because it just shoves the
bits in where the PRM says they go and isn't really aware that it's an
address.
Jason Ekstrand [Mon, 18 Jan 2016 19:35:04 +0000 (11:35 -0800)]
genX/pack: Add a __gen_fixed helper and use it for TextureLODBias
The __gen_fixed helper properly clamps the value and also handles negative
values correctly. Eventually, we need to make the scripts generate this
and use it for more things.
Jason Ekstrand [Mon, 18 Jan 2016 18:36:53 +0000 (10:36 -0800)]
anv/pack: Make TextureLODBias a proper 4.8 float
XXX: We need to update the generators so this doesn't get stompped.
Jason Ekstrand [Mon, 18 Jan 2016 18:10:47 +0000 (10:10 -0800)]
nir/spirv: Handle if's where the merge is also a break or continue
Jason Ekstrand [Mon, 18 Jan 2016 17:33:56 +0000 (09:33 -0800)]
nir/spirv: Hanle continues that use SSA values from the loop body
Instead of emitting the continue before the loop body we emit it
afterwards. Then, once we've finished with the entire function, we run
nir_repair_ssa to add whatever phi nodes are needed.
Jason Ekstrand [Mon, 18 Jan 2016 17:24:07 +0000 (09:24 -0800)]
nir/lower_returns: Repair SSA after doing return lowering
Jason Ekstrand [Mon, 18 Jan 2016 17:19:01 +0000 (09:19 -0800)]
nir: Add a pass to repair SSA form
Jason Ekstrand [Mon, 18 Jan 2016 16:40:16 +0000 (08:40 -0800)]
nir/vars_to_ssa: Use the new nir_phi_builder helper
The efficiency should be approximately the same. We do a little more work
per phi node because we have to sort the predecessors. However, we no
longer have to walk the blocks a second time to pop things off the stack.
The bigger advantage, however, is that we can now re-use the phi placement
and per-block SSA value tracking in other passes.
Jason Ekstrand [Mon, 18 Jan 2016 16:38:57 +0000 (08:38 -0800)]
nir: Add a phi node placement helper
Right now, we have phi placement code in two places and there are other
places where it would be nice to be able to do this analysis. Instead of
repeating it all over the place, this commit adds a helper for placing all
of the needed phi nodes for a value.
Jason Ekstrand [Sun, 17 Jan 2016 05:26:10 +0000 (21:26 -0800)]
util/bitset: Allow iterating over const bitsets
Jason Ekstrand [Sat, 16 Jan 2016 00:15:50 +0000 (16:15 -0800)]
nir/lower_system_values: Lower vertexID to id+base if needed
Jason Ekstrand [Fri, 15 Jan 2016 23:59:58 +0000 (15:59 -0800)]
anv/batch_chain: Remove padding from the BO before emitting BUFFER_END
Jason Ekstrand [Fri, 15 Jan 2016 23:48:18 +0000 (15:48 -0800)]
anv/batch_chain: Don't call current_batch_bo() again
We call it once at the top of the function and then hold on to the pointer.
It shouldn't have changed, so there's no reason to query for it again.
Jason Ekstrand [Fri, 15 Jan 2016 19:10:58 +0000 (11:10 -0800)]
nir/spirv: Stop trusting the SPIR-V for the number of texture coordinates
Chad Versace [Fri, 15 Jan 2016 18:54:05 +0000 (10:54 -0800)]
anv: Populate SURFACE_STATE more safely
genX_image_view_init allocates up to 3 separate SURFACE_STATE structures,
and populates each from a single template. Stop mutating the template
between each final SURFACE_STATE.
Chad Versace [Fri, 15 Jan 2016 18:07:16 +0000 (10:07 -0800)]
anv/meta: Stop leaking renderpass and framebuffer
Chad Versace [Fri, 15 Jan 2016 15:43:31 +0000 (07:43 -0800)]
anv/meta: Reuse code for vkCmdClear{Color,DepthStencil}Image
The two function bodies were very similar. Move common code to
anv_cmd_clear_image().
Fixes all 'dEQP-VK.renderpass.formats.*' on Skylake.
Chad Versace [Fri, 15 Jan 2016 05:29:46 +0000 (21:29 -0800)]
anv/gen8: Fix SF_CLIP_VIEWPORT's Z elements
SF_CLIP_VIEWPORT does not clamp Z values. It only scales and shifts
them. Clamping to VkViewport::minDepth,maxDepth is instead handled by
CC_VIEWPORT.
Fixes dEQP-VK.renderpass.simple.depth on Broadwell.
Chad Versace [Fri, 15 Jan 2016 04:09:38 +0000 (20:09 -0800)]
anv/meta: Implement vkCmdClearDepthStencilImage
Chad Versace [Thu, 14 Jan 2016 02:37:27 +0000 (18:37 -0800)]
anv/meta: Implement vkCmdClearAttachments
Chad Versace [Thu, 14 Jan 2016 02:34:20 +0000 (18:34 -0800)]
anv/meta: Add VkClearRect param to emit_clear()
Prepares for vkCmdClearAttachments.
Chad Versace [Thu, 14 Jan 2016 23:18:20 +0000 (15:18 -0800)]
anv: Distinguish between subpass setup and subpass start
vkCmdBeginRenderPass, vkCmdNextSubpass, and vkBeginCommandBuffer with
VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT, all *setup* the
command buffer for recording commands for some subpass. But only the
first two, vkCmdBeginRenderPass and vkCmdNextSubpass, can *start*
a subpass.
Therefore, calling anv_cmd_buffer_begin_subpass() inside
vkCmdBeginCommandBuffer is misleading. Clarify its purpose by renaming
it to anv_cmd_buffer_set_subpass() and adding comments.
Chad Versace [Wed, 13 Jan 2016 22:47:51 +0000 (14:47 -0800)]
anv: Emit load clears at start of each subpass
This should improve cache residency for render targets.
Pre-patch, vkCmdBeginRenderPass emitted all the meta clears for
VK_ATTACHMENT_LOAD_OP_CLEAR before any subpass began. Post-patch,
vCmdBeginRenderPass and vkCmdNextSubpass emit only the clears needed for
that current subpass.
Chad Versace [Thu, 14 Jan 2016 00:29:45 +0000 (16:29 -0800)]
anv/meta: Create 8 pipelines for color clears
This prepares for moving the clear ops from the start of the render pass
into each subpass.
Pipeline N will be used to clear color attachment N of the current
subpass. Currently meta color clears still create a throwaway subpass
with exactly one attachment, so currently only pipeline 0 is used.
This is an ugly hack to workaround the compiler's current inability to
dynamically set the render target index in the render target write
message.
Chad Versace [Thu, 14 Jan 2016 02:24:18 +0000 (18:24 -0800)]
anv: Allow override of pipeline color attachment count
Add anv_graphics_pipeline_create_info::color_attachment_count. If
non-negative, then it overrides the color attachment count in the
pipeline's subpass. Useful for meta. (All the hacks for meta!)
Chad Versace [Thu, 14 Jan 2016 02:09:01 +0000 (18:09 -0800)]
anv/meta: Name the nir shaders
The names appear in debug output.
Chad Versace [Thu, 14 Jan 2016 00:03:09 +0000 (16:03 -0800)]
anv: Move MAX_* defs to top of anv_private.h
Because I need to use MAX_RTS in struct anv_meta_state.
Chad Versace [Thu, 14 Jan 2016 00:24:14 +0000 (16:24 -0800)]
anv: Define zero() macro
zero(x) memsets x to zero. Eliminates bugs due to errors in memset's
size param.
Chad Versace [Wed, 13 Jan 2016 22:09:36 +0000 (14:09 -0800)]
anv/meta: Rename emit_load_*_clear funcs
The functions will soon handle clears unrelated to
VK_ATTACHMENT_LOAD_OP_CLEAR, namely vkCmdClearAttachments. So remove
"load" from their name:
emit_load_color_clear -> emit_color_clear
emit_load_depthstencil_clear -> emit_depthstencil_clear
Chad Versace [Wed, 13 Jan 2016 19:52:23 +0000 (11:52 -0800)]
anv/meta: Use anv_cmd_state::attachments for clears
Rewrite anv_cmd_buffer_clear_attachments, which emits the top-of-pass
clears, to use the data provided in anv_cmd_state::attachments. This
prepares for deferring each attachment clear to the first subpass that
uses the attachment.
Chad Versace [Wed, 13 Jan 2016 19:28:35 +0000 (11:28 -0800)]
anv: Add anv_cmd_state::attachments
This array contains attachment state when recording a renderpass instance.
It's populated on each call to anv_cmd_buffer_set_pass.
The data is currently set but unused. We'll use it later to defer each
attachment clear to the subpass that first uses the attachment.
Jason Ekstrand [Fri, 15 Jan 2016 06:03:15 +0000 (22:03 -0800)]
i965/fs/generator: Change a comment as per jordan's suggestion
Jason Ekstrand [Fri, 15 Jan 2016 04:42:47 +0000 (20:42 -0800)]
i965/fs: Always set hannel 2 of texture headers in some stages
Jason Ekstrand [Fri, 15 Jan 2016 04:27:51 +0000 (20:27 -0800)]
i965/fs/generator: Take an actual shader stage rather than a string
Jason Ekstrand [Fri, 15 Jan 2016 02:58:25 +0000 (18:58 -0800)]
anv/apply_pipeline_layout: Stomp texture array size to 1
Jason Ekstrand [Fri, 15 Jan 2016 02:40:35 +0000 (18:40 -0800)]
nir/spirv: Fix texture return types
We were just hard-coding everything to a vec4. This meant we weren't
handling shadow samplers at all and integer things were getting the wrong
return type.
Kristian Høgsberg Kristensen [Thu, 14 Jan 2016 23:18:40 +0000 (15:18 -0800)]
vk: Fix struct field indentation
Chad Versace [Thu, 14 Jan 2016 21:18:40 +0000 (13:18 -0800)]
anv: Document anv_cmd_state::current_pipeline
It's the value of PIPELINE_SELECT.PipelineSelection.
Chad Versace [Thu, 14 Jan 2016 21:12:35 +0000 (13:12 -0800)]
anv: Make vkBeginCommandBuffer reset the command buffer
If its the command buffer's first call to vkBeginCommandBuffer, we must
*initialize* the command buffer's state. Otherwise, we must *reset* its
state. In both cases, let's use anv_ResetCommandBuffer.
From the Vulkan 1.0 spec:
If a command buffer is in the executable state and the command buffer
was allocated from a command pool with the
VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
vkBeginCommandBuffer implicitly resets the command buffer, behaving
as if vkResetCommandBuffer had been called with
VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
the command buffer in the recording state.
Chad Versace [Thu, 14 Jan 2016 20:58:46 +0000 (12:58 -0800)]
anv: Add FIXME for vkResetCommandPool
vkResetCommandPool currently destroys its command buffers. The Vulkan
1.0 spec requires that it only reset them:
Resetting a command pool recycles all of the resources from all of
the command buffers allocated from the command pool back to the
command pool. All command buffers that have been allocated from the
command pool are put in the initial state.
Chad Versace [Thu, 14 Jan 2016 03:37:40 +0000 (19:37 -0800)]
anv: Remove duplicate func prototype
anv_private.h declared anv_cmd_buffer_begin_subpass twice.
Chad Versace [Mon, 11 Jan 2016 23:05:47 +0000 (15:05 -0800)]
anv/meta: Add FINISHME for clearing multi-layer framebuffers
Jason Ekstrand [Thu, 14 Jan 2016 20:04:20 +0000 (12:04 -0800)]
i965/vec4: Use UW type for multiply into accumulator on GEN8+
BDW adds the following restriction: "When multiplying DW x DW, the dst
cannot be accumulator."
Jason Ekstrand [Thu, 14 Jan 2016 19:36:17 +0000 (11:36 -0800)]
Merge remote-tracking branch 'mesa-public/master' into vulkan
This fixes the bitfieldextract and bitfieldinsert CTS tests
Ilia Mirkin [Thu, 14 Jan 2016 18:44:54 +0000 (13:44 -0500)]
st/mesa: use surface format to generate mipmaps when available
This fixes the recently posted mipmap + texture views piglit test.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Wed, 13 Jan 2016 17:42:02 +0000 (18:42 +0100)]
radeonsi: don't miss changes to SPI_TMPRING_SIZE
I'm not sure about the consequences of this bug, but it's definitely
dangerous.
This applies to SI, CIK, VI.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Charmaine Lee [Tue, 22 Dec 2015 19:20:41 +0000 (11:20 -0800)]
svga: add DXGenMips command support
For those formats that support hw mipmap generation, use the
DXGenMips command. Otherwise fallback to the mipmap generation utility.
Tested with piglit, OpenGL apps (Heaven, Turbine, Cinebench)
v2: make sure the texture surface was created with the render target bind flag
set relocation flag to SVGA_RELOC_WRITE for the texture surface
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Charmaine Lee [Mon, 21 Dec 2015 19:07:08 +0000 (11:07 -0800)]
svga: add num-generate-mipmap HUD query
The actual increment of the num-generate-mipmap counter will be done
in a subsequent patch when hw generate mipmap is supported.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Charmaine Lee [Thu, 14 Jan 2016 17:22:17 +0000 (10:22 -0700)]
gallium/st: add pipe_context::generate_mipmap()
This patch adds a new interface to support hardware mipmap generation.
PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify
if this new interface is supported; if not supported, the state tracker will
fallback to mipmap generation by rendering/texturing.
v2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers
v3: add format to the generate_mipmap interface to allow mipmap generation
using a format other than the resource format
v4: fix return type of trace_context_generate_mipmap()
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 14 Jan 2016 17:38:17 +0000 (10:38 -0700)]
st/mesa: declare struct pipe_screen in st_cb_bufferobjects.h
To silence a compiler warning. Trivial.
Matt Turner [Wed, 13 Jan 2016 19:09:11 +0000 (11:09 -0800)]
nir: Lower bitfield_extract.
The OpenGL specifications for bitfieldExtract() says:
The result will be undefined if <offset> or <bits> is negative, or if
the sum of <offset> and <bits> is greater than the number of bits
used to store the operand.
Therefore passing bits=32, offset=0 is legal and defined in GLSL.
But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits
of the width operand, making them not able to implement the GLSL-specified
behavior directly.
This commit adds ubfe/ibfe operations from SM5 and a lowering pass for
bitfield_extract to to handle the trivial case of <bits> = 32 as
bitfieldExtract:
bits > 31 ? value : bfe(value, offset, bits)
Fixes:
ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
Matt Turner [Wed, 13 Jan 2016 19:08:37 +0000 (11:08 -0800)]
nir: Handle <bits>=32 case in bitfield_insert lowering.
The OpenGL specifications for bitfieldInsert() says:
The result will be undefined if <offset> or <bits> is negative, or if
the sum of <offset> and <bits> is greater than the number of bits
used to store the operand.
Therefore passing bits=32, offset=0 is legal and defined in GLSL.
But the earlier SM5 bfi opcode is specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low
5 bits of the width operand, making them not able to implement the
GLSL-specified behavior directly.
This commit fixes the lowering of bitfield_insert to handle the trivial
case of <bits> = 32 as
bitfieldInsert:
bits > 31 ? insert : bfi(bfm(bits, offset), insert, base)
Fixes:
ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2
ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
Jason Ekstrand [Thu, 14 Jan 2016 17:12:32 +0000 (09:12 -0800)]
nir/spirv: Add initial support for Vertex/Instance index
Jason Ekstrand [Thu, 14 Jan 2016 16:37:54 +0000 (08:37 -0800)]
vulkan.h: Pull in 1.0.1 header
Jason Ekstrand [Thu, 14 Jan 2016 16:10:07 +0000 (08:10 -0800)]
vulkan-1.0.0: Bump the version to 1.0.0
Jason Ekstrand [Thu, 14 Jan 2016 16:09:39 +0000 (08:09 -0800)]
vulkan-1.0.0: Rework memory barriers
Brian Paul [Wed, 13 Jan 2016 23:20:09 +0000 (16:20 -0700)]
st/mesa: add check for color logicop in blit_copy_pixels()
We check that a bunch of raster operations are disabled in
blit_copy_pixels(). We also need to check that color logicop is
disabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Thu, 14 Jan 2016 16:02:44 +0000 (08:02 -0800)]
vulkan-1.0.0: No-op WSI changes
Jason Ekstrand [Thu, 14 Jan 2016 16:00:18 +0000 (08:00 -0800)]
vulkan-1.0.0: Make extents unsigned
Jason Ekstrand [Thu, 14 Jan 2016 15:59:37 +0000 (07:59 -0800)]
vulkan-1.0.0: Rework blits to use four offsets
Jason Ekstrand [Thu, 14 Jan 2016 15:45:15 +0000 (07:45 -0800)]
vulkan-1.0.0: Split out command buffer inheritance info
Jason Ekstrand [Thu, 14 Jan 2016 15:43:05 +0000 (07:43 -0800)]
vulkan-1.0.0: Re-order some structs in the header
Jason Ekstrand [Thu, 14 Jan 2016 15:41:45 +0000 (07:41 -0800)]
vulkan-1.0.0: Misc. field and argument renames
Jason Ekstrand [Thu, 14 Jan 2016 15:32:16 +0000 (07:32 -0800)]
vulkan-1.0.0: Get rid of MIPMAP_MODE_BASE
Jason Ekstrand [Thu, 14 Jan 2016 15:29:58 +0000 (07:29 -0800)]
vulkan-1.0.0: Convert pPreserveAttachments to a uint32_t
Jason Ekstrand [Thu, 14 Jan 2016 14:58:11 +0000 (06:58 -0800)]
anv/device: Update features and limits
Jason Ekstrand [Thu, 14 Jan 2016 14:50:18 +0000 (06:50 -0800)]
anv/cmd_buffer: Fix setting of viewport/scissor count
Jason Ekstrand [Thu, 7 Jan 2016 03:48:57 +0000 (19:48 -0800)]
anv/state: Respect SamplerCreateInfo.anisotropyEnable
Jason Ekstrand [Thu, 7 Jan 2016 03:27:10 +0000 (19:27 -0800)]
anv/image: Fill out VkSubresourceLayout.arrayPitch
BogDan Vatra [Tue, 5 Jan 2016 19:44:16 +0000 (21:44 +0200)]
WIP: Partially upgrade to vulkan v0.221.0
TODO, make use of:
- VkPhysicalDeviceFeatures.drawIndirectFirstInstance,
- VkPhysicalDeviceFeatures.inheritedQueries
- VkPhysicalDeviceLimits.timestampComputeAndGraphics
- VkSubmitInfo.pWaitDstStageMask
- VkSubresourceLayout.arrayPitch
- VkSamplerCreateInfo.anisotropyEnable
Nicolai Hähnle [Tue, 12 Jan 2016 14:29:18 +0000 (09:29 -0500)]
gallium/radeon: do not reallocate user memory buffers
The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 14 Jan 2016 14:41:04 +0000 (09:41 -0500)]
gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFER
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 11 Jan 2016 00:54:44 +0000 (19:54 -0500)]
gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
This accomodates a streaming pattern where the discard flag is set when the
application wraps back to the beginning of the buffer.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 9 Jan 2016 23:05:58 +0000 (18:05 -0500)]
st/mesa: implement Driver.InvalidateBufferSubData
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 11 Jan 2016 22:44:45 +0000 (17:44 -0500)]
st/mesa: use pipe->invalidate_resource instead of buffer re-allocation
Drivers are expected to avoid unnecessary work when possible in this code
path.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 11 Jan 2016 22:38:08 +0000 (17:38 -0500)]
gallium: add PIPE_CAP_INVALIDATE_BUFFER
It makes sense to re-use pipe->invalidate_resource for the purpose of
glInvalidateBufferData, but this function is already implemented in vc4
where it doesn't have the expected behavior. So add a capability flag
to indicate that the driver supports the expected behavior.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 9 Jan 2016 22:53:07 +0000 (17:53 -0500)]
mesa: add Driver.InvalidateBufferSubData
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 9 Jan 2016 22:51:39 +0000 (17:51 -0500)]
mesa: fix the checks in _mesa_InvalidateBuffer(Sub)Data
Change the check to be in line with what the quoted spec fragment says.
I have sent out a piglit test for this as well.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Tue, 12 Jan 2016 17:28:11 +0000 (12:28 -0500)]
winsys/radeon: fix warnings about incompatible pointer types
Some confusion between pb_buffer and radeon_bo as well as between
radeon_drm_winsys and radeon_winsys.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Neil Roberts [Wed, 13 Jan 2016 19:28:45 +0000 (19:28 +0000)]
texobj: Check completeness with InternalFormat rather than Mesa format
The internal Mesa format used for a texture might not match the one
requested in the internalFormat when the texture was created, for
example if the driver is internally remapping RGB textures to RGBA.
Otherwise it can cause false positives for completeness if one mipmap
image is created as RGBA and the other as RGB because they would both
have an RGBA Mesa format. If we check the InternalFormat instead then
we are directly checking the API usage which I think better matches
the intention of the check.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93700
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jordan Justen [Tue, 12 Jan 2016 05:53:35 +0000 (21:53 -0800)]
nir/spirv: Add support for ArrayLength op
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 13 Jan 2016 23:09:45 +0000 (15:09 -0800)]
nir/spirv/alu: Properly implement mod/rem
Jason Ekstrand [Wed, 13 Jan 2016 23:09:00 +0000 (15:09 -0800)]
i965: Implement nir_op_irem and nir_op_srem
Ben Widawsky [Wed, 30 Dec 2015 17:47:17 +0000 (09:47 -0800)]
i965: Remove unused hw_must_use_separate_stencil
I spotted this while looking for what needs updating in future platforms.
I'm too lazy to go through the git logs, but it was probably missed by Jason
when all the brw refactoring happened.
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 14 Jan 2016 00:17:26 +0000 (16:17 -0800)]
i965: Drop extra newline from shader compile messages.
Ilia changed shader-db's run.c to not expect messages to contain a
newline in shader-db commit
51bbc8035.