Eddie Hung [Tue, 16 Apr 2019 22:01:45 +0000 (15:01 -0700)]
Port from xc7mux branch
Eddie Hung [Tue, 16 Apr 2019 20:10:35 +0000 (13:10 -0700)]
Re-enable partsel.v test
Eddie Hung [Tue, 16 Apr 2019 20:10:13 +0000 (13:10 -0700)]
abc9 to call "setundef -zero" behaving as for abc
Eddie Hung [Tue, 16 Apr 2019 04:56:45 +0000 (21:56 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Tue, 16 Apr 2019 01:39:20 +0000 (18:39 -0700)]
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Tue, 16 Apr 2019 00:52:45 +0000 (17:52 -0700)]
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Mon, 15 Apr 2019 19:22:05 +0000 (12:22 -0700)]
Merge pull request #936 from YosysHQ/README-fix-quotes
README: fix some incorrect quoting
whitequark [Mon, 15 Apr 2019 14:29:46 +0000 (14:29 +0000)]
README: fix some incorrect quoting.
Eddie Hung [Sat, 13 Apr 2019 01:22:44 +0000 (18:22 -0700)]
Forgot backslashes
Eddie Hung [Sat, 13 Apr 2019 01:21:16 +0000 (18:21 -0700)]
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
Eddie Hung [Sat, 13 Apr 2019 01:16:50 +0000 (18:16 -0700)]
abc to ignore __dummy_o__ and __const[01]__ when re-integrating
Eddie Hung [Sat, 13 Apr 2019 01:16:25 +0000 (18:16 -0700)]
Output __const0__ and __const1__ CIs
Eddie Hung [Sat, 13 Apr 2019 00:09:24 +0000 (17:09 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Sat, 13 Apr 2019 00:02:24 +0000 (17:02 -0700)]
Fix inout handling for -map option
Eddie Hung [Fri, 12 Apr 2019 23:31:12 +0000 (16:31 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Fri, 12 Apr 2019 23:30:53 +0000 (16:30 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 12 Apr 2019 23:29:14 +0000 (16:29 -0700)]
Use -map instead of -symbols for aiger
Eddie Hung [Fri, 12 Apr 2019 23:17:48 +0000 (16:17 -0700)]
ci_bits and co_bits now a list, order is important for ABC
Eddie Hung [Fri, 12 Apr 2019 23:17:12 +0000 (16:17 -0700)]
Also cope with duplicated CIs
Eddie Hung [Fri, 12 Apr 2019 21:13:11 +0000 (14:13 -0700)]
WIP
Eddie Hung [Tue, 9 Apr 2019 17:09:43 +0000 (10:09 -0700)]
Comment out
Eddie Hung [Tue, 9 Apr 2019 17:06:44 +0000 (10:06 -0700)]
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
Eddie Hung [Fri, 12 Apr 2019 19:27:07 +0000 (12:27 -0700)]
Cope with an output having same name as an input (i.e. CO)
Eddie Hung [Fri, 12 Apr 2019 19:21:48 +0000 (12:21 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 12 Apr 2019 18:52:45 +0000 (11:52 -0700)]
Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
Keith Rothman [Fri, 12 Apr 2019 16:30:49 +0000 (09:30 -0700)]
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 12 Apr 2019 12:57:36 +0000 (14:57 +0200)]
Merge pull request #933 from dh73/master
Fixing issues in CycloneV cell sim
Clifford Wolf [Fri, 12 Apr 2019 12:57:01 +0000 (14:57 +0200)]
Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
Diego [Fri, 12 Apr 2019 00:59:03 +0000 (19:59 -0500)]
Fixing issues in CycloneV cell sim
Eddie Hung [Thu, 11 Apr 2019 22:03:40 +0000 (15:03 -0700)]
Add default entry to testcase
Eddie Hung [Thu, 11 Apr 2019 19:34:51 +0000 (12:34 -0700)]
Recognise default entry in case even if all cases covered (#931)
Eddie Hung [Thu, 11 Apr 2019 01:06:33 +0000 (18:06 -0700)]
Add non-input bits driven by unrecognised cells as ci_bits
Eddie Hung [Wed, 10 Apr 2019 21:02:23 +0000 (14:02 -0700)]
parse_aiger() to rename all $lut cells after "clean"
Keith Rothman [Tue, 9 Apr 2019 18:43:19 +0000 (11:43 -0700)]
Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Keith Rothman [Tue, 9 Apr 2019 16:01:53 +0000 (09:01 -0700)]
Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Eddie Hung [Mon, 8 Apr 2019 23:46:33 +0000 (16:46 -0700)]
Fix a few typos
Eddie Hung [Mon, 8 Apr 2019 23:40:17 +0000 (16:40 -0700)]
More space fixing
Eddie Hung [Mon, 8 Apr 2019 23:37:22 +0000 (16:37 -0700)]
Fix spacing
Eddie Hung [Mon, 8 Apr 2019 23:31:59 +0000 (16:31 -0700)]
Merge branch 'master' into xaig
Clifford Wolf [Mon, 8 Apr 2019 19:14:05 +0000 (21:14 +0200)]
Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
David Shah [Sun, 7 Apr 2019 15:56:31 +0000 (16:56 +0100)]
memory_bram: Fix multiport make_transp
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 5 Apr 2019 15:31:49 +0000 (17:31 +0200)]
Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 4 Apr 2019 16:10:10 +0000 (18:10 +0200)]
Added missing argument checking to "mutate" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 3 Apr 2019 13:27:41 +0000 (06:27 -0700)]
Merge pull request #913 from smunaut/fix_proc_mux
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
Sylvain Munaut [Wed, 3 Apr 2019 12:50:12 +0000 (14:50 +0200)]
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Wed, 3 Apr 2019 08:00:18 +0000 (10:00 +0200)]
Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
Clifford Wolf [Wed, 3 Apr 2019 07:59:11 +0000 (09:59 +0200)]
Merge pull request #910 from ucb-bar/memupdates
Refine memory support to deal with general Verilog memory definitions.
David Shah [Tue, 2 Apr 2019 18:47:50 +0000 (19:47 +0100)]
memory_bram: Consider read enable for address expansion register
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Tue, 2 Apr 2019 07:16:14 +0000 (00:16 -0700)]
Merge pull request #895 from YosysHQ/pmux2shiftx
RFC: Add a pmux-to-shiftx optimisation to proc_mux
Jim Lawson [Mon, 1 Apr 2019 22:02:12 +0000 (15:02 -0700)]
Refine memory support to deal with general Verilog memory definitions.
Clifford Wolf [Fri, 29 Mar 2019 23:09:42 +0000 (00:09 +0100)]
Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
Clifford Wolf [Fri, 29 Mar 2019 15:32:44 +0000 (16:32 +0100)]
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 28 Mar 2019 08:32:05 +0000 (09:32 +0100)]
Merge pull request #901 from trcwm/libertyfixes
Libertyfixes: accept superfluous ; at end of group.
Clifford Wolf [Thu, 28 Mar 2019 08:30:48 +0000 (09:30 +0100)]
Merge pull request #903 from YosysHQ/bram_reset_transp
memory_bram: Reset make_transp when growing read ports
David Shah [Wed, 27 Mar 2019 17:19:14 +0000 (17:19 +0000)]
memory_bram: Reset make_transp when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
Niels Moseley [Wed, 27 Mar 2019 14:17:58 +0000 (15:17 +0100)]
Liberty file parser now accepts superfluous ;
Niels Moseley [Wed, 27 Mar 2019 14:16:19 +0000 (15:16 +0100)]
Liberty file parser now accepts superfluous ;
Niels Moseley [Wed, 27 Mar 2019 14:15:53 +0000 (15:15 +0100)]
Liberty file parser now accepts superfluous ;
Clifford Wolf [Wed, 27 Mar 2019 13:03:35 +0000 (14:03 +0100)]
Add "read -verific" and "read -noverific"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 27 Mar 2019 12:47:42 +0000 (13:47 +0100)]
Add "rename -output"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 27 Mar 2019 12:33:26 +0000 (13:33 +0100)]
Improve "rename" help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 26 Mar 2019 15:01:14 +0000 (16:01 +0100)]
Add "cutpoint -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 26 Mar 2019 13:51:35 +0000 (14:51 +0100)]
Add "hdlname" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 26 Mar 2019 13:17:46 +0000 (14:17 +0100)]
Fix "verific -extnets" for more complex situations
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 25 Mar 2019 18:49:00 +0000 (19:49 +0100)]
Add "cutpoint" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Mon, 25 Mar 2019 18:16:56 +0000 (11:16 -0700)]
Create one $shiftx per bit in width
Clifford Wolf [Mon, 25 Mar 2019 13:55:16 +0000 (14:55 +0100)]
Merge pull request #896 from YosysHQ/transp_fixes
memory_bram: Fix multiclock make_transp
Clifford Wolf [Mon, 25 Mar 2019 13:47:33 +0000 (14:47 +0100)]
Merge pull request #897 from trcwm/libertyfixes
Liberty parser: Accept ranges [A:B], and ignore missing ';'.
Niels Moseley [Mon, 25 Mar 2019 13:12:04 +0000 (14:12 +0100)]
spaces -> tabs
Niels Moseley [Mon, 25 Mar 2019 11:15:10 +0000 (12:15 +0100)]
EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)
Niels Moseley [Sun, 24 Mar 2019 21:54:18 +0000 (22:54 +0100)]
Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
David Shah [Sun, 24 Mar 2019 16:21:36 +0000 (16:21 +0000)]
memory_bram: Fix multiclock make_transp
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Sat, 23 Mar 2019 23:45:36 +0000 (16:45 -0700)]
Add a pmux-to-shiftx optimisation to proc_mux
Clifford Wolf [Sat, 23 Mar 2019 19:20:32 +0000 (20:20 +0100)]
Add "mutate -none -mode", "mutate -mode none"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 23 Mar 2019 16:53:09 +0000 (17:53 +0100)]
Add "mutate -s <filename>"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 23 Mar 2019 15:02:01 +0000 (16:02 +0100)]
Merge pull request #893 from YosysHQ/clifford/btormeminit
Memory init support in write_btor
Clifford Wolf [Sat, 23 Mar 2019 13:40:01 +0000 (14:40 +0100)]
Add support for memory initialization to write_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 23 Mar 2019 13:39:42 +0000 (14:39 +0100)]
Fix BTOR output tags syntax in writye_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 23 Mar 2019 13:38:48 +0000 (14:38 +0100)]
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Mar 2019 17:03:06 +0000 (18:03 +0100)]
Merge pull request #889 from YosysHQ/clifford/fix888
Fix mem2reg handling of memories with upto data ports
Clifford Wolf [Fri, 22 Mar 2019 17:02:29 +0000 (18:02 +0100)]
Merge pull request #890 from YosysHQ/clifford/fix887
Trim init attributes when resizing FFs in "wreduce"
David Shah [Fri, 22 Mar 2019 14:28:29 +0000 (14:28 +0000)]
Merge pull request #891 from YosysHQ/xilinx_keep
xilinx: Add keep attribute where appropriate
David Shah [Fri, 22 Mar 2019 13:57:17 +0000 (13:57 +0000)]
xilinx: Add keep attribute where appropriate
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 22 Mar 2019 10:42:19 +0000 (11:42 +0100)]
Trim init attributes when resizing FFs in "wreduce", fixes #887
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Mar 2019 21:19:17 +0000 (22:19 +0100)]
Fix mem2reg handling of memories with upto data ports, fixes #888
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Mar 2019 21:20:16 +0000 (22:20 +0100)]
Improve "read_verilog -dump_vlog[12]" handling of upto ranges
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Mar 2019 19:52:29 +0000 (20:52 +0100)]
Improve read_verilog debug output capabilities
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 19 Mar 2019 19:31:53 +0000 (20:31 +0100)]
Merge pull request #885 from YosysHQ/clifford/fix873
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Clifford Wolf [Tue, 19 Mar 2019 19:29:54 +0000 (20:29 +0100)]
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Tue, 19 Mar 2019 16:41:40 +0000 (09:41 -0700)]
Merge pull request #808 from eddiehung/read_aiger
Add new read_aiger frontend
Eddie Hung [Tue, 19 Mar 2019 15:52:31 +0000 (08:52 -0700)]
Merge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung [Tue, 19 Mar 2019 15:52:06 +0000 (08:52 -0700)]
Add author name
Clifford Wolf [Tue, 19 Mar 2019 13:08:57 +0000 (14:08 +0100)]
Merge pull request #884 from zachjs/master
fix local name resolution in prefix constructs
Zachary Snow [Tue, 19 Mar 2019 00:34:21 +0000 (20:34 -0400)]
fix local name resolution in prefix constructs
Clifford Wolf [Sun, 17 Mar 2019 11:53:47 +0000 (12:53 +0100)]
Update issue template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 17 Mar 2019 11:44:23 +0000 (12:44 +0100)]
Update issue template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 16 Mar 2019 13:19:02 +0000 (14:19 +0100)]
Merge pull request #877 from FelixVi/master
Add note about test requirements in README
Felix Vietmeyer [Sat, 16 Mar 2019 12:20:59 +0000 (06:20 -0600)]
Add note about test requirements in README
Clifford Wolf [Fri, 15 Mar 2019 23:55:46 +0000 (00:55 +0100)]
Improve mix of src/wire/wirebit coverage in "mutate -list"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 15 Mar 2019 23:17:15 +0000 (00:17 +0100)]
Merge pull request #876 from YosysHQ/clifford/fmcombine
Add fmcombine pass