Clifford Wolf [Sun, 13 Jan 2019 16:15:40 +0000 (17:15 +0100)]
Fix pmgen "reject" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 16:03:58 +0000 (17:03 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 11:53:13 +0000 (12:53 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 09:57:11 +0000 (10:57 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 11 Jan 2019 13:02:16 +0000 (14:02 +0100)]
Add mockup .pmg (pattern matcher generator) file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 16:00:58 +0000 (17:00 +0100)]
Add optional nullstr argument to log_id()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 Jan 2019 09:55:27 +0000 (10:55 +0100)]
Fix handling of $shiftx in Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 Jan 2019 08:52:01 +0000 (09:52 +0100)]
Merge pull request #788 from whitequark/master
Document $tribuf and some gates
Clifford Wolf [Tue, 15 Jan 2019 08:50:58 +0000 (09:50 +0100)]
Merge pull request #787 from whitequark/flowmap_relax
flowmap: implement depth relaxation
whitequark [Mon, 14 Jan 2019 16:17:25 +0000 (16:17 +0000)]
manual: document some gates.
whitequark [Mon, 14 Jan 2019 16:08:58 +0000 (16:08 +0000)]
manual: explain $tribuf cell.
Clifford Wolf [Tue, 8 Jan 2019 19:16:36 +0000 (20:16 +0100)]
Improve igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Tue, 8 Jan 2019 02:05:06 +0000 (02:05 +0000)]
flowmap: clean up terminology.
* "map": group gates into LUTs;
* "pack": replace gates with LUTs.
This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.
Also clean up some other log messages while we're at it.
whitequark [Fri, 4 Jan 2019 13:06:51 +0000 (13:06 +0000)]
flowmap: implement depth relaxation.
Clifford Wolf [Mon, 7 Jan 2019 09:07:28 +0000 (10:07 +0100)]
Fix typo in manual
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 7 Jan 2019 09:01:11 +0000 (10:01 +0100)]
Bugfix in $memrd sharing
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 7 Jan 2019 08:47:57 +0000 (09:47 +0100)]
Merge pull request #782 from whitequark/flowmap_dfs
flowmap: construct a max-volume max-flow min-cut, not just any one
Clifford Wolf [Mon, 7 Jan 2019 08:45:21 +0000 (09:45 +0100)]
Switch "bugpoint" from system() to run_command()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 7 Jan 2019 08:42:17 +0000 (09:42 +0100)]
Merge pull request #783 from whitequark/bugpoint
bugpoint: new pass
whitequark [Mon, 7 Jan 2019 00:11:49 +0000 (00:11 +0000)]
bugpoint: new pass.
A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:
flowmap -relax -optarea 100
and would be invoked as:
bugpoint -yosys ./yosys -script flowmap.ys -clean -cells
This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.
`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:
select i:* %x t:$_MUX_ %i -assert-max 0
would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
whitequark [Sun, 6 Jan 2019 19:51:37 +0000 (19:51 +0000)]
flowmap: construct a max-volume max-flow min-cut, not just any one.
Clifford Wolf [Sun, 6 Jan 2019 10:35:31 +0000 (11:35 +0100)]
Merge pull request #780 from phire/rename_from_wire
Rename cells based on the wires they drive.
Scott Mansell [Sun, 6 Jan 2019 01:40:10 +0000 (14:40 +1300)]
Rename cells based on the wires they drive.
Clifford Wolf [Sat, 5 Jan 2019 16:02:01 +0000 (17:02 +0100)]
Add skeleton Yosys-Libero igloo2 example project
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 5 Jan 2019 11:10:24 +0000 (12:10 +0100)]
Bugfix in Verilog string handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Fri, 4 Jan 2019 21:18:03 +0000 (21:18 +0000)]
flowmap: add -minlut option, to allow postprocessing with opt_lut.
Clifford Wolf [Fri, 4 Jan 2019 14:18:18 +0000 (15:18 +0100)]
Merge pull request #777 from mmicko/achronix_cell_sim_fix
Fix cells_sim.v for Achronix FPGA
Miodrag Milanovic [Fri, 4 Jan 2019 14:15:23 +0000 (15:15 +0100)]
Fix cells_sim.v for Achronix FPGA
Clifford Wolf [Fri, 4 Jan 2019 14:03:29 +0000 (15:03 +0100)]
Remove -m32 Verific eval lib build instructions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 4 Jan 2019 13:56:04 +0000 (14:56 +0100)]
Merge pull request #776 from mmicko/unify_noflatten
Unify usage of noflatten among architectures
Clifford Wolf [Fri, 4 Jan 2019 13:44:35 +0000 (14:44 +0100)]
Update Verific default path
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Fri, 4 Jan 2019 04:54:20 +0000 (04:54 +0000)]
flowmap: cleanup for clarity. NFCI.
Miodrag Milanovic [Fri, 4 Jan 2019 10:37:25 +0000 (11:37 +0100)]
Unify usage of noflatten among architectures
whitequark [Fri, 4 Jan 2019 02:46:27 +0000 (02:46 +0000)]
flowmap: improve debug graph output. NFC.
whitequark [Fri, 4 Jan 2019 02:33:10 +0000 (02:33 +0000)]
flowmap: add link to longer version of paper. NFC.
Clifford Wolf [Thu, 3 Jan 2019 16:03:18 +0000 (17:03 +0100)]
Merge pull request #775 from whitequark/opt_flowmap
flowmap: new techmap pass
whitequark [Wed, 2 Jan 2019 14:09:53 +0000 (14:09 +0000)]
flowmap: new techmap pass.
Clifford Wolf [Wed, 2 Jan 2019 16:34:04 +0000 (17:34 +0100)]
Merge pull request #770 from whitequark/opt_expr_cmp
opt_expr: refactor and improve simplification of comparisons
whitequark [Wed, 2 Jan 2019 05:04:28 +0000 (05:04 +0000)]
opt_expr: improve simplification of comparisons with large constants.
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.
However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.
This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
Clifford Wolf [Wed, 2 Jan 2019 15:28:18 +0000 (16:28 +0100)]
Merge pull request #755 from Icenowy/anlogic-dram-init
anlogic: implement DRAM initialization
Clifford Wolf [Wed, 2 Jan 2019 14:53:50 +0000 (15:53 +0100)]
Merge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Wed, 2 Jan 2019 14:52:22 +0000 (15:52 +0100)]
Merge pull request #750 from Icenowy/anlogic-ff-init
Initialization of Anlogic DFFs
Clifford Wolf [Wed, 2 Jan 2019 14:45:29 +0000 (15:45 +0100)]
Merge pull request #773 from whitequark/opt_lut_elim_fixes
opt_lut: elimination fixes
Clifford Wolf [Wed, 2 Jan 2019 14:44:57 +0000 (15:44 +0100)]
Merge pull request #772 from whitequark/synth_lut
synth: add k-LUT mode
Clifford Wolf [Wed, 2 Jan 2019 14:43:10 +0000 (15:43 +0100)]
Merge pull request #771 from whitequark/techmap_cmp2lut
cmp2lut: new techmap pass
Clifford Wolf [Wed, 2 Jan 2019 14:33:43 +0000 (15:33 +0100)]
Improve VerificImporter support for writes to asymmetric memories
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 2 Jan 2019 14:05:23 +0000 (15:05 +0100)]
Fix VerificImporter asymmetric memories error message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 2 Jan 2019 13:47:18 +0000 (14:47 +0100)]
Merge pull request #769 from whitequark/typos
Fix typographical and grammatical errors and inconsistencies
whitequark [Fri, 7 Dec 2018 19:14:07 +0000 (19:14 +0000)]
Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
whitequark [Wed, 2 Jan 2019 10:21:58 +0000 (10:21 +0000)]
opt_lut: reflect changes in sigmap.
Otherwise, some LUTs will be missed during elimination.
whitequark [Wed, 2 Jan 2019 09:36:32 +0000 (09:36 +0000)]
opt_lut: use a worklist, and revisit cells affected by elimination.
whitequark [Wed, 2 Jan 2019 08:40:01 +0000 (08:40 +0000)]
opt_lut: count eliminated cells, and set opt.did_something for them.
whitequark [Wed, 2 Jan 2019 08:25:55 +0000 (08:25 +0000)]
synth_ice40: use 4-LUT coarse synthesis mode.
whitequark [Wed, 2 Jan 2019 08:25:03 +0000 (08:25 +0000)]
synth: add k-LUT mode.
whitequark [Wed, 2 Jan 2019 08:05:44 +0000 (08:05 +0000)]
synth: improve script documentation. NFC.
whitequark [Wed, 2 Jan 2019 07:53:31 +0000 (07:53 +0000)]
cmp2lut: new techmap pass.
whitequark [Wed, 2 Jan 2019 04:31:20 +0000 (04:31 +0000)]
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
whitequark [Wed, 2 Jan 2019 03:01:25 +0000 (03:01 +0000)]
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
whitequark [Wed, 2 Jan 2019 02:45:49 +0000 (02:45 +0000)]
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
Clifford Wolf [Tue, 1 Jan 2019 10:13:48 +0000 (11:13 +0100)]
Merge pull request #768 from whitequark/opt_lut_elim
opt_lut: eliminate LUTs evaluating to constants or inputs
whitequark [Mon, 31 Dec 2018 23:53:23 +0000 (23:53 +0000)]
opt_lut: eliminate LUTs evaluating to constants or inputs.
Clifford Wolf [Mon, 31 Dec 2018 15:34:27 +0000 (16:34 +0100)]
Fix handling of (* keep *) wires in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 31 Dec 2018 14:52:01 +0000 (15:52 +0100)]
Merge pull request #766 from Icenowy/anlogic-latches
anlogic: add latch cells
Larry Doolittle [Fri, 28 Dec 2018 16:21:53 +0000 (08:21 -0800)]
Fix 7 instances of add_share_file to add_gen_share_file
in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
Larry Doolittle [Fri, 28 Dec 2018 16:24:31 +0000 (08:24 -0800)]
Squelch a little more trailing whitespace
Icenowy Zheng [Tue, 25 Dec 2018 14:47:46 +0000 (22:47 +0800)]
anlogic: add latch cells
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Clifford Wolf [Sun, 23 Dec 2018 15:16:06 +0000 (16:16 +0100)]
Merge pull request #761 from whitequark/proc_clean_partial
proc_clean: remove any empty cases, if possible to do safely
Clifford Wolf [Sun, 23 Dec 2018 14:45:09 +0000 (15:45 +0100)]
Add "read_ilang -[no]overwrite"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 23 Dec 2018 14:44:19 +0000 (15:44 +0100)]
Merge branch 'master' of github.com:YosysHQ/yosys
whitequark [Sun, 23 Dec 2018 09:04:23 +0000 (09:04 +0000)]
proc_clean: remove any empty cases if all cases use all-def compare.
Clifford Wolf [Sat, 22 Dec 2018 19:12:18 +0000 (20:12 +0100)]
Merge pull request #757 from whitequark/manual_mem
manual: document $meminit cell and memory_* passes
whitequark [Sat, 22 Dec 2018 08:58:37 +0000 (08:58 +0000)]
proc_clean: remove any empty cases at the end of the switch.
Previously, only completely empty switches were removed.
whitequark [Fri, 21 Dec 2018 01:26:08 +0000 (01:26 +0000)]
manual: make description of $meminit ports match reality.
Clifford Wolf [Fri, 21 Dec 2018 16:56:43 +0000 (17:56 +0100)]
Merge pull request #758 from whitequark/tcl_script_args
tcl: add support for passing arguments to scripts
Clifford Wolf [Fri, 21 Dec 2018 16:39:52 +0000 (17:39 +0100)]
Merge pull request #759 from whitequark/memory_collect_init_x
memory_collect: do not truncate 'x from \INIT
whitequark [Fri, 21 Dec 2018 02:01:27 +0000 (02:01 +0000)]
memory_collect: do not truncate 'x from \INIT.
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
whitequark [Thu, 20 Dec 2018 07:59:40 +0000 (07:59 +0000)]
manual: fix typos.
whitequark [Thu, 20 Dec 2018 07:29:46 +0000 (07:29 +0000)]
tcl: add support for passing arguments to scripts.
whitequark [Thu, 20 Dec 2018 04:37:28 +0000 (04:37 +0000)]
manual: document $meminit cell and memory_* passes.
Icenowy Zheng [Wed, 19 Dec 2018 02:18:47 +0000 (10:18 +0800)]
anlogic: implement DRAM initialization
As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Clifford Wolf [Wed, 19 Dec 2018 18:52:31 +0000 (19:52 +0100)]
Merge pull request #752 from Icenowy/anlogic-lut-cost
Anlogic: let LUT5/6 have more cost than LUT4-
Clifford Wolf [Wed, 19 Dec 2018 18:51:10 +0000 (19:51 +0100)]
Merge pull request #753 from Icenowy/anlogic-makefile-fix
anlogic: fix Makefile.inc
Clifford Wolf [Wed, 19 Dec 2018 18:48:54 +0000 (19:48 +0100)]
Merge pull request #749 from Icenowy/anlogic-dram-fix
anlogic: fix dbits of Anlogic Eagle DRAM16X4
Icenowy Zheng [Wed, 19 Dec 2018 02:23:58 +0000 (10:23 +0800)]
anlogic: fix Makefile.inc
During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.
Fix this issue.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Wed, 19 Dec 2018 01:36:53 +0000 (09:36 +0800)]
Anlogic: let LUT5/6 have more cost than LUT4-
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Clifford Wolf [Tue, 18 Dec 2018 19:02:39 +0000 (20:02 +0100)]
Minor style fixes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 18 Dec 2018 18:59:29 +0000 (19:59 +0100)]
Merge pull request #748 from makaimann/add-btor-ops
Add btor ops for $mul, $div, $mod and $concat
Clifford Wolf [Tue, 18 Dec 2018 18:55:42 +0000 (19:55 +0100)]
Merge pull request #751 from daveshah1/fix_589
memory_dff: Fix typo when checking init value
David Shah [Tue, 18 Dec 2018 17:40:01 +0000 (17:40 +0000)]
memory_dff: Fix typo when checking init value
Signed-off-by: David Shah <davey1576@gmail.com>
Clifford Wolf [Tue, 18 Dec 2018 16:49:38 +0000 (17:49 +0100)]
Fix segfault in AST simplify
(as proposed by Dan Gisselquist)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Icenowy Zheng [Tue, 18 Dec 2018 07:39:02 +0000 (15:39 +0800)]
anlogic: set the init value of DFFs
As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.
Support for set the init values of Anlogic DFFs.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Tue, 18 Dec 2018 15:10:40 +0000 (23:10 +0800)]
Add "dffinit -noreinit" parameter
Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.
Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Clifford Wolf [Tue, 18 Dec 2018 15:01:22 +0000 (16:01 +0100)]
Improve src tagging (using names and attrs) of cells and wires in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Icenowy Zheng [Tue, 18 Dec 2018 07:37:43 +0000 (15:37 +0800)]
Add "dffinit -strinit high low"
On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".
Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Tue, 18 Dec 2018 06:38:44 +0000 (14:38 +0800)]
anlogic: fix dbits of Anlogic Eagle DRAM16X4
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
makaimann [Mon, 5 Nov 2018 19:49:31 +0000 (11:49 -0800)]
Add btor ops for $mul, $div, $mod and $concat
Clifford Wolf [Mon, 17 Dec 2018 16:16:10 +0000 (17:16 +0100)]
Merge pull request #746 from Icenowy/anlogic-dram
Support for DRAM inferring on Anlogic FPGAs
Clifford Wolf [Mon, 17 Dec 2018 15:35:56 +0000 (16:35 +0100)]
Merge pull request #742 from whitequark/changelog
Update CHANGELOG to mention my improvements
Clifford Wolf [Mon, 17 Dec 2018 15:29:25 +0000 (16:29 +0100)]
Merge pull request #741 from whitequark/ilang_slice_sigspec
read_ilang: allow slicing all sigspecs, not just wires
Clifford Wolf [Mon, 17 Dec 2018 15:26:57 +0000 (16:26 +0100)]
Merge pull request #744 from whitequark/write_verilog_$shift
write_verilog: handle the $shift cell