Florent Kermarrec [Tue, 19 May 2020 08:44:36 +0000 (10:44 +0200)]
litex_setup: add sha1 support on git clone/pull and fix microwatt to a specific sha1.
The pythondata are generated automatically from external sources, some of them are
stable, some others still under development, so allow specifying a specific sha1
commit for sources that are moving and breaking LiteX support.
enjoy-digital [Tue, 19 May 2020 06:18:44 +0000 (08:18 +0200)]
Merge pull request #530 from enjoy-digital/bios-libs
BIOS: move cores' specific code to libs and cleanup.
Florent Kermarrec [Mon, 18 May 2020 21:35:48 +0000 (23:35 +0200)]
software/libbase: remove linker-sdram (unused).
Florent Kermarrec [Mon, 18 May 2020 21:33:34 +0000 (23:33 +0200)]
software/bios: mode spisdcard code to liblitesdcard.
Florent Kermarrec [Mon, 18 May 2020 21:26:51 +0000 (23:26 +0200)]
software/bios: rename commands to cmds and update with libs' names.
Florent Kermarrec [Mon, 18 May 2020 21:09:31 +0000 (23:09 +0200)]
software/bios: move hw flags definitions to respective libs, remove hw/flags.h.
Florent Kermarrec [Mon, 18 May 2020 20:49:12 +0000 (22:49 +0200)]
software: create liblitescard and move sdcard init/test code to it.
Florent Kermarrec [Mon, 18 May 2020 20:39:59 +0000 (22:39 +0200)]
software: create liblitedram and move sdram init/test code to it.
Florent Kermarrec [Mon, 18 May 2020 20:19:02 +0000 (22:19 +0200)]
bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash.
Florent Kermarrec [Mon, 18 May 2020 20:16:20 +0000 (22:16 +0200)]
software/bios/commands: rename cmd_mdio to cmd_liteeth.
Florent Kermarrec [Mon, 18 May 2020 19:09:41 +0000 (21:09 +0200)]
software/bios: move mdio to libliteeth.
Florent Kermarrec [Mon, 18 May 2020 19:04:54 +0000 (21:04 +0200)]
software/bios: rename libnet to libliteeth and move all ethernet files to it.
Florent Kermarrec [Mon, 18 May 2020 17:59:28 +0000 (19:59 +0200)]
software/bios: rename cmd_mem_access to cmd_mem.
Florent Kermarrec [Mon, 18 May 2020 15:28:41 +0000 (17:28 +0200)]
cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.
Florent Kermarrec [Mon, 18 May 2020 14:38:08 +0000 (16:38 +0200)]
cpu/microwatt: update microwatt_wraper.vhdl
Florent Kermarrec [Sun, 17 May 2020 09:03:21 +0000 (11:03 +0200)]
uptime: rework and integrate it in Timer to ease software support.
Florent Kermarrec [Sat, 16 May 2020 08:02:31 +0000 (10:02 +0200)]
bios: add uptime command and rewrite cmd_bios comments.
Florent Kermarrec [Sat, 16 May 2020 08:01:39 +0000 (10:01 +0200)]
soc: improve uptime comments.
enjoy-digital [Fri, 15 May 2020 14:03:37 +0000 (16:03 +0200)]
Merge pull request #526 from rprinz08/master
Make booting from SD-Card to behave same as from SPI flash
Florent Kermarrec [Fri, 15 May 2020 12:47:10 +0000 (14:47 +0200)]
soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled.
rprinz08 [Fri, 15 May 2020 10:07:52 +0000 (12:07 +0200)]
Make booting from SD-Card to behave same as from SPI flash
Florent Kermarrec [Thu, 14 May 2020 13:20:52 +0000 (15:20 +0200)]
bios/sdram: always show bitslip on two digits to keep scan aligned.
enjoy-digital [Thu, 14 May 2020 13:04:52 +0000 (15:04 +0200)]
Merge pull request #517 from ozbenh/csr-access-rework
csr: Rework accessors
Benjamin Herrenschmidt [Wed, 13 May 2020 11:50:44 +0000 (21:50 +1000)]
csr: Rework accessors
Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.
This *should* also also fix incorrect multiple accesses done
by 64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8
In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h
This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.
One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Florent Kermarrec [Thu, 14 May 2020 07:34:37 +0000 (09:34 +0200)]
CHANGES: update.
enjoy-digital [Thu, 14 May 2020 06:02:37 +0000 (08:02 +0200)]
Merge pull request #518 from enjoy-digital/csr_base
export: add define of CSR_BASE if not already defined and use it for …
enjoy-digital [Thu, 14 May 2020 05:17:46 +0000 (07:17 +0200)]
Merge pull request #523 from DurandA/patch-5
Update litex_term help
Arnaud Durand [Wed, 13 May 2020 20:50:09 +0000 (22:50 +0200)]
Update litex_term help
Specify the use of kernel address with flash flag.
Florent Kermarrec [Wed, 13 May 2020 17:11:46 +0000 (19:11 +0200)]
platforms/nexys4ddr: add card detect pin to sdcard.
Florent Kermarrec [Wed, 13 May 2020 16:26:54 +0000 (18:26 +0200)]
integration/soc: review/simplify interconnect and add logger.info.
enjoy-digital [Wed, 13 May 2020 14:48:21 +0000 (16:48 +0200)]
Merge pull request #519 from ozbenh/point2point
soc: Revive generation of a PointToPoint interconnect
Benjamin Herrenschmidt [Wed, 13 May 2020 14:06:15 +0000 (00:06 +1000)]
soc: Revive generation of a PointToPoint interconnect
When there's only one master, one slave, and that slave is at 0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Florent Kermarrec [Wed, 13 May 2020 13:52:09 +0000 (15:52 +0200)]
export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
This will allow more flexibility when integrating standalone cores.
Florent Kermarrec [Wed, 13 May 2020 09:04:40 +0000 (11:04 +0200)]
test/test_targets: workaround to fix travis.
Florent Kermarrec [Wed, 13 May 2020 07:31:20 +0000 (09:31 +0200)]
cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.
Florent Kermarrec [Wed, 13 May 2020 06:44:17 +0000 (08:44 +0200)]
bios/boot: review/fix #503.
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
enjoy-digital [Wed, 13 May 2020 06:36:43 +0000 (08:36 +0200)]
Merge pull request #503 from rprinz08/master
BIOS boot firmware from SPI with address offset
enjoy-digital [Wed, 13 May 2020 05:52:37 +0000 (07:52 +0200)]
Merge pull request #513 from mubes/bios_linker
Bios linker edits to prevent inappropriate optimisation
Dave Marples [Tue, 12 May 2020 22:32:49 +0000 (23:32 +0100)]
Bios linker edits to prevent inappropriate optimisation
rprinz08 [Tue, 12 May 2020 14:58:42 +0000 (16:58 +0200)]
fixed bug in BIOS spi flash "fw" command
rprinz08 [Tue, 12 May 2020 14:57:21 +0000 (16:57 +0200)]
removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram
Florent Kermarrec [Tue, 12 May 2020 14:51:47 +0000 (16:51 +0200)]
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
enjoy-digital [Tue, 12 May 2020 14:42:01 +0000 (16:42 +0200)]
Merge pull request #478 from antmicro/extended_spi_flash
Extended SPI flash support
enjoy-digital [Tue, 12 May 2020 14:35:29 +0000 (16:35 +0200)]
Merge pull request #510 from mubes/colorlight_usb
Colorlight usb
Florent Kermarrec [Tue, 12 May 2020 14:18:26 +0000 (16:18 +0200)]
integration/soc: review/simplify changes for standalone cores.
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
Dave Marples [Tue, 12 May 2020 13:40:11 +0000 (14:40 +0100)]
Fix dumb missing line
enjoy-digital [Tue, 12 May 2020 12:55:44 +0000 (14:55 +0200)]
Merge pull request #511 from ozbenh/standalone-cores
Improve standalone cores
Florent Kermarrec [Tue, 12 May 2020 10:53:01 +0000 (12:53 +0200)]
interconnect/wishbonebridge: refresh/simplify.
This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
Benjamin Herrenschmidt [Tue, 12 May 2020 11:37:36 +0000 (21:37 +1000)]
WB2CSR: Use CSR address_width for the wishbone bus
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 12 May 2020 11:35:12 +0000 (21:35 +1000)]
soc_core: Add option to override CSR base
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 12 May 2020 11:31:23 +0000 (21:31 +1000)]
soc: Don't update CSR alignment when there is no CPU
The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 12 May 2020 11:30:19 +0000 (21:30 +1000)]
soc: Don't create a wishbone slave to LiteDRAM with no CPU
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Dave Marples [Tue, 12 May 2020 11:28:09 +0000 (12:28 +0100)]
Bring into line with master
Benjamin Herrenschmidt [Tue, 12 May 2020 10:58:19 +0000 (20:58 +1000)]
soc: Don't create a share intercon with only one master and one slave
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
enjoy-digital [Tue, 12 May 2020 09:41:25 +0000 (11:41 +0200)]
Merge pull request #506 from scanakci/blackparrot_litex
Update README and core.py for Blackparrot and change vivado command for systemverilog
enjoy-digital [Tue, 12 May 2020 09:38:09 +0000 (11:38 +0200)]
Merge pull request #508 from antmicro/update_litesdcard
Update Litex bios to handle updated litesdcard.
Dave Marples [Tue, 12 May 2020 08:41:37 +0000 (09:41 +0100)]
Addition of boot address parameter for trellis builds
Kamil Rakoczy [Fri, 3 Apr 2020 12:58:36 +0000 (14:58 +0200)]
Update Litex bios to handle updated litesdcard.
sadullah [Tue, 12 May 2020 04:58:19 +0000 (00:58 -0400)]
Update README.md and core.py for BlackParrot
sadullah [Fri, 8 May 2020 06:17:37 +0000 (02:17 -0400)]
Vivado Command Update for Systemverilog
Add BlackParrot to LiteX setup file
enjoy-digital [Mon, 11 May 2020 20:53:31 +0000 (22:53 +0200)]
Merge pull request #505 from DurandA/patch-3
Enable 1x mode on SPI flash
Florent Kermarrec [Mon, 11 May 2020 20:39:17 +0000 (22:39 +0200)]
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
Arnaud Durand [Mon, 11 May 2020 20:12:40 +0000 (22:12 +0200)]
Enable 1x mode on SPI flash
Florent Kermarrec [Mon, 11 May 2020 08:50:25 +0000 (10:50 +0200)]
build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends.
enjoy-digital [Mon, 11 May 2020 07:55:52 +0000 (09:55 +0200)]
Merge pull request #502 from shuffle2/master
diamond: project generation improvements
enjoy-digital [Mon, 11 May 2020 07:42:55 +0000 (09:42 +0200)]
Merge pull request #490 from daveshah1/rdimm_bside_init
Add RDIMM side-B inversion support
enjoy-digital [Mon, 11 May 2020 07:42:35 +0000 (09:42 +0200)]
Merge branch 'master' into rdimm_bside_init
Florent Kermarrec [Mon, 11 May 2020 07:33:26 +0000 (09:33 +0200)]
lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args.
Florent Kermarrec [Mon, 11 May 2020 07:26:12 +0000 (09:26 +0200)]
lattice/trellis: simplify seed support and add it to trellis_args.
enjoy-digital [Mon, 11 May 2020 07:13:26 +0000 (09:13 +0200)]
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
enjoy-digital [Mon, 11 May 2020 06:58:28 +0000 (08:58 +0200)]
Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv
Added `imac` config for CPUs …
enjoy-digital [Mon, 11 May 2020 06:58:20 +0000 (08:58 +0200)]
Merge branch 'master' into cpu-imac-config-for-vexriscv
Florent Kermarrec [Mon, 11 May 2020 06:47:34 +0000 (08:47 +0200)]
integration/soc/add_adapter: rename is_master to direction.
enjoy-digital [Mon, 11 May 2020 06:34:03 +0000 (08:34 +0200)]
Merge pull request #504 from sergachev/master
integration/soc: fix add_adapter for slaves
Ilia Sergachev [Sun, 10 May 2020 09:32:34 +0000 (11:32 +0200)]
integration/soc: fix add_adapter for slaves
Benjamin Herrenschmidt [Sat, 9 May 2020 17:43:37 +0000 (19:43 +0200)]
bios: Fix warning on 64-bit
This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
rprinz08 [Sat, 9 May 2020 17:20:32 +0000 (19:20 +0200)]
BIOS boot firmware from SPI with address offset
Shawn Hoffman [Sat, 9 May 2020 09:16:24 +0000 (02:16 -0700)]
diamond: close project when done
Avoids ".recovery file is present" prompt.
Shawn Hoffman [Sat, 9 May 2020 04:00:24 +0000 (21:00 -0700)]
diamond: clock constraint improvements
Specify NET or PORT for freq constraints
Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
Florent Kermarrec [Fri, 8 May 2020 20:13:47 +0000 (22:13 +0200)]
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
Florent Kermarrec [Fri, 8 May 2020 11:17:59 +0000 (13:17 +0200)]
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
Florent Kermarrec [Fri, 8 May 2020 11:15:44 +0000 (13:15 +0200)]
integration/soc: add clock_domain parameter to add_etherbone.
To allow using a sys_clk < 125MHz with a 1Gbps link.
Florent Kermarrec [Fri, 8 May 2020 09:54:51 +0000 (11:54 +0200)]
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
Florent Kermarrec [Thu, 7 May 2020 10:11:59 +0000 (12:11 +0200)]
bios/sdram: fix lfsr typo.
enjoy-digital [Thu, 7 May 2020 09:55:58 +0000 (11:55 +0200)]
Merge pull request #500 from mubes/fixups
Fixups
Florent Kermarrec [Thu, 7 May 2020 09:34:26 +0000 (11:34 +0200)]
build/xilinx: add disable_constraints parameter to Platform.add_ip.
When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
Dave Marples [Thu, 7 May 2020 08:36:41 +0000 (09:36 +0100)]
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
Dave Marples [Thu, 7 May 2020 08:26:46 +0000 (09:26 +0100)]
Small fixups to address compiler warnings etc.
Florent Kermarrec [Thu, 7 May 2020 06:21:57 +0000 (08:21 +0200)]
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
Benjamin Herrenschmidt [Wed, 6 May 2020 19:54:27 +0000 (21:54 +0200)]
bios/sdram: Use an LFSR to speed up pseudo-random number generation
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
enjoy-digital [Wed, 6 May 2020 16:54:23 +0000 (18:54 +0200)]
Merge pull request #499 from DurandA/patch-2
Add data dirs to manifest
Florent Kermarrec [Wed, 6 May 2020 14:16:41 +0000 (16:16 +0200)]
boards/platforms: update xilinx programmers.
Florent Kermarrec [Wed, 6 May 2020 11:13:01 +0000 (13:13 +0200)]
build/xilinx/vivado: ensure Vivado process our .xdc early.
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.
Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
Arnaud Durand [Tue, 5 May 2020 20:15:24 +0000 (22:15 +0200)]
Add data dirs to manifest
Florent Kermarrec [Tue, 5 May 2020 14:58:33 +0000 (16:58 +0200)]
gen/fhdl/verilog: explicitly define input/output/inout wires.
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
Florent Kermarrec [Tue, 5 May 2020 14:33:14 +0000 (16:33 +0200)]
targets/genesys2: set cmd_latency to 1.
Florent Kermarrec [Tue, 5 May 2020 14:27:21 +0000 (16:27 +0200)]
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
Florent Kermarrec [Tue, 5 May 2020 13:55:09 +0000 (15:55 +0200)]
platforms/targets: fix CI.
Florent Kermarrec [Tue, 5 May 2020 13:27:56 +0000 (15:27 +0200)]
boards: keep in sync with LiteX-Boards, integrate improvements.
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
Florent Kermarrec [Tue, 5 May 2020 11:31:58 +0000 (13:31 +0200)]
build/lattice/programmer: add UJProg (for ULX3S).