Paul Berry [Sat, 11 Jan 2014 05:39:25 +0000 (21:39 -0800)]
mesa/cs: Add inline functions for dealing with compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Sat, 11 Jan 2014 05:39:25 +0000 (21:39 -0800)]
i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.
Also add code to brw_upload_state to set it when the compute program
changes.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Neil Roberts [Thu, 23 Apr 2015 23:56:53 +0000 (16:56 -0700)]
i965/fs: Strip trailing constant zeroes in sample messages
If a send message is emitted with a message length that is less than
required for the message then the remaining parameters default to
zero. We can take advantage of this to save a register when a shader
passes constant zeroes as the final coordinates to the sample
function.
I think this might be useful for GLES applications that are using 2D
textures to simulate 1D textures.
On Skylake it will be useful for shaders that do
texelFetch(tex,something,0) which I think is fairly common. This helps
more on Skylake because in that case the order of the instruction
operands are u,v,lod,r which is good for 2D textures whereas before
they were u,lod,v,r which is only good for 1D textures.
On Haswell:
total instructions in shared programs:
8535730 ->
8533261 (-0.03%)
instructions in affected programs: 236968 -> 234499 (-1.04%)
helped: 1174
On Skylake:
total instructions in shared programs:
10345646 ->
10341237 (-0.04%)
instructions in affected programs: 293011 -> 288602 (-1.50%)
helped: 1218
Reviewed-by: Matt Turner <mattst88@gmail.com>
v2: Applied suggestions by Kenneth Graunke:
- Only apply on Gen5+
- Apply to all texture opcodes, not just TEX and TXF.
Moved the optimisation into the loop as suggested by Matt Turner.
Fix the array index when there is a header.
Neil Roberts [Thu, 23 Apr 2015 17:09:52 +0000 (10:09 -0700)]
i965/skl: Force the exec size to 8 when initing header for SIMD4x2
On Gen9+ there needs to be a header when sampling using SIMD4x2. The
header is set up by copying from the g0 register. Commit
07c571a39f
tried to fix this mov instruction to always use an exec size of 8
because previously it was incorrectly using 4. It did this by casting
the type of the destination register to vec8. This was done because
there is code in brw_set_dest to guess the exec size based on the
width of the dest register. However I misunderstood how this works
because it is actually only used when the width is less than 8. That
means the patch actually changed it to use the default exec size which
on SIMD16 would be 16 and the MOV would clobber over the first
register in the send message. This patch makes it additionally set the
default exec size to 8. This is similar to how the message is set up
in fs_generator::generate_tex.
I think this wasn't picked up by any Piglit tests because we don't
have any fragment shaders that hit this code path so nothing was using
SIMD16. However the patch caused failures in deqp tests.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Kenneth Graunke [Thu, 12 Mar 2015 12:37:43 +0000 (05:37 -0700)]
i965: Unhardcode a few more stage names and abbreviations.
The stage_abbrev and stage_name fields in backend_visitor provide what
we need without any additional effort. It also means we'll get the
right names for compute shaders, SIMD8 geometry shaders, and both kinds
of tessellation shaders.
This does unfortunately change the capitalization of the stage
abbreviation in the INTEL_DEBUG=optimizer output filenames. It doesn't
seem worth adding code to handle, though.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Marek Olšák [Wed, 29 Apr 2015 18:33:21 +0000 (20:33 +0200)]
docs/relnotes: document the new EGL sync extensions
Marek Olšák [Fri, 10 Apr 2015 17:45:50 +0000 (19:45 +0200)]
st/dri: implement the fence interface for CL events
Marek Olšák [Fri, 10 Apr 2015 16:42:42 +0000 (18:42 +0200)]
gallium,clover: add OpenCL interoperability support for CL events
v2: - move interop.cpp to clover/api
- change intptr_t to void* in the interface
- add a virtual function fence() to simplify some code
v3: - use bool in the interface
v4: - enclose the last two interop functions in try..catch
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Marek Olšák [Fri, 10 Apr 2015 17:41:39 +0000 (19:41 +0200)]
st/dri: implement the fence interface
Marek Olšák [Fri, 10 Apr 2015 21:35:39 +0000 (23:35 +0200)]
egl/dri2: return the latest sync status in eglGetSyncAttribKHR
Marek Olšák [Fri, 10 Apr 2015 11:16:30 +0000 (13:16 +0200)]
egl/dri2: implement EGL_KHR_cl_event2 (v2)
v2: fix the SYNC_CONDITION query
Marek Olšák [Fri, 10 Apr 2015 10:04:18 +0000 (12:04 +0200)]
egl/dri2: implement EGL_KHR_wait_sync
Marek Olšák [Fri, 10 Apr 2015 08:56:02 +0000 (10:56 +0200)]
egl/dri2: implement EGL_KHR_fence_sync
Marek Olšák [Thu, 9 Apr 2015 21:26:14 +0000 (23:26 +0200)]
mesa: add GL_OES_EGL_sync
This is an empty extension whose presence means that EGL sync objects can be
used with ES contexts.
Marek Olšák [Fri, 10 Apr 2015 08:43:26 +0000 (10:43 +0200)]
dri_interface: add an interface for fences
Marek Olšák [Thu, 9 Apr 2015 21:25:07 +0000 (23:25 +0200)]
egl/dri: don't expose configs with an accumulation buffer
Ilia Mirkin [Thu, 30 Apr 2015 06:01:22 +0000 (02:01 -0400)]
nvc0/ir: fix predicated PFETCH for real
Commit
a9d08a250 accidentally didn't make use of the new src1 variable.
Use it.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Thu, 30 Apr 2015 03:33:27 +0000 (23:33 -0400)]
nv50/ir: fix asFlow() const helper for OP_JOIN
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Thu, 30 Apr 2015 03:05:44 +0000 (23:05 -0400)]
nvc0/ir: fix predicated PFETCH emission
src1 would contain the predicate, which would get emitted as a register
source by an undiscerning srcId helper. Work around this in the same way
as in emitTEX.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Wed, 29 Apr 2015 22:01:53 +0000 (18:01 -0400)]
gk110/ir: fix set with a register dest to not auto-set the abs flag
This was causing src0 to always have the absolute value flag set.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Topi Pohjolainen [Sun, 29 Mar 2015 18:52:02 +0000 (21:52 +0300)]
i965/blorp: Prepare drawing rectangle for flipped coordinates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 27 Mar 2015 14:25:56 +0000 (16:25 +0200)]
i965/blorp: Add support for layered rendering
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 26 Mar 2015 14:43:31 +0000 (16:43 +0200)]
i965/blorp: Allow blend state to be set for multiple render targets
Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.
Also drop the always constant color write disable settings.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 27 Feb 2015 09:45:34 +0000 (11:45 +0200)]
i965/blorp: Prepare for attributes other than render position
Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.
On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 30 Jan 2015 09:37:54 +0000 (11:37 +0200)]
i965/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 30 Jan 2015 09:30:34 +0000 (11:30 +0200)]
i965/gen7/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 27 Feb 2015 19:59:56 +0000 (21:59 +0200)]
i965/blorp: Allow caller to provide sampler settings
v2 (Ken): s/use_unorm_coords/non_normalized_coords/
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 27 Feb 2015 09:17:05 +0000 (11:17 +0200)]
i965/blorp: Refactor vertex buffer state setup
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Sat, 14 Mar 2015 08:21:33 +0000 (10:21 +0200)]
i965/blorp: Remove constant parameter
This was still needed when we had support for blorp clears but now
this is fixed to nop.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Mon, 2 Mar 2015 09:29:05 +0000 (11:29 +0200)]
i965/gen8: Expose state base address setup
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Mon, 2 Mar 2015 10:31:17 +0000 (12:31 +0200)]
i965/ps/gen8: Refactor state uploading
v2: Use SET_FIELD() for sampler count, and for that reason
added GEN7_PS_SAMPLER_COUNT_MASK.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Fri, 13 Feb 2015 09:20:05 +0000 (11:20 +0200)]
i965/ps/gen7: Refactor state uploading
Now the uploading depends only on the input parameters instead
of consulting the current gl-state.
v2: Rebased on top of sampler count clamping
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 2 Apr 2015 09:45:02 +0000 (12:45 +0300)]
i965: Refactor sampler state setup
v2 (Matt): Moved * to the name.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Sat, 4 Apr 2015 17:28:45 +0000 (20:28 +0300)]
i965: Remove dependency to tex object in default color setup
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 19 Mar 2015 08:42:49 +0000 (10:42 +0200)]
i965: Refactor and expose brw_upload_binding_table()
Read and write parts of the state stage are also split into
explicit arguments allowing future patches to use constant
program data.
v2 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 19 Mar 2015 09:09:54 +0000 (11:09 +0200)]
i965: Expose and refactor brw_update_renderbuffer_surfaces()
Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Tue, 17 Mar 2015 11:09:16 +0000 (13:09 +0200)]
i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
v2 (Matt): Fixed whitespace: tabs -> spaces
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Sun, 1 Mar 2015 20:23:33 +0000 (22:23 +0200)]
i965/gen8: Use constant pointers for reading miptree details
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Wed, 29 Apr 2015 17:35:45 +0000 (20:35 +0300)]
i965/ps: Use SET_FIELD() for sampler count
The value is actually clamped to 0-16 as sample state pointer
can be used to support more than 16 samplers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Ian Romanick [Wed, 15 Apr 2015 18:34:50 +0000 (11:34 -0700)]
glx: Massive update of comments in struct extension_info
In response to another patch, Emil asked for some clarification how this
stuff works. Rather than just reply to the e-mail, I decided to update
the exlanation in the code.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Marek Olšák [Thu, 16 Apr 2015 20:53:04 +0000 (22:53 +0200)]
winsys/radeon: add a private interface for radeon_surface
Marek Olšák [Thu, 16 Apr 2015 20:50:33 +0000 (22:50 +0200)]
winsys/radeon: move radeon_winsys.h to drivers/radeon
EdB [Thu, 23 Apr 2015 18:13:51 +0000 (20:13 +0200)]
clover: remove util/compat
Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Neil Roberts [Tue, 28 Apr 2015 13:20:06 +0000 (14:20 +0100)]
i965: Don't try to apply the opt_sampler_eot extension for vs
The opt_sampler_eot optimisation of fs_visitor effectively assumes
that it is running on a fragment shader because it casts the program
key to a brw_wm_prog_key. However on Skylake fs_visitor can also be
used for vertex shaders. It looks like this usually works anyway
because the optimisation is skipped if key->nr_color_regions != 1.
However for a vertex shader the key is actually a brw_vs_prog_key so
the space for nr_color_regions is probably taken up by
key->base.program_string_id. This can end up making nr_color_regions
be 1 in which case the function will later assert when the last
instruction is not FS_OPCODE_FB_WRITE. This was making the DEQP test
suite assert. Presumably this only happens there because that compiles
a lot of shaders so it would end up with a high value for
program_string_id.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Wed, 15 Apr 2015 13:44:02 +0000 (14:44 +0100)]
r300: do not link against libdrm_intel
Accidentally added since the introduction of the file.
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
EdB [Fri, 24 Apr 2015 10:59:56 +0000 (12:59 +0200)]
clover: make module::symbol::name a string
Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
EdB [Fri, 24 Apr 2015 10:59:55 +0000 (12:59 +0200)]
clover: remove compat::string
Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
EdB [Fri, 24 Apr 2015 10:59:54 +0000 (12:59 +0200)]
clover: remove compat classes that match std one
Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
EdB [Tue, 21 Apr 2015 13:49:09 +0000 (15:49 +0200)]
clover: compile all sources with c++11
Later we can remove the compat code
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Axel Davy [Fri, 20 Feb 2015 11:59:45 +0000 (12:59 +0100)]
st/nine: Remove Managed texture hack.
Previously binding an unitialized managed texture
was causing a crash, and a workaround was added to
prevent the crash.
This patch removes this workaround and instead set the initial
state of managed textures as dirty, so that when the texture is bound
for the first time, it is always initialized.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Fri, 20 Feb 2015 11:34:47 +0000 (12:34 +0100)]
st/nine: Enforce LOD 0 for D3DUSAGE_AUTOGENMIPMAP
For D3DUSAGE_AUTOGENMIPMAP textures, applications can only
lock/copy from/get surface descriptor for/etc the first level.
Thus it makes sense to restrict the LOD to 0, and use only the first
level to generate the sublevels.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Fri, 20 Feb 2015 11:11:56 +0000 (12:11 +0100)]
st/nine: Some D3DUSAGE_AUTOGENMIPMAP fixes
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 21:28:37 +0000 (22:28 +0100)]
st/nine: util_gen_mipmap doesn't need we reset states.
util_gen_mipmap uses pipe->blit, and thus doesn't need
we restore all states after using it.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 19:55:42 +0000 (20:55 +0100)]
st/nine: D3DUSAGE_AUTOGENMIPMAP is forbidden for volumes
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 19:23:06 +0000 (20:23 +0100)]
st/nine: Fix NineBaseTexture9_PreLoad
It wasn't uploading the texture when the lod
had changed.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 18:34:02 +0000 (19:34 +0100)]
st/nine: Rewrite Managed texture uploads
That part of the code was quite obscure.
This new implementation tries to make it clearer
by separating the differents parts, and commenting more.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 16:44:43 +0000 (17:44 +0100)]
st/nine: Bound the dirty regions to resource size
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 16:34:45 +0000 (17:34 +0100)]
st/nine: Simplify Surface9 Managed resources implementation
Remove the Surface9 code for dirty rects, used only for Managed
resources. Instead convey the information to the parent texture.
According to documentation, this seems to be the expected behaviour,
and if documentation is wrong there, that's not a problem since it can
only leads to more texture updates in corner cases.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 15:35:45 +0000 (16:35 +0100)]
st/nine: Remove impossible cases with Managed textures
Copying to/from a Managed texture is forbidden.
Rendering to a Managed texture is forbidden.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 15:18:00 +0000 (16:18 +0100)]
st/nine: Encapsulate variables for MANAGED resource
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 19 Feb 2015 10:21:12 +0000 (11:21 +0100)]
st/nine: Rework texture data allocation
Some applications assume the memory for multilevel
textures is allocated per continuous blocks.
This patch implements that behaviour.
v2: cache offsets
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Mon, 23 Mar 2015 22:31:18 +0000 (23:31 +0100)]
st/nine: Fix update_vertex_elements bad rebase
This code was supposed to be removed, but a rebase seems to have
made it stay.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 22 Mar 2015 10:49:03 +0000 (11:49 +0100)]
st/nine: Add debug warning when application uses sw processing
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Fri, 20 Feb 2015 17:25:44 +0000 (18:25 +0100)]
st/nine: Rework update_vertex_buffers
Previous code was trying to optimise to call set_vertex_buffers on
big packets, and thus avoids as many calls as possible.
However in practice doing so won't be faster (drivers implement
set_vertex_buffers by a loop over the buffers we want to bind)
When we want to unbind a buffer, we were calling set_vertex_buffers
on a buffer with vtxbuf->buffer = NULL. It works on some drivers,
but not on all of them, because it isn't in Gallium spec.
This patch fixes that.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Xavier Bouchoux [Mon, 16 Feb 2015 08:43:23 +0000 (09:43 +0100)]
st/nine: Fix computation of const_used_size
Was sometimes too large for PS.
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Axel Davy [Sun, 26 Apr 2015 21:19:03 +0000 (23:19 +0200)]
gallium/svga: Remove useless ARRAY_SIZE declaration
This is already declared in util/macros.h
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 26 Apr 2015 21:17:45 +0000 (23:17 +0200)]
util/macros: Move DIV_ROUND_UP to util/macros.h
Move DIV_ROUND_UP to a shared location accessible everywhere
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Xavier Bouchoux [Sat, 21 Feb 2015 18:58:38 +0000 (19:58 +0100)]
st/nine: Fix behaviour of D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING
Ignore D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING when
D3DUSAGE_RENDERTARGET is not specified.
This behaviour matches windows drivers.
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Xavier Bouchoux [Sat, 21 Feb 2015 18:56:40 +0000 (19:56 +0100)]
st/nine: Improve D3DQUERYTYPE_TIMESTAMP
Avoid blocking when retrieving D3DQUERYTYPE_TIMESTAMP result with
NineQuery9_GetData(), when D3DGETDATA_FLUSH is not specified.
This mimics Win behaviour and gives slightly better performance
for some games.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Xavier Bouchoux [Sun, 8 Feb 2015 14:56:15 +0000 (15:56 +0100)]
st/nine: Fix D3DQUERYTYPE_TIMESTAMPFREQ query
D3DQUERYTYPE_TIMESTAMPFREQ is supposed to give the frequency
at which the clock of D3DQUERYTYPE_TIMESTAMP runs.
PIPE_QUERY_TIMESTAMP returns a value in ns, thus the corresponding
frequency is
1000000000.
PIPE_QUERY_TIMESTAMP_DISJOINT returns the frequency at which
PIPE_QUERY_TIMESTAMP value is updated. It isn't always
1000000000.
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Tiziano Bacocco [Sun, 25 Jan 2015 11:15:39 +0000 (12:15 +0100)]
st/nine: Change x86 FPU Control word on device creation
As on wined3d and windows, when D3DCREATE_FPU_PRESERVE is not
specified, change the fpu control word to all exceptions masked,
single precision, round to nearest.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>
Axel Davy [Fri, 20 Feb 2015 11:51:55 +0000 (12:51 +0100)]
st/nine: Do not advertise D3DDEVCAPS_TEXTURESYSTEMMEMORY
No major vendor advertises it, and we weren't supporting it.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 23 Apr 2015 19:46:24 +0000 (21:46 +0200)]
st/nine: Fix comment in update_viewport
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Thu, 23 Apr 2015 19:46:09 +0000 (21:46 +0200)]
st/nine: Workaround barycentrics issue on some cards
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Xavier Bouchoux [Mon, 16 Feb 2015 09:02:42 +0000 (10:02 +0100)]
st/nine: Clear struct pipe_blit_info before use.
render_condition_enable was uninitialized.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Patrick Rudolph [Fri, 20 Feb 2015 14:48:57 +0000 (15:48 +0100)]
st/nine: NineDevice9_Clear skip fastpath for bigger depth-buffers
This adds an additional check to make sure the bound depth-buffer doesn't
exceed the rendertarget size when clearing depth and color buffer at once.
D3D9 clears only a rectangle with the same dimensions as the viewport, leaving
other parts of the depth-buffer intact.
This fixes failing WINE test visual.c:depth_buffer_test()
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sat, 21 Mar 2015 12:36:25 +0000 (13:36 +0100)]
st/nine: Fix wrong assert in nine_shader
The sampler src index was wrong for texldl and texldd
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Tue, 23 Dec 2014 14:15:10 +0000 (15:15 +0100)]
st/nine: Handle special LIT case
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Jose Fonseca [Tue, 28 Apr 2015 20:49:36 +0000 (21:49 +0100)]
mesa: Fix glGetProgramiv(GL_ACTIVE_ATTRIBUTES).
It's returning random values, because RESOURCE_VAR() is casting
different objects into ir_variable pointers.
This updates _mesa_count_active_attribs to filter the resources with the
same logic used in _mesa_longest_attribute_name_length.
https://bugs.freedesktop.org/show_bug.cgi?id=90207
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Marc-André Lureau [Tue, 28 Apr 2015 10:23:42 +0000 (12:23 +0200)]
egl: misc fixes for EGL_MESA_image_dma_buf_export
Fix define and a function argument name introduced in commit
8f7338f284cdb1fef64c85e3293d2200d0cc6387
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Tue, 28 Apr 2015 07:30:08 +0000 (03:30 -0400)]
nvc0/ir: flush denorms to zero in non-compute shaders
This will set the FTZ flag (flush denorms to zero) on all opcodes that
can take it.
This resolves issues in Unigine Heaven 4.0 where there were solid-filled
boxes popping up.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89455
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Sat, 25 Apr 2015 02:12:50 +0000 (20:12 -0600)]
meta: remove unneeded #include colortab.h
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Sat, 25 Apr 2015 02:12:42 +0000 (20:12 -0600)]
mesa: remove unneeded #include colortab.h
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Sat, 25 Apr 2015 02:04:29 +0000 (20:04 -0600)]
mesa: remove unused options var in compile_shader()
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Thu, 23 Apr 2015 16:00:34 +0000 (10:00 -0600)]
docs: more details about Viewperf 12 medical-01 test issues
Ilia Mirkin [Sun, 26 Apr 2015 20:15:02 +0000 (16:15 -0400)]
nvc0: expose GLSL version 410
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 26 Apr 2015 20:14:36 +0000 (16:14 -0400)]
st/mesa: allow glsl version up to 410, enable ARB_shader_precision
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Leo Liu [Thu, 12 Mar 2015 18:29:21 +0000 (14:29 -0400)]
st/va: add h264 decoder level support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Fri, 13 Mar 2015 16:39:26 +0000 (12:39 -0400)]
st/omx/dec: add h264 decoder level support
v2: use sps level idc as level to driver
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 16 Mar 2015 19:06:30 +0000 (15:06 -0400)]
vl: add level idc in sps
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Fri, 13 Mar 2015 16:25:42 +0000 (12:25 -0400)]
st/omx/dec: separate create_video_codec to different codecs
v2: get frame size from port info
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Thu, 12 Mar 2015 18:09:49 +0000 (14:09 -0400)]
st/vdpau: add h264 decoder level support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Thu, 12 Mar 2015 18:01:52 +0000 (14:01 -0400)]
gallium/util: get h264 level based on number of max references and resolution
v2: add commments for limitation of max references numbers,
and what the caculation is based
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Tue, 24 Feb 2015 00:26:13 +0000 (01:26 +0100)]
r600g,radeonsi: add a driver query returning GPU load
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Mon, 23 Feb 2015 23:50:20 +0000 (00:50 +0100)]
r600g,radeonsi: add driver queries for GPU temperature and shader+memory clocks
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Ilia Mirkin [Wed, 23 Jul 2014 03:45:13 +0000 (23:45 -0400)]
gm107/ir: add lane/vertex count sysvals
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 27 Apr 2015 16:54:43 +0000 (12:54 -0400)]
gk110/ir: add support for writing per-patch and shader outputs
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 25 Apr 2015 19:37:24 +0000 (15:37 -0400)]
freedreno/a3xx: color masking works like a blend for some formats
When there is a colormask active that does not cover all the channels,
enable reading in the destination like with a combining blend
operation. This fixes fbo-blending-formats on a3xx.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 22 Apr 2015 18:35:00 +0000 (14:35 -0400)]
freedreno/a3xx: add support for S8 and Z32F_S8
Enables ARB_depth_buffer_float. There is no sampling support for
interleaved Z32F_S8, so we store the two textures separately, one as
Z32F, the other as S8. As a result, we need a lot of additional logic
for restores and transfers.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 25 Apr 2015 05:21:26 +0000 (01:21 -0400)]
freedreno/a3xx: add Z32F support
32-bit depth buffers are stored as unorm, and thus need special handling
when moving to and from gmem. They are copied into gmem by writing
depth, and resolved from gmem using a special resolve bit which
apparently float-ifies the data.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>