nir: Add algebraic opt for int comparisons with identical operands.

No change on shader-db on i965.

v2: Reword the comment due to feedback from Erik Faye-Lund

Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v1)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> (v1)

nir: Fix load_const comparisons for CSE.

We want the size of a float per component, not the size of a whole vec4.

NIR instructions on i965:
total instructions in shared programs: 1261937 -> 1261929 (-0.00%)
instructions in affected programs:     114 -> 106 (-7.02%)

Looking at one of these examples (tesseract), it's from vec4 load_consts
for a MRT solid fill, which do get CSEed now that we don't memcmp off the
end of the const value and into the SSA def.  For the 1-component loads
that are common in i965, we were only memcmping off into the rest of the
usually zero-filled const_value.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

i965/fs: Remove conditional mod when optimizing a SEL into a MOV.

Missed in commit ca675b73, but got right in the companion commit 3c28b2c0.

darwin: build fix

xfont.c:237:14: error: implicit declaration of function 'GetGLXDRIDrawable' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
   glxdraw = GetGLXDRIDrawable(CC->currentDpy, CC->currentDrawable);
             ^
Fixes regression from 291be28476ea60c6fb1eb2a882e2e25def5d3735

Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>

darwin: build fix

../../../src/mesa/main/compiler.h:47:10: fatal error: 'util/macros.h' file not found

Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>

glsl: Optimize 1/exp(x) into exp(-x).

Lots of shaders divide by exp2(...) which we turn into a multiplication
by the reciprocal. We can avoid the reciprocal by simply negating exp2's
argument.

total instructions in shared programs: 5947154 -> 5946695 (-0.01%)
instructions in affected programs:     118661 -> 118202 (-0.39%)
helped:                                380

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir: Remove casts from void*.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Replace assert(0) with unreachable().

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Remove unused has_indirect variable.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Emit MADs from (x + abs(y * z)).

Same as commit 3654b6d4 to the fs backend.

total instructions in shared programs: 5945788 -> 5945787 (-0.00%)
instructions in affected programs:     36 -> 35 (-2.78%)
helped:                                1

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Emit MADs from (x + -(y * z)).

Same as commit c4fab711 to the fs backend.

total instructions in shared programs: 5945998 -> 5945788 (-0.00%)
instructions in affected programs:     74665 -> 74455 (-0.28%)
helped:                                399
HURT:                                  180

It hurts some programs because we make no attempts in the vec4 backend
to avoid MADs if they have constant (or vector uniform) arguments.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/skl: Implement WaDisable1DDepthStencil

Skylake+ doesn't support setting a depth buffer to a 1D surface but it
does allow pretending it's a 2D texture with a height of 1 instead.

This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit
test (and also seems to avoid a subsequent GPU hang).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89037
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen7-8: Implement glMemoryBarrier().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-renderbuffers.

Null surfaces are going to be useful to have something to point
unbound image units to, as the ARB_shader_image_load_store extension
requires us to behave deterministically in cases where some shader
tries to access an unbound image unit: Invalid stores and atomics are
supposed to be discarded and invalid loads are supposed to return
zero, which is precisely what the null surface does.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Allocate binding table space for shader images.

v2: Bump the number of supported image uniforms to 32 (Ken).

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't tile 1D miptrees.

It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.

v2: Check mt->logical_height0 instead of mt->target (Ken).  Add short
    comment explaining why they shouldn't be tiled.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.

It's expanded to several instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Handle negated unsigned immediate values in constant propagation.

Negation of UD/UW sources behaves the same as for D/W sources, taking
the two's complement of the source, except for bitwise logical
operations on Gen8 and up which take the one's complement.  Fixes
crash in a GLSL shader with subtraction of two unsigned values.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Take into account non-zero reg_offset during register allocation.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Add register classes up to MAX_VGRF_SIZE.

In preparation for some send from GRF instructions that will require
larger payloads.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Init mlen for several send from GRF instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Don't infer MRF dependencies for send from GRF instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix the scheduler to take into account reads and writes of multiple registers.

v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends from GRF.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Pass dst register to the vec4_instruction constructor.

So regs_written gets initialized with a sensible value.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Implement equals() method for dst_reg too.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.

Scalar registers are required to have zero stride, fix the
regs_written calculation not to assume that the instruction writes
zero registers in that case.

v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Fix stack allocation of fs_inst and stop stealing src array provided on construction.

Using 'ralloc*(this, ...)' is wrong if the object has automatic
storage or was allocated through any other means.  Use normal dynamic
memory instead.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Remove duplicate include of brw_shader.h

The second one was inside an extern "C" block, luckily it was being
discarded by the preprocessor.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move up fs_inst::flag_subreg to backend_instruction.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move up fs_inst::regs_written to backend_instruction.

It will also be useful in the VEC4 back-end.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Remove dependency of vec4_instruction on the visitor class.

The only reason why you need a vec4_visitor to construct a
vec4_instruction is to initialize vec4_instruction::ir and
::annotation.  Instead set them from vec4_visitor::emit() just like
fs_visitor does.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Remove dependency of fs_inst on the visitor class.

The fs_visitor argument of fs_inst::regs_read() wasn't used at all.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move IR object definitions to separate header files.

One should be able to manipulate i965 IR without pulling the whole
FS/VEC4 visitor classes -- Optimization passes and other
transformations would ideally be visitor-agnostic.  Among other issues
this avoids a circular dependency between the header file where such
visitor-agnostic code will be defined and the main FS/VEC4 header
where both IR (layer below) and visitor (layer above) happen to be
defined.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Factor out virtual GRF allocation to a separate object.

Right now virtual GRF book-keeping and allocation is performed in each
visitor class separately (among other hundred different things),
leading to duplicated logic in each visitor and preventing layering as
it forces any code that manipulates i965 IR and needs to allocate
virtual registers to depend on the specific visitor that happens to be
used to translate from GLSL IR.

v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor).

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Forbid calling the constructor of any opaque type.

The spec doesn't define any opaque type constructors.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Return correct number of coordinate components for cubemap array images.

Cubemap array images are unlike cubemap array samplers in that they don't need
an additional coordinate to index individual cubemaps in the array, instead
they behave like a 2D array of 6n layers, with n the number of cubemaps in the
array.  Take this exception into account.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Bump MAX_IMAGE_UNIFORMS to 32.

So the i965 driver can expose 32 image uniforms per shader stage.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Rename the CEILING() macro to DIV_ROUND_UP().

Some people have complained that code using the CEILING() macro is
difficult to understand because it's not immediately obvious what it
is supposed to do until you go and look up its definition.  Use a more
descriptive name that matches the similar utility macro in the Linux
kernel.

Reviewed-by: Matt Turner <mattst88@gmail.com>

nv50,nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediately

Without this when an application issues that query, it would try to
wait the result from the gpu, and since no query has been actually
issued, it will wait forever.

Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: Fold IMM into MAD

Add a specific optimisation pass for NV50 to check whether SRC0 or SRC1 is
a MOV dst, IMM. If so: fold the IMM in and try to drop the MOV. Must be
done post-RA because it requires that SDST == SSRC2.

V2: improve readability and add comments to clarify decisions
V3: Remove redundant code... compiler already attempts to put the IMM in
SSRC1

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: Add emit support for MAD IMM format

But don't enable generation of it in the opProperties, because we can't
guarantee the SDST==SRC2 constraint until after register assignment. We'll
add a post-RA folding pass to utilise this.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: Add support for MAD 4-byte opcode

Add emission rules for negative and saturate flags for MAD 4-byte opcodes,
and get rid of some of the constraints. Obviously tested with a wide variety
of shaders.

V2: Document MAD as supported short form
V3: Split up IMM from short-form modifiers

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: change the way float face is returned

The old way made it impossible for the optimizer to reason about what
was going on. The new way is the same number of instructions (the neg
gets folded into the cvt) but enables the optimizer to be cleverer if
comparing to a constant (most common case). [The optimizer is presently
not sufficiently clever to work this out, but it could relatively easily
be made to be. The old way would have required significant complexity to
work out.]

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nir: Mark nir_print_instr's instr pointer as const.

Printing instructions doesn't modify them, so we can mark the parameter
const.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965: Fix integer border color on Haswell.

+82 Piglits - 100% of border color tests now pass on Haswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org

i965: Use a gl_color_union for sampler border color.

This should have no effect, but will make it easier to implement other
bug fixes.

v2: Eliminate "unsigned one" local; just use the value where necessary.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org

i965: Override swizzles for integer luminance formats.

The hardware's integer luminance formats are completely unusable;
currently we fall back to RGBA.  This means we need to override
the texture swizzle to obtain the XXX1 values expected for luminance
formats.

Fixes spec/EXT_texture_integer/texwrap formats bordercolor [swizzled]
on Broadwell - 100% of border color tests now pass on Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org

util/u_atomic: Add new macro p_atomic_add

This provides for atomic addition, which will be used by an upcoming
shader-cache patch. A simple test is added to "make check" as well.

Note: The various O/S functions differ on whether they return the
original value or the value after the addition, so I did not provide
an add_return() macro which would be sensitive to that difference.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>

util/hash_table: Try to hit a double-insertion bug in the collision test

Reviewed-by: Eric Anholt <eric@anholt.net>

util/set: Do a full search when adding new items

Previously, the set_insert function would bail early if it found a deleted
slot that it could re-use.  However, this is a problem if the key being
inserted is already in the set but further down the list.  If this happens,
the element ends up getting inserted in the set twice.  This commit makes
it so that we walk over all of the possible entries for the given key and
then, if we don't find the key, place it in the available free entry we
found.

Reviewed-by: Eric Anholt <eric@anholt.net>

util/hash_table: Do a full search when adding new items

Previously, the hash_table_insert function would bail early if it found a
deleted slot that it could re-use.  However, this is a problem if the key
being inserted is already in the hash table but further down the list.  If
this happens, the element ends up getting inserted in the hash table twice.
This commit makes it so that we walk over all of the possible entries for
the given key and then, if we don't find the key, place it in the available
free entry we found.

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Make renderbuffer FBO attachments not layered

For framebuffer completeness checks, consider renderbuffers as not
layered. Previously, they would have counted as layered if a layered
textured had previously been bound to the same attachment point. This
could cause framebuffer completeness checks to incorrectly fail with
GL_FRAMEBUFFER_INCOMPLETE_LAYER_TARGETS, even if no layered attachments
were present.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89026

Post-branch version bump to 10.6.0-devel, add release notes template

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/hud: also try R8_UNORM format for font texture

Convert the code to try formats from an array rather than a bunch
of if/else cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/hud: flush stdout in print_help(), for Windows

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Add more stringent blitter assertions

Blits to or from a y-tiled surface must always be a multiple of the tile size.
From page 16 of the HSW PRM
(https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16)
"The pitch of a tiled enclosing region must be an integral number of tile
widths"

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965: Consolidate some of the intel_blit logic

An upcoming patch is going to introduce some code here, and having this code
organized as the patch does makes it a bit easier to read later.

There should be no functional change here.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

st/dri: Make depth buffer optional for postprocessing

Since only pp_jimenezmlaa uses depth buffer, we can make it optional.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

postprocess: Check for depth buffer in pp_jimenezmlaa

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88962
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

i965/vec4: Correct MUL destination hazard

As it turns out, we were over-thinking the cause of the hang on
Cherryview. It's simply errata for Cherryview.

commit 88fea85f09e2252035bec66ab26c375b45b000f5
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Fri Nov 21 10:47:41 2014 -0800

    i965/vec4/gen8: Handle the MUL dest hazard exception

This is an explanation to why we never saw the hang on BDW.

NOTE: The problem the original patch was trying to fix does still exist. It will
have to be fixed at some point.

v2: Modify commit message, s/CHV/BDW

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: add news item and link release notes for mesa 10.4.4

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256 sums for the 10.4.4 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 54da987baec25fbaf6975c93f197ddbfe65a303c)

Add release notes for the 10.4.4 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 62eb27ac8bbd979796f50e253f6c786d7d791242)

nir: Fix broken fsat recognizer.

We've probably never seen this ridiculous pattern in the wild, so it
didn't matter.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nir: Slightly simplify algebraic code generation by reusing a struct.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

tgsi/ureg: Add missing some missing opcodes opcode_tmp.h

I wanted all of these for NIR-to-TGSI.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

tgsi/ureg: Move ureg_dst_register() to the header.

I wanted to use it for nir-to-tgsi.  The equivalent ureg_src_register() is
also located here.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium/u_tests: test a NULL buffer sampler view

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

gallium/u_tests: test a NULL constant buffer

This expects (0,0,0,0), though it can be changed to something else or allow
more than one set of values to be considered correct.

This is currently the radeonsi behavior.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

gallium/u_tests: test a NULL texture sampler view

v2: allow one of the two values

gallium/u_tests: restructure the only test, refactor out reusable code

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

gallium: run gallium tests if GALLIUM_TESTS=1 is set

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

gallium/postprocessing: fix crash at context destruction

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g/sb: fix a bug in constants folding optimisation pass

    ADD     R6.y.1,    R5.w.1, ~1|3f800000
    ADD     R6.y.2,    |R6.y.1|, -0.0001|b8d1b717

was wrongly being converted to

    ADD     R6.y.1,    R5.w.1, ~1|3f800000
    ADD     R6.y.2,    R5.w.1, -1.0001|bf800347

because abs() modifier was ignored.

Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

r600g: fix abs() support on ALU 3 source operands instructions

Since alu does not support abs() modifier on source operands, spill
and apply the modifiers to a temp register when needed.

Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

r300g: small code cleanup (v2)

v2: incorporated changes from Marek Olšák

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: David Heidelberg <david@ixit.cz>

glsl: GLSL ES identifiers cannot exceed 1024 characters

v2 (Ian Romanick)
- Move the check to the lexer before rallocing a copy of the large string.

Fixes the following 2 dEQP tests:
dEQP-GLES3.functional.shaders.keywords.invalid_identifiers.max_length_vertex
dEQP-GLES3.functional.shaders.keywords.invalid_identifiers.max_length_fragment

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS (and GS).

We were incorrectly attributing VS time to FS8 on Gen8+, which now use
fs_visitor for vertex shaders.

We don't hit this for geometry shaders yet, but we may as well add
support now - the fix is obvious, and we'll just forget later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/fs: Use inst->eot rather than opcodes in register allocation.

Previously, we special cased FB writes and URB writes in the register
allocation code.  What we really wanted was to handle any message with
EOT set.

This saves us from extending the list with new opcodes in the future.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/fs: Delete is_last_send(); just check inst->eot.

This helper function basically just checks inst->eot, but also asserts
that only opcodes we expect to terminate threads have EOT set.  As far
as I'm aware, we've never had such a bug.

Removing it means that we don't have to extend the list for new opcodes.
Cherryview and Skylake introduce an optimization where sampler messages
can have EOT set; scalar GS/HS/DS will likely introduce new opcodes as
well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

st/mesa: Don't use PIPE_USAGE_STREAM for GL_PIXEL_UNPACK_BUFFER_ARB

The latter currently implies CPU read access, so only PIPE_USAGE_STAGING
can be expected to be fast.

Mesa demos src/tests/streaming_rect on Kaveri (radeonsi):

Unpatched:  42 frames in  1.023 seconds = 41.056 FPS
Patched:   615 frames in  1.000 seconds = 615.000 FPS

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88658
Cc: "10.3 10.4" <mesa-stable@lists.freedestkop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/nine: Implement dummy vbo behaviour when vs is missing inputs

Use a dummy vertex buffer object when vs inputs have no corresponding
entries in the vertex declaration. This dummy buffer will give to the
shader float4(0,0,0,0).

This fixes several artifacts on some games.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>

gallium/targets/d3dadapter9: Free card device

The drm fd wasn't released, causing a crash
for wine tests on nouveau, which seems to have
a bug when a lot of device descriptors are open.

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

gallium/targets/d3dadapter9: Release the pipe_screen at destruction.

We weren't releasing hal and ref, causing some issues (threads not released, etc)

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

gallium/targets/d3dadapter9: Fix device detection for render-nodes

When on a render node the unique ioctl doesn't work.

This patch drops the code to detect the device, which relied
on an ioctl, and replaces it by the mesa loader function.
The mesa loader function is more complete and won't fail for render-nodes.

Alternatively we could also have used the pipe cap to
determine the vendor and device id from the driver.

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Dummy sampler should have a=1

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix update_framebuffer binding cbufs the pixel shader wouldn't render to

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Clear: better behave if rt_mask is different to the one of the framebuffer bound

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix multisampling support detection

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix enabled lights in stateblocks

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>

st/nine: Fix depth stencil formats bindings flags.

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix gpu memory leak in swapchain

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: SetResourceResize should track nr_samples too

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: D3DRS_FILLMODE set to 0 is D3DFILL_SOLID

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>

st/nine: Setting D3DRS_ALPHAFUNC to 0 means D3DCMP_NEVER

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>

st/nine: Implement fallback behaviour when rts and ds don't match

This seems to be the behaviour on Win. Previous behaviour led
to different issues depending on the driver.

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix present_buffers allocation

If has_present_buffers was false at first,
but after a device reset, it turns true (for
example if we begin to render to a multisampled
back buffer), there was a crash due to present_buffers
being uninitialised.
This patch fixes it.

Reviewed-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Check for aligned offset in each vertex element

Fixes wine test test_vertex_declaration_alignment()

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>