openpower-isa.git
2 years agosv_analysis: use is instead of eq for enums
Dmitry Selyutin [Tue, 30 Nov 2021 13:42:10 +0000 (13:42 +0000)]
sv_analysis: use is instead of eq for enums

2 years agosv_analysis: fix single-line binutils comments
Dmitry Selyutin [Tue, 30 Nov 2021 13:41:19 +0000 (13:41 +0000)]
sv_analysis: fix single-line binutils comments

2 years agoadd randomised hazard test
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 18:29:09 +0000 (18:29 +0000)]
add randomised hazard test

2 years agoadd two more hazard tests
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 16:18:18 +0000 (16:18 +0000)]
add two more hazard tests

2 years agoattempting to use PowerDecode2 in non-svp64 mode
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 10:43:47 +0000 (10:43 +0000)]
attempting to use PowerDecode2 in non-svp64 mode

2 years agosv_analysis: decouple common disclaimer
Dmitry Selyutin [Sat, 27 Nov 2021 20:28:22 +0000 (20:28 +0000)]
sv_analysis: decouple common disclaimer

2 years agosv_analysis: introduce stub binutils format
Dmitry Selyutin [Sat, 27 Nov 2021 19:36:25 +0000 (19:36 +0000)]
sv_analysis: introduce stub binutils format

2 years agosv_analysis: support format argument
Dmitry Selyutin [Sat, 27 Nov 2021 19:35:01 +0000 (19:35 +0000)]
sv_analysis: support format argument

2 years agoadd extra overlap hazard test
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 14:29:51 +0000 (14:29 +0000)]
add extra overlap hazard test

2 years agoShorten expected state code for case_extsb using exts function
R Veera Kumar [Fri, 26 Nov 2021 17:48:02 +0000 (23:18 +0530)]
Shorten expected state code for case_extsb using exts function

2 years agoShorten expected state code for case_extsb in alu_cases unit test
R Veera Kumar [Fri, 26 Nov 2021 03:09:56 +0000 (08:39 +0530)]
Shorten expected state code for case_extsb in alu_cases unit test

2 years agoShorten expected state code for case_rand in alu_cases unit test
R Veera Kumar [Fri, 26 Nov 2021 02:53:12 +0000 (08:23 +0530)]
Shorten expected state code for case_rand in alu_cases unit test

2 years agoShorten case_rand_imm alu test case code
R Veera Kumar [Fri, 26 Nov 2021 02:26:50 +0000 (07:56 +0530)]
Shorten case_rand_imm alu test case code

Shorten addis sub test code
Shorten subfic sub test code in general
In subfic case shorten carry_out32 execution code
Make carry_out32 variable boolean and expected state ca var less confusing

2 years agoMake carry_out32 variable boolean and expected state ca var less confusing
R Veera Kumar [Fri, 26 Nov 2021 01:53:29 +0000 (07:23 +0530)]
Make carry_out32 variable boolean and expected state ca var less confusing

2 years agoShortened code in case_addis_nonzero_r0 alu test case
R Veera Kumar [Thu, 25 Nov 2021 10:15:21 +0000 (15:45 +0530)]
Shortened code in case_addis_nonzero_r0 alu test case

2 years agoCorrect add-equal operator in case_rand_imm
R Veera Kumar [Thu, 25 Nov 2021 09:45:18 +0000 (15:15 +0530)]
Correct add-equal operator in case_rand_imm

2 years agoShort the code of case_rand_imm
R Veera Kumar [Thu, 25 Nov 2021 01:21:23 +0000 (06:51 +0530)]
Short the code of case_rand_imm

2 years agoFix line so that 80 characters per line is kept and removed a comment
R Veera Kumar [Wed, 24 Nov 2021 23:47:35 +0000 (05:17 +0530)]
Fix line so that 80 characters per line is kept and removed a comment

2 years agoAdd expected state to case_rand_imm in alu_cases unit test
R Veera Kumar [Wed, 24 Nov 2021 23:39:34 +0000 (05:09 +0530)]
Add expected state to case_rand_imm in alu_cases unit test

2 years agocorrections to hazard overlap test
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 23:12:00 +0000 (23:12 +0000)]
corrections to hazard overlap test

2 years agoadd extra hazard unit tests
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 22:46:37 +0000 (22:46 +0000)]
add extra hazard unit tests

2 years agotidyup on case_0_adde
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:17:29 +0000 (16:17 +0000)]
tidyup on case_0_adde

2 years agocorrect write-after-write hazard test (expected values)
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:08:15 +0000 (16:08 +0000)]
correct write-after-write hazard test (expected values)

2 years agoAdd expected state to case_0_adde in alu_cases unit test
R Veera Kumar [Tue, 23 Nov 2021 17:58:03 +0000 (23:28 +0530)]
Add expected state to case_0_adde in alu_cases unit test

2 years agoadd write-after-write hazard test for inorder core
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 15:16:28 +0000 (15:16 +0000)]
add write-after-write hazard test for inorder core

2 years agoAdd expected state to case_rand in alu_cases unit test
R Veera Kumar [Tue, 23 Nov 2021 14:07:39 +0000 (19:37 +0530)]
Add expected state to case_rand in alu_cases unit test

2 years agoAdd expected state to case_addis_nonzero_r0 in alu_cases unit test
R Veera Kumar [Tue, 23 Nov 2021 12:13:58 +0000 (17:43 +0530)]
Add expected state to case_addis_nonzero_r0 in alu_cases unit test

2 years agoAdd expected state to case_extsb in alu_cases unit test
R Veera Kumar [Tue, 23 Nov 2021 11:18:15 +0000 (16:48 +0530)]
Add expected state to case_extsb in alu_cases unit test

2 years agoAdd computed CR0 to expected version of case_adde_0
R Veera Kumar [Tue, 23 Nov 2021 06:09:04 +0000 (11:39 +0530)]
Add computed CR0 to expected version of case_adde_0

2 years agoadd expected version of case_adde_0
Luke Kenneth Casson Leighton [Mon, 22 Nov 2021 12:11:09 +0000 (12:11 +0000)]
add expected version of case_adde_0

2 years agoadding a couple more hazard avoidance cases
Luke Kenneth Casson Leighton [Mon, 22 Nov 2021 11:51:07 +0000 (11:51 +0000)]
adding a couple more hazard avoidance cases

2 years agoAdd expected state to case_cmpeqb in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 10:24:08 +0000 (15:54 +0530)]
Add expected state to case_cmpeqb in alu_cases unit test

2 years agoAdd expected state to case_cmplw_microwatt_1 in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 06:26:17 +0000 (11:56 +0530)]
Add expected state to case_cmplw_microwatt_1 in alu_cases unit test

2 years agoAdd expected state to case_cmpli_microwatt in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 05:32:57 +0000 (11:02 +0530)]
Add expected state to case_cmpli_microwatt in alu_cases unit test

2 years agoAdd expected state to case_cmpl_microwatt_0_disasm in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 04:45:01 +0000 (10:15 +0530)]
Add expected state to case_cmpl_microwatt_0_disasm in alu_cases unit test

2 years agoAdd expected state to case_cmpl_microwatt_0 in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 04:30:28 +0000 (10:00 +0530)]
Add expected state to case_cmpl_microwatt_0 in alu_cases unit test

2 years agoAdd expected state to case_addme_ca_so_4 in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 02:34:26 +0000 (08:04 +0530)]
Add expected state to case_addme_ca_so_4 in alu_cases unit test

2 years agoAdd expected state to case_addme_ca_so_3 in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 02:18:06 +0000 (07:48 +0530)]
Add expected state to case_addme_ca_so_3 in alu_cases unit test

2 years agoAdd expected state to case_addme_ca_1 in alu_cases unit test
R Veera Kumar [Mon, 22 Nov 2021 01:52:15 +0000 (07:22 +0530)]
Add expected state to case_addme_ca_1 in alu_cases unit test

2 years agosigh, for overlap mode there is no safe way to get instruction state.
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 21:04:21 +0000 (21:04 +0000)]
sigh, for overlap mode there is no safe way to get instruction state.
therefore, just check the last one.

2 years agomove dump state to base class State in test API
Luke Kenneth Casson Leighton [Sun, 21 Nov 2021 21:03:52 +0000 (21:03 +0000)]
move dump state to base class State in test API

2 years agoAdd expected state to case_cmp3 in alu_cases unit test
R Veera Kumar [Sun, 21 Nov 2021 17:15:28 +0000 (22:45 +0530)]
Add expected state to case_cmp3 in alu_cases unit test

2 years agoAdd expected state to case_cmp2 in alu_cases unit test
R Veera Kumar [Sun, 21 Nov 2021 15:32:41 +0000 (21:02 +0530)]
Add expected state to case_cmp2 in alu_cases unit test

2 years agoAdd expected state to case_cmp in alu_cases unit test
R Veera Kumar [Sun, 21 Nov 2021 14:16:02 +0000 (19:46 +0530)]
Add expected state to case_cmp in alu_cases unit test

2 years agoAdd expected state to all of case_addze in alu_cases unit test
R Veera Kumar [Sun, 21 Nov 2021 11:22:28 +0000 (16:52 +0530)]
Add expected state to all of case_addze in alu_cases unit test

2 years agoadd bitmanip_cases.py
Jacob Lifshay [Wed, 17 Nov 2021 20:50:50 +0000 (12:50 -0800)]
add bitmanip_cases.py

2 years agorename ternary->ternlog and associated form/field TI->TLI
Jacob Lifshay [Wed, 17 Nov 2021 19:25:21 +0000 (11:25 -0800)]
rename ternary->ternlog and associated form/field TI->TLI

2 years agoadd allow_overlap argument to TestRunnerBase
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 16:22:35 +0000 (16:22 +0000)]
add allow_overlap argument to TestRunnerBase

this is to filter down to TestIssuer which (surprise) will be allowed
to have instructions be issued that overlap

2 years agocode-comments
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 16:15:01 +0000 (16:15 +0000)]
code-comments

2 years agoXER regspec_decode_write was not sophisticated enough.
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 15:52:41 +0000 (15:52 +0000)]
XER regspec_decode_write was not sophisticated enough.

XER is being written to without the hazard vector being set.
this previously did not matter because the TestIssuer FSM was
only allowing one pipeline access to all regfiles at a time.

in-order now will have overlapping instructions so it matters

2 years agosplit up regression cases so that a single Rc=1 add can be tested
Luke Kenneth Casson Leighton [Wed, 17 Nov 2021 14:45:47 +0000 (14:45 +0000)]
split up regression cases so that a single Rc=1 add can be tested

2 years agotruncate CR regspec_decode_write reg mask to 8 bit
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 19:13:24 +0000 (19:13 +0000)]
truncate CR regspec_decode_write reg mask to 8 bit

2 years agoargh, regspec_decode_write is supposed to return single-bit flags
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 16:26:18 +0000 (16:26 +0000)]
argh, regspec_decode_write is supposed to return single-bit flags
for indicating whether a register is to be written to or not.
the write data structures are a Data() record - with data and an ok.
the *entire* data structure was being returned, not the "ok" bit,
in many cases in regspec_decode_write.

2 years agoname of cr reg3 was numbered 2
Luke Kenneth Casson Leighton [Tue, 16 Nov 2021 15:13:47 +0000 (15:13 +0000)]
name of cr reg3 was numbered 2

3 years agoremove excess I from ternary-related names
Jacob Lifshay [Sat, 13 Nov 2021 00:36:40 +0000 (16:36 -0800)]
remove excess I from ternary-related names

3 years agochange ternaryi to correct register fields
Jacob Lifshay [Fri, 12 Nov 2021 01:32:47 +0000 (17:32 -0800)]
change ternaryi to correct register fields

3 years agoformat code
Jacob Lifshay [Fri, 12 Nov 2021 01:19:50 +0000 (17:19 -0800)]
format code

3 years agoformat code
Jacob Lifshay [Fri, 12 Nov 2021 00:44:57 +0000 (16:44 -0800)]
format code

3 years agoadd case-based expected results in addme alu_cases
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 11:30:03 +0000 (11:30 +0000)]
add case-based expected results in addme alu_cases
creates the expected results based on conditions in the choices and values

3 years agoinvert speedup (commenting-out) of tests
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 10:37:40 +0000 (10:37 +0000)]
invert speedup (commenting-out) of tests

3 years agosort out numbering on CRs in SimState
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 10:30:11 +0000 (10:30 +0000)]
sort out numbering on CRs in SimState

3 years agowhitespace
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 10:29:57 +0000 (10:29 +0000)]
whitespace

3 years agofix test API State.compare which was overwriting intregs and crregs
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 10:08:05 +0000 (10:08 +0000)]
fix test API State.compare which was overwriting intregs and crregs
-        for i, (self.intregs, s2.intregs) in enumerate(
+        for i, (intreg, intreg2) in enumerate(

3 years agohttps://bugs.libre-soc.org/show_bug.cgi?id=730#c27
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 09:44:32 +0000 (09:44 +0000)]
https://bugs.libre-soc.org/show_bug.cgi?id=730#c27
yep, the CR Field numbering has already been fixed so does not need
inverting with a 7-i

3 years agoadd unexpected result to see what happens
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 09:40:49 +0000 (09:40 +0000)]
add unexpected result to see what happens

3 years agouse append on expected state dump, not ideal but
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 09:40:33 +0000 (09:40 +0000)]
use append on expected state dump, not ideal but
gives multiple results

3 years agoadd core state to gtkw
Luke Kenneth Casson Leighton [Thu, 11 Nov 2021 09:26:54 +0000 (09:26 +0000)]
add core state to gtkw

3 years agoAdd expected state to case_addze for addze in alu_cases unit test
R Veera Kumar [Thu, 11 Nov 2021 05:39:12 +0000 (11:09 +0530)]
Add expected state to case_addze for addze in alu_cases unit test

Now for only addze opcode
Removed a not needed self.add_case line

3 years agoAdd expected state to case_1_regression for 'add' in alu_cases unit test
R Veera Kumar [Thu, 11 Nov 2021 04:22:13 +0000 (09:52 +0530)]
Add expected state to case_1_regression for 'add' in alu_cases unit test

3 years agoAdd expected state to case_1_regression for extsb in alu_cases unit test
R Veera Kumar [Thu, 11 Nov 2021 02:55:54 +0000 (08:25 +0530)]
Add expected state to case_1_regression for extsb in alu_cases unit test

3 years agoAdd expected state to case_1_regression for subf (2) in alu_cases unit test
R Veera Kumar [Thu, 11 Nov 2021 02:35:51 +0000 (08:05 +0530)]
Add expected state to case_1_regression for subf (2) in alu_cases unit test

3 years agoattempt to get gtkw simulator signals updated on WB MMU
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 19:51:14 +0000 (19:51 +0000)]
attempt to get gtkw simulator signals updated on WB MMU

3 years agoAdd expected state to case_1_regression for subf in alu_cases unit test
R Veera Kumar [Wed, 10 Nov 2021 19:37:03 +0000 (01:07 +0530)]
Add expected state to case_1_regression for subf in alu_cases unit test

3 years agoadd LDST msr_pr to gtkw debug
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 19:10:40 +0000 (19:10 +0000)]
add LDST msr_pr to gtkw debug

3 years agodisplay 64 bits of msr
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 19:07:46 +0000 (19:07 +0000)]
display 64 bits of msr

3 years agoadd MSR to ldst operand debug gtkw
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 19:05:49 +0000 (19:05 +0000)]
add MSR to ldst operand debug gtkw

3 years agoadd MSR to gtkw file for simulation output
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 18:43:25 +0000 (18:43 +0000)]
add MSR to gtkw file for simulation output

3 years agoadd RT as an option for ternary instruction as 3rd register input
Luke Kenneth Casson Leighton [Wed, 10 Nov 2021 14:53:04 +0000 (14:53 +0000)]
add RT as an option for ternary instruction as 3rd register input

3 years agoadd creation of 8 and 16 DCT butterfly diagrams
Luke Kenneth Casson Leighton [Thu, 28 Oct 2021 11:47:45 +0000 (12:47 +0100)]
add creation of 8 and 16 DCT butterfly diagrams

3 years agoforward mmu sprs
Tobias Platen [Tue, 9 Nov 2021 17:12:45 +0000 (18:12 +0100)]
forward mmu sprs

3 years agoAdd expected state to case_1_regression for extsw for alu_cases unit test
R Veera Kumar [Tue, 9 Nov 2021 13:53:46 +0000 (19:23 +0530)]
Add expected state to case_1_regression for extsw for alu_cases unit test

3 years agoadd ternaryi
Jacob Lifshay [Fri, 5 Nov 2021 23:10:35 +0000 (16:10 -0700)]
add ternaryi

3 years agoformat code
Jacob Lifshay [Fri, 5 Nov 2021 22:50:36 +0000 (15:50 -0700)]
format code

3 years agoformat code
Jacob Lifshay [Fri, 5 Nov 2021 22:46:29 +0000 (15:46 -0700)]
format code

3 years agoadd comment2 and unofficial fields to existing instructions
Jacob Lifshay [Fri, 5 Nov 2021 22:10:06 +0000 (15:10 -0700)]
add comment2 and unofficial fields to existing instructions

3 years agodcbz needs to go through ldst function unit
Tobias Platen [Thu, 4 Nov 2021 19:44:30 +0000 (20:44 +0100)]
dcbz needs to go through ldst function unit

3 years agocaller.py: Fix ISACaller modifying test state
klehman [Thu, 4 Nov 2021 13:45:34 +0000 (09:45 -0400)]
caller.py: Fix ISACaller modifying test state

3 years agostate.py: Fix expected dump for cr regs
klehman [Thu, 28 Oct 2021 02:53:08 +0000 (22:53 -0400)]
state.py: Fix expected dump for cr regs

3 years agospacing fix
klehman [Mon, 25 Oct 2021 20:46:44 +0000 (16:46 -0400)]
spacing fix

3 years agotests now dump into caller dirs
klehman [Mon, 25 Oct 2021 20:19:16 +0000 (16:19 -0400)]
tests now dump into caller dirs

3 years agoget file name from stack, add in TestCase
klehman [Mon, 25 Oct 2021 19:59:54 +0000 (15:59 -0400)]
get file name from stack, add in TestCase

3 years agotmp creation/string formatting
klehman [Mon, 25 Oct 2021 14:13:39 +0000 (10:13 -0400)]
tmp creation/string formatting

3 years agoadded dump_state_tofile for code creation
klehman [Mon, 25 Oct 2021 12:41:25 +0000 (08:41 -0400)]
added dump_state_tofile for code creation

3 years agoAdd a new test caller for ALU based on shift_rot test caller
R Veera Kumar [Sat, 23 Oct 2021 05:19:50 +0000 (10:49 +0530)]
Add a new test caller for ALU based on shift_rot test caller

3 years agofixedlogical: simplify extsw
Dmitry Selyutin [Sat, 2 Oct 2021 09:23:42 +0000 (09:23 +0000)]
fixedlogical: simplify extsw

3 years agofixedlogical: simplify extsh
Dmitry Selyutin [Sat, 2 Oct 2021 09:23:22 +0000 (09:23 +0000)]
fixedlogical: simplify extsh

3 years agofixedlogical: simplify extsb
Dmitry Selyutin [Sat, 2 Oct 2021 09:23:02 +0000 (09:23 +0000)]
fixedlogical: simplify extsb

3 years agodecoder/helpers: introduce EXTSXL helper
Dmitry Selyutin [Sat, 2 Oct 2021 09:18:34 +0000 (09:18 +0000)]
decoder/helpers: introduce EXTSXL helper

https://libre-soc.org/openpower/sv/svp64/extsxl

3 years agodecoder/helpers: simplify XLCASTU
Dmitry Selyutin [Sat, 2 Oct 2021 09:12:13 +0000 (09:12 +0000)]
decoder/helpers: simplify XLCASTU

3 years agocorrections to EXTSXL 0x000000090000093 table for extsb, bit 7 needs
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 20:14:30 +0000 (21:14 +0100)]
corrections to EXTSXL 0x000000090000093 table for extsb, bit 7 needs
propagating through for XLEN=16/32/64