Cleaned up comments

removed unused library and already present compiler flag

Added Monitor class that can monitor all changes in a Design or in a Module

added destructors for wires and cells

removed debug output

commands can now be run on arbitrary designs, not only on the active one

multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues

Introduced namespace and removed class-prefixes to increase readability

changed references from hash-ids to IdString names

added wrappers for Design, Modules, Cells and Wires

added ENABLE_PYTHON option in build environment

Add simplified "read" command, enable extnets in implicit Verific import

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of github.com:YosysHQ/yosys

Add automatic verific import in hierarchy command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #572 from q3k/q3k/fix-protobuf-build

Fix protobuf build

Fix protobuf build

Merge pull request #571 from q3k/q3k/protobuf-backend

Add Protobuf backend

Add Protobuf backend

Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>

Be slightly less aggressive in "deminout" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #570 from edcote/patch-4

Include module name for area summary stats

Include module name for area summary stats

The PR prints the name of the module when displaying the final area count.

Pros:
- Easier for the user to `grep` for area information about a specific module

Cons:
- Arguably more verbose, less "pretty" than author desires

Verification:
~~~~
30c30
<    Chip area for this module: 20616.349000
---
>    Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
<    Chip area for this module: 88.697700
---
>    Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
<    Chip area for this module: 20705.046700
---
>    Chip area for top module '\picorv32_axi': 20705.046700
~~~~

Bugfix in liberty parser (as suggested by aiju in #569)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "synth_ice40 -json"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix ice40_opt for cases where a port is connected to a signal with width != 1

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #561 from udif/pr_skip_typo

Fixed typo (sikp -> skip)

Fixed typo (sikp -> skip)

Add (* gclk *) attribute support

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add setundef -anyseq / -anyconst support to -undriven mode

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "setundef -anyconst"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bugfix in handling of array instances with empty ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update examples/cmos/counter.ys to use "synth" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Make -nordff the default in "prep"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update ABC to git rev 6df1396

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Disable memory_dff for initialized FFs

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add some cleanup code to memory_nordff

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add comment to VIPER #13453 work-around

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix Verific handling of single-bit anyseq/anyconst wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix verific handling of anyconst/anyseq attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #454 from rqou/emscripten-and-abc

Add option to statically link abc; emscripten fixes

Force abc to align memory to 8 bytes

Apparently abc has a memory pool implementation that by default returns
memory that is unaligned. There is a workaround in the abc makefile that
uses uname to look for "arm" specifically and then sets the alignment.
However, ARM is not the only platform that requires proper alignment
(e.g. emscripten does too). For now, pessimistically force the alignment
for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten
despite being approximately a 32-bit platform).

Modify emscripten main to mount nodefs and to run arg as a script

Force abc to be linked statically and without threads in emscripten

Fix infinite loop in abc command under emscripten

Fix reading techlibs under emscripten

Add options to disable abc's usage of pthreads and readline

Add an option to statically link abc into yosys

This is currently incomplete because the output filter no longer works.

Makefile: Make abc always use stdint.h

Merge pull request #550 from jimparis/yosys-upstream

Support SystemVerilog `` extension for macros

Merge pull request #551 from olofk/ice40_cells_sim_ports

Avoid mixing module port declaration styles in ice40 cells_sim.v

Avoid mixing module port declaration styles in ice40 cells_sim.v

The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.

Support SystemVerilog `` extension for macros

Skip spaces around macro arguments

Fix handling of anyconst/anyseq attrs in VHDL code via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Remove mercurial from build instructions

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix iopadmap for loops between tristate IO buffers

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix iopadmap for cases where IO pins already have buffers on them

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Some cleanups in setundef.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Use $(OS) in makefile to check for Darwin

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #505 from thefallenidealist/FreeBSD_build

FreeBSD build

Add "#ifdef __FreeBSD__"

(Re-commit e3575a8 with corrected author field)

Revert "Add "#ifdef __FreeBSD__""

This reverts commit e3575a86c525f2511902e7022893c3923ba8093e.

Also interpret '&' in liberty functions

Add optimization of tristate buffer with constant control input

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "hierarchy -simcheck"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

update README

autotest.sh: Change from /bin/bash to /usr/bin/env bash

This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).

Enable building on FreeBSD

Further improve handling of zero-length SVA consecutive repetition

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of zero-length SVA consecutive repetition

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "#ifdef __FreeBSD__"

Add ABC FAQ to "help abc"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "yosys -e regex" for turning warnings into errors

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #537 from mithro/yosys-vpr

Improving Yosys when used with VPR

Replace -ignore_redef with -[no]overwrite

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Support more character literals

Update ABC to git rev f23ea8e

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "synth_intel --noiopads"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add $dlatch support to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improving vpr output support.

 * Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.

synth_ice40: Rework the vpr blif output slightly.

Add "synth_ice40 -nodffe"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "write_blif -inames -iattr"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add statement labels for immediate assertions

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Allow "property" in immediate assertions

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve Makefile error handling for when abc/ is a hg working copy

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add PRIM_HDL_ASSERTION support to Verific importer

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of $global_clocking in Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add documentation for anyconst/anyseq/allconst/allseq attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add read_verilog anyseq/anyconst/allseq/allconst attribute support

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add Verific anyseq/anyconst/allseq/allconst attribute support

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "verific -autocover"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #530 from makaimann/set-ram-flags

Set RAM runtime flags for Verific frontend

Set RAM runtime flags for Verific frontend

Added missing dont_use handling for SR FFs to dfflibmap

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Create issue_template.md

Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constants

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fixed -stbv handling in SMT2 back-end

Merge pull request #522 from c60k28/master

Fixed broken Quartus backend on dffeas init value, and other updates.

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value  for the POWER_UP parameter. Fixed and tested Cyclone V device