ir3: fixup for new nir_foreach_block()

nir/lower_double_ops: fixup for new nir_foreach_block()

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir/lower_double_pack: fixup for new nir_foreach_block()

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir/gather_info: fixup for new foreach_block()

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir/lower_two_sided_color: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir/lower_tex: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir/lower_outputs_to_temporaries: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Switch to scalar TCS by default.

Normally, we expect SIMD8 shaders to be more instructions than SIMD4x2
shaders, as it takes four instructions to operate on a vec4, rather than
a single instruction.  However, the benefit is that it can process 8
objects per shader thread instead of 2.

Surprisingly, the shader-db statistics show an improvement in both
instruction and cycle counts:

Synmark: -31.25% instructions, -29.27% cycles, 0 hurt.
Tessmark: -36.92% instructions, -37.81% cycles, 0 hurt.
Unigine Heaven: -3.42% instructions, -17.95% cycles, 0 hurt.
Shadow of Mordor:
   +13.24% instructions (26 with fewer instructions, 45 with more),
   -5.23% cycles (44 with fewer cycles, 27 with more cycles).

Presumably, this is because the SIMD8 URB messages are a much more
natural fit than the SIMD4x2 URB messages - there's a ton less header
setup.

I benchmarked Shadow of Mordor and Unigine Heaven on my Skylake GT3e,
and the performance seems to be the same or increase ever so slightly
(< 1 FPS difference).  So I believe it's strictly superior.

There's also a lot more optimization potential we can do in scalar mode.

This will also help us finish fp64 support, as scalar support is going
to land much sooner than vec4-mode support.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Optimize out stores of undefs.

There are a couple of cycle count changes in shader-db, but it's
basically a wash.

However, with the Broadwell scalar TCS backend enabled, many
Shadow of Mordor shaders benefit from this patch.  Because we don't
batch up output writes for TCS, vec4 outputs might not have all
components defined.  Many output writes have a value of undef,
which is useless.

With scalar TCS, stats for tessellation shaders on Broadwell:

total instructions in shared programs: 1283000 -> 1280444 (-0.20%)
instructions in affected programs: 34302 -> 31746 (-7.45%)
helped: 71
HURT: 0

total cycles in shared programs: 10798768 -> 10780682 (-0.17%)
cycles in affected programs: 158004 -> 139918 (-11.45%)
helped: 71
HURT: 0

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Replace vecN(undef, undef, ...) with a single undef.

shader-db statistics on Broadwell:

total instructions in shared programs: 8963409 -> 8962455 (-0.01%)
instructions in affected programs: 60858 -> 59904 (-1.57%)
helped: 318
HURT: 0

total cycles in shared programs: 71408022 -> 71406276 (-0.00%)
cycles in affected programs: 398416 -> 396670 (-0.44%)
helped: 199
HURT: 51

GAINED: 1

The only shaders affected were in Dota 2 Reborn.

It also sets up for the next optimization.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Rename opt_undef_alu to opt_undef_csel; update comments.

This better reflects what it does.  I plan to add other ALU
optimizations as well, so the old name would be confusing.

In preparation for that, also move the file comments about csels
above the opt_undef_csel function, and delete the ones about there
not being other optimizations.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Rework passthrough TCS checks.

According to Timothy, using program_string_id == 0 to identify the
passthrough TCS is going to be problematic for his shader cache work.

So, change it to strcmp() the name at visitor creation time.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

swr: [rasterizer core] Faster modulo operator in ProcessVerts

Avoid % operator, since we know that curVertex is always incrementing.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Small warning cleanup

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Add SWR_ASSUME / SWR_ASSUME_ASSERT macros

Fix static code analysis errors found by coverity on Linux

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Miscellaneous backend changes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Add support for X24_TYPELESS_G8_UINT format

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer jitter] Fix printing bugs for tracing.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer memory] Add missing store tiles function

Storing color hot tile to 8bit w-major stencil format.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer jitter] Add asserts for supported formats in fetch shader

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Fix thread allocation

Fix windows in 32-bit mode when hyperthreading is disabled on Xeons.

Some support for asymmetric processor topologies.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Fix threadviz support in buckets

Need to do lazy eval of the threadviz knob since order of globals
is undefined.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Whitespace cleanup and misc changes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radeonsi: mark descriptor loads as using dynamically uniform indices

This tells LLVM to always use SMEM loads for descriptors. It fixes a
regression in piglit's arb_shader_storage_buffer_object/execution/indirect.shader_test
that was caused by LLVM r268259 (but the proper fix is really here in Mesa).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965/fs: Don't follow pow with an instruction with two dest regs.

Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
Gen >= 8 platforms.

Evidently that commit allowed the scheduler to make different choices
that somehow finally ran afoul of a hardware bug in which POW and FDIV
instructions may not be followed by an instruction with two destination
registers (including compressed instructions). I presume the conditions
are more complex than that, but the internal hardware bug report (BDWGFX
bug_de 1696294) does not contain much more information.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> [v1]
Tested-by: Mark Janes <mark.a.janes@intel.com> [v1]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

swr: Remove stall waiting for core query counters.

When gathering query results, swr_gather_stats was
unnecessarily stalling the entire pipeline.  Results are now
collected asynchronously, with a fence marking completion.

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>

mesa/ubo: add missing compute cases for ubo/atomic buffers

This fixes: GL43-CTS.compute_shader.resource-ubo

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/compute: drop pointless casts.

We already are a GLintptr, casting won't help.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: remove null check before free

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

freedreno: remove null check before free

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

nir: fix assert for wildcard pairs

The assert was null checking dest_arr_parent twice. The intention
seems to be to check both dest_ and src_.

Added in d3636da9

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

glapi: fix parameter type for GetSamplerParameterIuivEXT() in es_EXT.xml

The function returns GLuint, not GLfloat values.

v2: also fix the OES function

Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: include texture format in glGenerateMipmap error message

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

main: uses casts to silence some _mesa_debug() format warnings

Silences warnings with 32-bit Linux gcc builds and MinGW which doesn't
recognize the ‘t’ conversion character.

Reviewed-by: Sinclair Yeh <syeh@vmware.com>

docs: Mark GL_ARB_query_buffer_object as done for i965/hsw+

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Implement ARB_query_buffer_object for HSW+

v2:
 * Declare loop index variable at loop site (idr)
 * Make arrays of MI_MATH instructions 'static const' (idr)
 * Remove commented debug code (idr)
 * Updated comment in set_query_availability (Ken)
 * Replace switch with if/else in hsw_result_to_gpr0 (Ken)
 * Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on
   hsw and gen8 (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/gen6+: Add load register immediate helper functions

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/hsw+: Add support for copying a register

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6+: Add support for storing immediate data into a buffer

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add MI_MATH reg defs for HSW+

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add brw_store_register_mem32

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use offset instead of index in brw_store_register_mem64

This matches the byte based offset of brw_load_register_mem*.

The function is also moved into intel_batchbuffer.c like
brw_load_register_mem*.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r600,compute: create vtx buffer for text + rodata

Reserve buffer id 2

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

freedreno: allow ctx->draw_vbo to fail

Pretty much only happens if shader variant compile fails.  But in this
case, if we haven't emitted cmdstream, we don't want to set needs_flush.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: move shader-stage dirty bits to global dirty flag

This was always a bit overly complicated, and had some issues (like
ctx->prog.dirty not getting reset at the end of the batch).  It also
required some special hacks to avoid resetting dirty state on binning
pass.  So just move it all into ctx->dirty (leaving some free bits
for future shader stages), and make FD_DIRTY_PROG just be the union
of all FD_SHADER_DIRTY_*.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: fix bogus offset for f32x24s8 stencil restore

fixes: $piglit/bin/fbo-clear-formats GL_ARB_depth_buffer_float

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: add some debug_asserts() to catch insane offsets

Ofc won't catch *all* faults, but at least helpful for catching offsets
which are completely bogus.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: deal with VS which do not write position

Fixes $piglit/bin/glsl-1.40-tf-no-position

a3xx may need similar?

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: remove a couple redundant is_flow()s

Now that the opc's encode the instruction category (making them unique)
we no longer need to check the category in addition to the opc.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: cp small negative integers too

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix # of registers

The instruction encoding allows for more registers, but at least on
a3xx/a4xx they don't actually exist.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: lower immeds to const

Helps reduce register pressure and instruction counts for immediates
that would otherwise require a mov into gpr.

total instructions in shared programs:          4455332 -> 4369297 (-1.93%)
total dwords in shared programs:                8807872 -> 8614432 (-2.20%)
total full registers used in shared programs:   263062 -> 250846 (-4.64%)
total half registers used in shader programs:   9845 -> 9845 (0.00%)
total const registers used in shared programs:  1029735 -> 1466993 (42.46%)

                 half       full      const      instr     dwords
    helped           0       10415           0       17861        5912
      hurt           0        1157       21458         947          33

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: add ir3_cp_ctx

Needed in next commit.. just split out to reduce noise.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

add REVIEWERS and get_reviewer.pl script

Copied from linux kernel (where it is called MAINTAINERS and
get_maintainer.pl), with minimal changes to script (to recognize
mesa src tree rather than linux kernel src tree, and to avoid
accidentaly CC'ing Linus Torvalds on mesa patches), and slimmed
down MAINTAINER file syntax to recognize that we don't really have
subsystem "maintainers" in the same sense as the linux kernel (ie. no
different mailing lists and git trees per subsystem).

The main point is to automate slapping on the correct CC's for patches
via git's --cc-cmd feature, more than anything else.

I didn't attempt to fully populate the REVIEWERS file, by a long shot.
This is an opt-in system and anyone else can add their own entries.

To utilize:

  git send-email --cc-cmd ./scripts/get_reviewer.pl ...

or to configure it to be the default:

  git config sendemail.cccmd ./scripts/get_reviewer.pl

Signed-off-by: Rob Clark <robclark@freedesktop.org>

nouveau/video: properly detect the decoder class for availability checks

The kernel is now more strict with the class ids it exposes, so we need
to check the G98 and MCP89 classes as well as the GT215 class. This
effectively caused us to decide there were no decoding capabilities on
newer kernel for VP3 chips.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95251
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2" <mesa-stable@lists.freedesktop.org>

i965: Delete stale perf_debug().

MOCS for 3DSTATE_SO_BUFFER has existed for ages.

i965: Silence unused variable warning

I added this when deleting some unnecessary code in a rebase.

mesa/main: handle double uniform matrices properly

When computing the offset in the uniform storage table, take into account
the size multiplier so double precision matrices are handled correctly.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Separate 32 and 64-bit fmod lowering

Split 32-bit and 64-bit fmod lowering as the drivers might need to
lower them separately inside NIR depending on the HW support.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

nir/lower_double_ops: lower mod()

There are rounding errors with the division in i965 that affect
the mod(x,y) result when x = N * y. Instead of returning '0' it
was returning 'y'.

This lowering pass fixes those cases.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Define GEN_GE/GEN_LE macros in terms of GEN_LT.

GEN_LT has a straightforward implementation on which we can build the
GEN_GE and GEN_LE macros.

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add disassembler support for remaining opcodes.

For opcodes that changed meaning on different generations, we store a
pointer to a secondary table and the table's size in a tagged union in
place of the mnemonic and number of sources.

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Make opcode_descs and gen_from_devinfo() static.

The previous commit replaced direct uses of opcode_descs with calls to
the wrapper function, which should be the only method of accessing
opcode_descs's data. As a result gen_from_devinfo() can also be made
static.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Actually check whether the opcode is supported.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Merge inst_info and opcode_desc tables.

I merged opcode_desc into inst_info (instead of the other way around)
because inst_info was sorted by opcode number.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move inst_info from brw_eu_validate.c to brw_eu.c.

Drop the uses of 'enum gen' to a plain int, so that we don't have to
expose the bitfield definitions and GEN_GE/GEN_LE macros to other users
of brw_eu.h. As a result, s/.gen/.gens/ to avoid confusion with
devinfo->gen.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/disasm: Wrap opcode_desc look-up in a function.

The function takes a device info struct as argument in addition to the
opcode number in order to disambiguate between multiple opcode_desc
entries for different instructions with the same opcode number.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v1]
[v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it
               there in a later patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v2]
[v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs)
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Pass devinfo pointer to is_3src() helpers.

This is not strictly required for the following changes because none
of the three-source opcodes we support at the moment in the compiler
back-end has been removed or redefined, but that's likely to change in
the future.  In any case having hardware instructions specified as a
pair of hardware device and opcode number explicitly in all cases will
simplify the opcode look-up interface introduced in a subsequent
commit, since the opcode number alone is in general ambiguous.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass devinfo pointer to brw_instruction_name().

A future series will implement support for an instruction that happens
to have the same opcode number as another instruction we support
already on a disjoint set of hardware generations.  In order to
disambiguate which instruction it is brw_instruction_name() will need
some way to find out which device we are generating code for.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Write a scalar TCS backend that runs in SINGLE_PATCH mode.

Unlike most shader stages, the Hull Shader hardware makes us explicitly
tell it how many threads to dispatch and manually configure the channel
mask.  One perk of this is that we have a lot of flexibility - we can
run it in either SIMD4x2 or SIMD8 mode.

Treating it as SIMD8 means that shaders with 8 or fewer output vertices
(which is overwhemingly the common case) can be handled by a single
thread.  This has several intriguing properties:

- Accessing input arrays with gl_InvocationID as the index is a simple
  SIMD8 URB read with g1 as the header.  No indirect addressing required.
- Barriers are no-ops.
- We could potentially do output shadowing to combine writes, as the
  concurrency concerns are gone.  (We don't do this yet, though.)

v2: Drop first_non_payload_grf change, as it was always adding 0
    (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Rework the TCS passthrough shader to use NIR.

I'm about to implement a scalar TCS backend, and I'd rather not
duplicate all of this code there.

One change is that we now write the tessellation levels from all
TCS threads, rather than just the first.  This is pretty harmless,
and was easier.  The IF/ENDIF needed for that are gone; otherwise
the generated code is basically identical.

I chose to emit load/store intrinsics directly because it was easier.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

gallium/util: change assertion to conditional in util_bitmask_destroy()

If we fail to create a context in the VMware driver we call this function
unconditionally to free a bunch of bit vectors.  Instead of asserting on
a null pointer, just no-op.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

cso: null-out previously bound sampler states

If, for example, we previously had 2 sampler states bound and now we
are binding one, we'd leave the second sampler state unchanged.
This change nulls-out the second sampler state in this situation.
We're already doing the same thing for sampler views.

This silences an occasional warning issued by the VMware driver when
the number of sampler views and sampler states disagreed.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

svga: try to flag surfaces for sampling, in addition to rendering

This silences some warnings when we try to sample from surfaces that were
created for drawing, such as when blitting from one of the framebuffer
surfaces.  We were already doing the opposite situation (adding a bind
flag for rendering to surfaces declared as texture sources).

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: fix copying non-zero layers of 1D array textures

Like cube maps, we need to convert the z information to a layer index.
Also rename the *_face vars to *_face_layer to make things a little more
understandable.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: clean up svga_pipe_blit.c

Remove dead code.  Fix formatting.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

rbug: s/Elements/ARRAY_SIZE/

Signed-off-by: Brian Paul <brianp@vmware.com>

freedreno: s/Elements/ARRAY_SIZE/

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

trace: s/Elements/ARRAY_SIZE/

Signed-off-by: Brian Paul <brianp@vmware.com>

ilo: s/Elements/ARRAY_SIZE/

Signed-off-by: Brian Paul <brianp@vmware.com>

i915g: s/Elements/ARRAY_SIZE/

Signed-off-by: Brian Paul <brianp@vmware.com>

nvc0: compute a percentage for metric-achieved_occupancy

metric-issue_slot_utilization and metric-branch_efficiency are already
computed as percentages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

nvc0: display some performance metrics with a percentage

This makes more sense for them.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

nvc0: store the driver query type for performance metrics

This will allow to use percentages for some metrics because the Gallium
HUD doesn't allow to display floating point numbers and 0 is printed
instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

nvc0: fix exposing of metric-issue_slots for SM21/SM30

This is most likely a copy-paste error when I reworked this area few
weeks ago. For SM20, metric-issue_slots is equal to inst_issued because
there is only one pipeline, so the metric is not exposed there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reported-by: Karol Herbst <nouveau@karolherbst.de>

mesa/objectlabel: handle NULL src string

This prevents a crash when a NULL src is passed with a non-NULL length.

fixes: dEQP-GLES31.functional.debug.object_labels.query_length_only
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95252

Signed-off-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

glsl: subroutine types cannot be used in constructors.

This fixes two of the cases in
GL43-CTS.shader_subroutine.subroutines_not_allowed_as_variables_constructors_and_argument_or_return_types

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glsl: resource is a reserved keyword in GLSL 4.20 as well

resource just appears in GLSL 4.20 without any fanfare.

Fixes GL43-CTX.CommonBugs.CommonBug_ReservedNames

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium,utils: Fix trivial sign compare warnings

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jakob Sinclair <sinclair.jakob@openmailbox.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

anv: fix hang during generation of dev_icd.json.

Fixes: b370ec7c76d ("anv: tweak the %.json rule")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

swrast: Add texfetch_funcs entries for astc 3d formats

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Enable translation between astc 3d gl formats and mesa formats

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Handle astc 3d formats in _mesa_get_compressed_formats()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Handle astc 3d formats in _mesa_base_tex_format()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Account for astc 3d formats in _mesa_is_astc_format()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add a helper function is_astc_3d_format()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add the missing defines for GL_OES_texture_compression_astc

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Align the values of #define's in glheader.h

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add OES_texture_compression_astc to extension table and gl_extensions

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add entries for astc 3d formats initializing struct gl_format_info

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>