yosys.git
5 years agoMerge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
Eddie Hung [Tue, 16 Jul 2019 15:53:47 +0000 (08:53 -0700)]
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters

abc9: push inverters driving box inputs (comb outputs) through $lut soft logic

5 years agoMerge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
Eddie Hung [Tue, 16 Jul 2019 15:52:14 +0000 (08:52 -0700)]
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix

abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box

5 years agoMerge pull request #1200 from mmicko/fix_typo_liberty_cc
Clifford Wolf [Tue, 16 Jul 2019 13:27:25 +0000 (15:27 +0200)]
Merge pull request #1200 from mmicko/fix_typo_liberty_cc

Fix typo, double "of"

5 years agoMerge pull request #1199 from mmicko/extract_fa_fix
Clifford Wolf [Tue, 16 Jul 2019 13:27:09 +0000 (15:27 +0200)]
Merge pull request #1199 from mmicko/extract_fa_fix

Fix check logic in extract_fa

5 years agoFix typo, double "of"
Miodrag Milanovic [Tue, 16 Jul 2019 09:03:30 +0000 (11:03 +0200)]
Fix typo, double "of"

5 years agoFix check logic in extract_fa
Miodrag Milanovic [Tue, 16 Jul 2019 08:35:18 +0000 (10:35 +0200)]
Fix check logic in extract_fa

5 years agoMerge pull request #1196 from YosysHQ/eddie/fix1178
Eddie Hung [Mon, 15 Jul 2019 20:31:08 +0000 (13:31 -0700)]
Merge pull request #1196 from YosysHQ/eddie/fix1178

Fix different synth results between with and without debug output "-g"

5 years ago$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
Eddie Hung [Mon, 15 Jul 2019 19:03:51 +0000 (12:03 -0700)]
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

5 years agoMerge pull request #1189 from YosysHQ/eddie/fix1151
Clifford Wolf [Mon, 15 Jul 2019 18:06:35 +0000 (20:06 +0200)]
Merge pull request #1189 from YosysHQ/eddie/fix1151

Error out if enable > dbits in memory_bram file

5 years agoMerge pull request #1190 from YosysHQ/eddie/fix_1099
Clifford Wolf [Mon, 15 Jul 2019 18:05:56 +0000 (20:05 +0200)]
Merge pull request #1190 from YosysHQ/eddie/fix_1099

extract_fa to return nothing more gracefully

5 years agoMerge pull request #1191 from whitequark/opt_lut-log_debug
Clifford Wolf [Mon, 15 Jul 2019 18:04:00 +0000 (20:04 +0200)]
Merge pull request #1191 from whitequark/opt_lut-log_debug

Make opt_lut less chatty

5 years agoMerge pull request #1195 from Roman-Parise/master
Clifford Wolf [Mon, 15 Jul 2019 18:01:38 +0000 (20:01 +0200)]
Merge pull request #1195 from Roman-Parise/master

Updated FreeBSD dependencies in README.md

5 years agoMerge pull request #1197 from nakengelhardt/handle-setrlimit-fail
Clifford Wolf [Mon, 15 Jul 2019 17:42:11 +0000 (19:42 +0200)]
Merge pull request #1197 from nakengelhardt/handle-setrlimit-fail

smt: handle failure of setrlimit syscall

5 years agoRevert "Add log_checkpoint function and use it in opt_muxtree"
Eddie Hung [Mon, 15 Jul 2019 15:35:48 +0000 (08:35 -0700)]
Revert "Add log_checkpoint function and use it in opt_muxtree"

This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574.

5 years agosmt: handle failure of setrlimit syscall
N. Engelhardt [Mon, 15 Jul 2019 15:33:18 +0000 (23:33 +0800)]
smt: handle failure of setrlimit syscall

5 years agoRevert "Fix first divergence in #1178"
Eddie Hung [Mon, 15 Jul 2019 15:31:26 +0000 (08:31 -0700)]
Revert "Fix first divergence in #1178"

This reverts commit 1122a2e0671ed00b7c03658f5012e34df12f26de.

5 years agoMerge branch 'master' into eddie/fix1178
Eddie Hung [Mon, 15 Jul 2019 15:23:01 +0000 (08:23 -0700)]
Merge branch 'master' into eddie/fix1178

5 years agoRedesign log_id_cache so that it doesn't keep IdString instances referenced, fixes...
Clifford Wolf [Mon, 15 Jul 2019 15:10:42 +0000 (17:10 +0200)]
Redesign log_id_cache so that it doesn't keep IdString instances referenced, fixes #1178

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd log_checkpoint function and use it in opt_muxtree
Clifford Wolf [Mon, 15 Jul 2019 10:12:21 +0000 (12:12 +0200)]
Add log_checkpoint function and use it in opt_muxtree

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1194 from cr1901/miss-semi
Eddie Hung [Sun, 14 Jul 2019 20:36:34 +0000 (13:36 -0700)]
Merge pull request #1194 from cr1901/miss-semi

Fix missing semicolon in Windows-specific code in aigerparse.cc.

5 years agoFix missing semicolon in Windows-specific code in aigerparse.cc.
William D. Jones [Sun, 14 Jul 2019 15:57:08 +0000 (11:57 -0400)]
Fix missing semicolon in Windows-specific code in aigerparse.cc.

Signed-off-by: William D. Jones <thor0505@comcast.net>
5 years agoUpdated FreeBSD dependencies in README.md
Roman-Parise [Sun, 14 Jul 2019 16:25:07 +0000 (09:25 -0700)]
Updated FreeBSD dependencies in README.md

5 years agoopt_lut: make less chatty.
whitequark [Sat, 13 Jul 2019 16:49:56 +0000 (16:49 +0000)]
opt_lut: make less chatty.

5 years agoIf ConstEval fails do not log_abort() but return gracefully
Eddie Hung [Sat, 13 Jul 2019 11:13:57 +0000 (04:13 -0700)]
If ConstEval fails do not log_abort() but return gracefully

5 years agoError out if enable > dbits
Eddie Hung [Sat, 13 Jul 2019 10:39:23 +0000 (03:39 -0700)]
Error out if enable > dbits

5 years agoice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
Eddie Hung [Sat, 13 Jul 2019 08:11:00 +0000 (01:11 -0700)]
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT

5 years agoAdd comment
Eddie Hung [Sat, 13 Jul 2019 07:52:21 +0000 (00:52 -0700)]
Add comment

5 years agoUpdate test with more accurate LUT mask
Eddie Hung [Sat, 13 Jul 2019 04:00:13 +0000 (21:00 -0700)]
Update test with more accurate LUT mask

5 years agoduplicate -> clone
Eddie Hung [Sat, 13 Jul 2019 02:33:02 +0000 (19:33 -0700)]
duplicate -> clone

5 years agoMore cleanup
Eddie Hung [Sat, 13 Jul 2019 02:21:03 +0000 (19:21 -0700)]
More cleanup

5 years agoCleanup
Eddie Hung [Sat, 13 Jul 2019 02:17:32 +0000 (19:17 -0700)]
Cleanup

5 years agoCleanup
Eddie Hung [Fri, 12 Jul 2019 23:06:14 +0000 (16:06 -0700)]
Cleanup

5 years agoCleanup
Eddie Hung [Fri, 12 Jul 2019 23:01:11 +0000 (16:01 -0700)]
Cleanup

5 years agoMore cleanup
Eddie Hung [Fri, 12 Jul 2019 22:43:39 +0000 (15:43 -0700)]
More cleanup

5 years agoCleanup
Eddie Hung [Fri, 12 Jul 2019 22:41:06 +0000 (15:41 -0700)]
Cleanup

5 years agoCleanup
Eddie Hung [Fri, 12 Jul 2019 22:31:02 +0000 (15:31 -0700)]
Cleanup

5 years agoCleanup
Eddie Hung [Fri, 12 Jul 2019 22:29:04 +0000 (15:29 -0700)]
Cleanup

5 years agoDo not double count cells in abc
Eddie Hung [Fri, 12 Jul 2019 15:22:26 +0000 (08:22 -0700)]
Do not double count cells in abc

5 years agoMerge pull request #1183 from whitequark/ice40-always-relut
Clifford Wolf [Fri, 12 Jul 2019 08:48:00 +0000 (10:48 +0200)]
Merge pull request #1183 from whitequark/ice40-always-relut

synth_ice40: switch -relut to be always on

5 years agoUse Const::from_string() not its constructor...
Eddie Hung [Fri, 12 Jul 2019 08:32:10 +0000 (01:32 -0700)]
Use Const::from_string() not its constructor...

5 years agoOff by one
Eddie Hung [Fri, 12 Jul 2019 08:17:53 +0000 (01:17 -0700)]
Off by one

5 years agoFix spacing
Eddie Hung [Fri, 12 Jul 2019 08:15:22 +0000 (01:15 -0700)]
Fix spacing

5 years agoRemove double push
Eddie Hung [Fri, 12 Jul 2019 08:08:48 +0000 (01:08 -0700)]
Remove double push

5 years agoMap to and from this box if -abc9
Eddie Hung [Fri, 12 Jul 2019 07:53:01 +0000 (00:53 -0700)]
Map to and from this box if -abc9

5 years agoice40_opt to handle this box and opt back to SB_LUT4
Eddie Hung [Fri, 12 Jul 2019 07:52:31 +0000 (00:52 -0700)]
ice40_opt to handle this box and opt back to SB_LUT4

5 years agoAdd new box to cells_sim.v
Eddie Hung [Fri, 12 Jul 2019 07:52:19 +0000 (00:52 -0700)]
Add new box to cells_sim.v

5 years ago_ABC macro will map and unmap to this new box
Eddie Hung [Fri, 12 Jul 2019 07:51:37 +0000 (00:51 -0700)]
_ABC macro will map and unmap to this new box

5 years agoCombine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
Eddie Hung [Fri, 12 Jul 2019 07:50:42 +0000 (00:50 -0700)]
Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box

5 years agosynth_ice40: switch -relut to be always on.
whitequark [Thu, 11 Jul 2019 10:46:30 +0000 (10:46 +0000)]
synth_ice40: switch -relut to be always on.

5 years agosynth_ice40: fix help text typo. NFC.
whitequark [Thu, 11 Jul 2019 10:46:45 +0000 (10:46 +0000)]
synth_ice40: fix help text typo. NFC.

5 years agoMerge pull request #1182 from koriakin/xc6s-bram
Eddie Hung [Thu, 11 Jul 2019 19:55:35 +0000 (12:55 -0700)]
Merge pull request #1182 from koriakin/xc6s-bram

synth_xilinx: Initial Spartan 6 block RAM inference support.

5 years agoMerge pull request #1185 from koriakin/xc-ff-init-vals
Eddie Hung [Thu, 11 Jul 2019 19:55:14 +0000 (12:55 -0700)]
Merge pull request #1185 from koriakin/xc-ff-init-vals

xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.

5 years agoxilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
Marcin Kościelnicki [Thu, 11 Jul 2019 19:13:12 +0000 (21:13 +0200)]
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.

5 years agoEnable &mfs for abc9, even if it only currently works for ice40
Eddie Hung [Thu, 11 Jul 2019 15:49:06 +0000 (08:49 -0700)]
Enable &mfs for abc9, even if it only currently works for ice40

5 years agosynth_xilinx: Initial Spartan 6 block RAM inference support.
Marcin Kościelnicki [Tue, 2 Jul 2019 12:28:35 +0000 (14:28 +0200)]
synth_xilinx: Initial Spartan 6 block RAM inference support.

5 years agoMerge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
Clifford Wolf [Thu, 11 Jul 2019 05:25:52 +0000 (07:25 +0200)]
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark

write_verilog: write RTLIL::Sa aka - as Verilog ?

5 years agoMerge pull request #1179 from whitequark/attrmap-proc
Clifford Wolf [Thu, 11 Jul 2019 05:23:28 +0000 (07:23 +0200)]
Merge pull request #1179 from whitequark/attrmap-proc

attrmap: also consider process, switch and case attributes

5 years agoMerge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Eddie Hung [Wed, 10 Jul 2019 21:38:13 +0000 (14:38 -0700)]
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime

Error out if -abc9 and -retime specified

5 years agoMerge pull request #1148 from YosysHQ/xc7mux
Eddie Hung [Wed, 10 Jul 2019 21:38:00 +0000 (14:38 -0700)]
Merge pull request #1148 from YosysHQ/xc7mux

synth_xilinx to infer wide multiplexers using new '-widemux <min>' option

5 years agoError out if -abc9 and -retime specified
Eddie Hung [Wed, 10 Jul 2019 19:47:48 +0000 (12:47 -0700)]
Error out if -abc9 and -retime specified

5 years agoAdd some spacing
Eddie Hung [Wed, 10 Jul 2019 19:32:33 +0000 (12:32 -0700)]
Add some spacing

5 years agoAdd some ASCII art explaining mux decomposition
Eddie Hung [Wed, 10 Jul 2019 19:20:04 +0000 (12:20 -0700)]
Add some ASCII art explaining mux decomposition

5 years agoattrmap: also consider process, switch and case attributes.
whitequark [Wed, 10 Jul 2019 12:28:32 +0000 (12:28 +0000)]
attrmap: also consider process, switch and case attributes.

5 years agoMerge pull request #1177 from YosysHQ/clifford/async
Clifford Wolf [Wed, 10 Jul 2019 06:48:20 +0000 (08:48 +0200)]
Merge pull request #1177 from YosysHQ/clifford/async

Fix clk2fflogic adff reset semantic to negative hold time on reset

5 years agoCall muxpack and pmux2shiftx before cmp2lut
Eddie Hung [Wed, 10 Jul 2019 04:26:38 +0000 (21:26 -0700)]
Call muxpack and pmux2shiftx before cmp2lut

5 years agoFix first divergence in #1178
Eddie Hung [Tue, 9 Jul 2019 22:49:16 +0000 (15:49 -0700)]
Fix first divergence in #1178

5 years agoRestore opt_clean back to original place
Eddie Hung [Tue, 9 Jul 2019 21:29:58 +0000 (14:29 -0700)]
Restore opt_clean back to original place

5 years agoRestore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
Eddie Hung [Tue, 9 Jul 2019 21:28:54 +0000 (14:28 -0700)]
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6

5 years agosynth_ecp5: Fix typo in copyright header
David Shah [Tue, 9 Jul 2019 21:26:10 +0000 (22:26 +0100)]
synth_ecp5: Fix typo in copyright header

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1174 from YosysHQ/eddie/fix1173
Clifford Wolf [Tue, 9 Jul 2019 20:59:51 +0000 (22:59 +0200)]
Merge pull request #1174 from YosysHQ/eddie/fix1173

Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero

5 years agoMerge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
Clifford Wolf [Tue, 9 Jul 2019 20:51:25 +0000 (22:51 +0200)]
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position

write_verilog: fix placement of case attributes

5 years agoFix tests/various/async FFL test
Clifford Wolf [Tue, 9 Jul 2019 20:44:39 +0000 (22:44 +0200)]
Fix tests/various/async FFL test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove tests/various/async, disable failing ffl test
Clifford Wolf [Tue, 9 Jul 2019 20:21:25 +0000 (22:21 +0200)]
Improve tests/various/async, disable failing ffl test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoExtend using A[1] to preserve don't care
Eddie Hung [Tue, 9 Jul 2019 19:35:41 +0000 (12:35 -0700)]
Extend using A[1] to preserve don't care

5 years agoMerge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc
Eddie Hung [Tue, 9 Jul 2019 19:19:40 +0000 (12:19 -0700)]
Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc

Revert "Add "synth -keepdc" option"

5 years agoMerge remote-tracking branch 'origin/eddie/fix1173' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 19:16:33 +0000 (12:16 -0700)]
Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux

5 years agowrite_verilog: fix placement of case attributes. NFC.
whitequark [Tue, 9 Jul 2019 19:14:03 +0000 (19:14 +0000)]
write_verilog: fix placement of case attributes. NFC.

5 years agoIncrement _TECHMAP_BITS_CONNMAP_ by one since counting from zero
Eddie Hung [Tue, 9 Jul 2019 19:14:00 +0000 (12:14 -0700)]
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero

5 years agoAdd tests/various/async.{sh,v}
Clifford Wolf [Tue, 9 Jul 2019 18:58:59 +0000 (20:58 +0200)]
Add tests/various/async.{sh,v}

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove tests/various/run-test.sh
Clifford Wolf [Tue, 9 Jul 2019 18:58:28 +0000 (20:58 +0200)]
Improve tests/various/run-test.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd tests/simple_abc9/.gitignore
Clifford Wolf [Tue, 9 Jul 2019 18:58:01 +0000 (20:58 +0200)]
Add tests/simple_abc9/.gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agowrite_verilog: write RTLIL::Sa aka - as Verilog ?.
whitequark [Tue, 9 Jul 2019 18:30:24 +0000 (18:30 +0000)]
write_verilog: write RTLIL::Sa aka - as Verilog ?.

Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.

5 years agoExtend during mux decomposition with 1'bx
Eddie Hung [Tue, 9 Jul 2019 17:59:37 +0000 (10:59 -0700)]
Extend during mux decomposition with 1'bx

5 years agoFix typo and comments
Eddie Hung [Tue, 9 Jul 2019 17:38:07 +0000 (10:38 -0700)]
Fix typo and comments

5 years agoMerge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Eddie Hung [Tue, 9 Jul 2019 17:22:57 +0000 (10:22 -0700)]
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore

Rename __builtin_bswap32 -> bswap32

5 years agoMerge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 17:22:49 +0000 (10:22 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux

5 years agosynth_xilinx to call commands of synth -coarse directly
Eddie Hung [Tue, 9 Jul 2019 17:21:54 +0000 (10:21 -0700)]
synth_xilinx to call commands of synth -coarse directly

5 years agoRevert "synth_xilinx to call "synth -run coarse" with "-keepdc""
Eddie Hung [Tue, 9 Jul 2019 17:15:02 +0000 (10:15 -0700)]
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""

This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.

5 years agoRevert "Add "synth -keepdc" option"
Eddie Hung [Tue, 9 Jul 2019 17:14:23 +0000 (10:14 -0700)]
Revert "Add "synth -keepdc" option"

5 years agoRename __builtin_bswap32 -> bswap32
Eddie Hung [Tue, 9 Jul 2019 16:35:09 +0000 (09:35 -0700)]
Rename __builtin_bswap32 -> bswap32

5 years agoFix spacing
Eddie Hung [Tue, 9 Jul 2019 16:22:12 +0000 (09:22 -0700)]
Fix spacing

5 years agoFix spacing
Eddie Hung [Tue, 9 Jul 2019 16:16:00 +0000 (09:16 -0700)]
Fix spacing

5 years agoMerge pull request #1168 from whitequark/bugpoint-processes
Clifford Wolf [Tue, 9 Jul 2019 14:59:43 +0000 (16:59 +0200)]
Merge pull request #1168 from whitequark/bugpoint-processes

Add support for processes in bugpoint

5 years agoMerge pull request #1169 from whitequark/more-proc-cleanups
Clifford Wolf [Tue, 9 Jul 2019 14:59:18 +0000 (16:59 +0200)]
Merge pull request #1169 from whitequark/more-proc-cleanups

A new proc_prune pass

5 years agoMerge pull request #1163 from whitequark/more-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:57:16 +0000 (16:57 +0200)]
Merge pull request #1163 from whitequark/more-case-attrs

More support for case rule attributes

5 years agoMerge pull request #1162 from whitequark/rtlil-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:56:29 +0000 (16:56 +0200)]
Merge pull request #1162 from whitequark/rtlil-case-attrs

Allow attributes on individual switch cases in RTLIL

5 years agoMerge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Clifford Wolf [Tue, 9 Jul 2019 14:49:08 +0000 (16:49 +0200)]
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup

Cleanup synth_xilinx SRL inference, make more consistent

5 years agoproc_prune: promote assigns to module connections when legal.
whitequark [Tue, 9 Jul 2019 08:14:52 +0000 (08:14 +0000)]
proc_prune: promote assigns to module connections when legal.

This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)

5 years agoproc_prune: new pass.
whitequark [Mon, 8 Jul 2019 15:19:01 +0000 (15:19 +0000)]
proc_prune: new pass.

The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.

5 years agobugpoint: add -assigns and -updates options.
whitequark [Tue, 9 Jul 2019 09:08:38 +0000 (09:08 +0000)]
bugpoint: add -assigns and -updates options.