Tamar Christina [Thu, 14 Jan 2021 21:01:15 +0000 (21:01 +0000)]
slp: Add Tests for complex mul, mls and mla"
This adds the initial tests for the complex mul, mls and mla.
These will be enabled in the commits that add the optabs.
Committed as obvious variations of existing tests.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/complex/complex-mla-template.c: New test.
* gcc.dg/vect/complex/complex-mls-template.c: New test.
* gcc.dg/vect/complex/complex-mul-template.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-double.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-float.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-half-float.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-double.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-float.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-half-float.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-double.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-float.c: New test.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-half-float.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mla-double.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mla-float.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mla-half-float.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mls-double.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mls-float.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mls-half-float.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mul-double.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mul-float.c: New test.
* gcc.dg/vect/complex/fast-math-complex-mul-half-float.c: New test.
Tamar Christina [Thu, 14 Jan 2021 21:00:10 +0000 (21:00 +0000)]
slp: Add complex operations class to share first match among all matchers
This introduces a common class complex_operations_pattern which encapsulates
the complex add, mul, fma and fms pattern in such a way so that the first match
is shared.
gcc/ChangeLog:
* tree-vect-slp-patterns.c (class complex_operations_pattern,
complex_operations_pattern::matches,
complex_operations_pattern::recognize,
complex_operations_pattern::build): New.
(slp_patterns): Use it.
Tamar Christina [Thu, 14 Jan 2021 20:59:12 +0000 (20:59 +0000)]
slp: support complex FMS and complex FMS conjugate
This adds support for FMS and FMS conjugated to the slp pattern matcher.
Example of matches:
#include <stdio.h>
#include <complex.h>
#define N 200
#define ROT
#define TYPE float
#define TYPE2 float
void g (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] -= a[i] * (b[i] ROT);
}
}
void g_f1 (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] -= conjf (a[i]) * (b[i]);
}
}
void g_s1 (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] -= a[i] * conjf (b[i] ROT);
}
}
void caxpy_sub(double complex * restrict y, double complex * restrict x, size_t N, double complex f) {
for (size_t i = 0; i < N; ++i)
y[i] -= x[i]* f;
}
gcc/ChangeLog:
* internal-fn.def (COMPLEX_FMS, COMPLEX_FMS_CONJ): New.
* optabs.def (cmls_optab, cmls_conj_optab): New.
* doc/md.texi: Document them.
* tree-vect-slp-patterns.c (class complex_fms_pattern,
complex_fms_pattern::matches, complex_fms_pattern::recognize,
complex_fms_pattern::build): New.
Tamar Christina [Thu, 14 Jan 2021 20:58:12 +0000 (20:58 +0000)]
slp: support complex FMA and complex FMA conjugate
This adds support for FMA and FMA conjugated to the slp pattern matcher.
Example of instructions matched:
#include <stdio.h>
#include <complex.h>
#define N 200
#define ROT
#define TYPE float
#define TYPE2 float
void g (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] += a[i] * (b[i] ROT);
}
}
void g_f1 (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] += conjf (a[i]) * (b[i] ROT);
}
}
void g_s1 (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] += a[i] * conjf (b[i] ROT);
}
}
void caxpy_add(double complex * restrict y, double complex * restrict x, size_t N, double complex f) {
for (size_t i = 0; i < N; ++i)
y[i] += x[i]* f;
}
gcc/ChangeLog:
* internal-fn.def (COMPLEX_FMA, COMPLEX_FMA_CONJ): New.
* optabs.def (cmla_optab, cmla_conj_optab): New.
* doc/md.texi: Document them.
* tree-vect-slp-patterns.c (vect_match_call_p,
class complex_fma_pattern, vect_slp_reset_pattern,
complex_fma_pattern::matches, complex_fma_pattern::recognize,
complex_fma_pattern::build): New.
Tamar Christina [Thu, 14 Jan 2021 20:57:17 +0000 (20:57 +0000)]
slp: support complex multiply and complex multiply conjugate
This adds support for complex multiply and complex multiply and accumulate to
the vect pattern detector.
Example of instructions matched:
#include <stdio.h>
#include <complex.h>
#define N 200
#define ROT
#define TYPE float
#define TYPE2 float
void g (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] = a[i] * (b[i] ROT);
}
}
void g_f1 (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] = conjf (a[i]) * (b[i] ROT);
}
}
void g_s1 (TYPE2 complex a[restrict N], TYPE complex b[restrict N], TYPE complex c[restrict N])
{
for (int i=0; i < N; i++)
{
c[i] = a[i] * conjf (b[i] ROT);
}
}
gcc/ChangeLog:
* internal-fn.def (COMPLEX_MUL, COMPLEX_MUL_CONJ): New.
* optabs.def (cmul_optab, cmul_conj_optab): New.
* doc/md.texi: Document them.
* tree-vect-slp-patterns.c (vect_match_call_complex_mla,
vect_normalize_conj_loc, is_eq_or_top, vect_validate_multiplication,
vect_build_combine_node, class complex_mul_pattern,
complex_mul_pattern::matches, complex_mul_pattern::recognize,
complex_mul_pattern::build): New.
Tamar Christina [Thu, 14 Jan 2021 20:50:57 +0000 (20:50 +0000)]
slp: Support optimizing load distribution
This introduces a post processing step for the pattern matcher to flatten
permutes introduced by the complex multiplications patterns.
This performs a blend early such that SLP is not cancelled by the LOAD_LANES
permute. This is a temporary workaround to the fact that loads are not CSEd
during building and is required to produce efficient code.
gcc/ChangeLog:
* tree-vect-slp.c (optimize_load_redistribution_1): New.
(optimize_load_redistribution, vect_is_slp_load_node): New.
(vect_match_slp_patterns): Use it.
Tamar Christina [Thu, 14 Jan 2021 20:49:55 +0000 (20:49 +0000)]
slp: elide intermediate nodes for complex add and avoid truncate
This applies the same feedback received for MUL and the rest to
ADD which was already committed. In short it elides the intermediate
nodes vec and avoids the use of truncate on the SLP child.
gcc/ChangeLog:
* tree-vect-slp-patterns.c (complex_add_pattern::build):
Elide nodes.
David Malcolm [Thu, 14 Jan 2021 20:39:14 +0000 (15:39 -0500)]
analyzer: fixes to -fdump-analyzer-json
I've been implementing a PyGTK viewer for the output of
-fdump-analyzer-json, to help me debug analyzer issues:
https://github.com/davidmalcolm/gcc-analyzer-viewer
The viewer is very much just a work in progress.
This patch adds some fields that were missing from the dump, and
fixes some mistakes I spotted whilst working on the viewer.
gcc/analyzer/ChangeLog:
* engine.cc (strongly_connected_components::to_json): New.
(worklist::to_json): New.
(exploded_graph::to_json): JSON-ify the worklist.
* exploded-graph.h (strongly_connected_components::to_json): New
decl.
(worklist::to_json): New decl.
* store.cc (store::to_json): Fix comment.
* supergraph.cc (supernode::to_json): Fix reference to
"returning_call" in comment. Add optional "fun" to JSON.
(edge_kind_to_string): New.
(superedge::to_json): Add "kind" to JSON.
David Malcolm [Thu, 14 Jan 2021 20:25:27 +0000 (15:25 -0500)]
analyzer: const fixes [PR98679]
gcc/analyzer/ChangeLog:
PR analyzer/98679
* analyzer.h (region_offset::operator==): Make const.
* pending-diagnostic.h (pending_diagnostic::equal_p): Likewise.
* store.h (binding_cluster::for_each_value): Likewise.
(binding_cluster::for_each_binding): Likewise.
Marek Polacek [Thu, 14 Jan 2021 19:44:59 +0000 (14:44 -0500)]
c++: Tweak g++.dg/template/pr98372.C.
This test was failing in C++11 because variable templates are only
available in C++14.
gcc/testsuite/ChangeLog:
* g++.dg/template/pr98372.C: Only run in C++14 and up.
Harald Anlauf [Thu, 14 Jan 2021 19:25:33 +0000 (20:25 +0100)]
PR fortran/93340 - fix missed substring simplifications
Substrings were not reduced early enough for use in initializations,
such as DATA statements. Add an early simplification for substrings
with constant starting and ending points.
gcc/fortran/ChangeLog:
* gfortran.h (gfc_resolve_substring): Add prototype.
* primary.c (match_string_constant): Simplify substrings with
constant starting and ending points.
* resolve.c: Rename resolve_substring to gfc_resolve_substring.
(gfc_resolve_ref): Use renamed function gfc_resolve_substring.
gcc/testsuite/ChangeLog:
* substr_10.f90: New test.
* substr_9.f90: New test.
Alexandre Oliva [Thu, 14 Jan 2021 19:12:22 +0000 (16:12 -0300)]
calibrate intervals to avoid zero in futures poll test
We get occasional failures of 30_threads/future/members/poll.cc
on some platforms whose high resolution clock doesn't have such a high
resolution; wait_for_0 ends up as 0, and then some asserts fail as
intervals measured as longer than zero are tested for less than
several times zero.
This patch adds some calibration in the iteration count to set a
measurable base time interval with some additional margin.
for libstdc++-v3/ChangeLog
* testsuite/30_threads/future/members/poll.cc: Calibrate
iteration count.
Alexandre Oliva [Thu, 14 Jan 2021 19:12:20 +0000 (16:12 -0300)]
use sigjmp_buf for analyzer sigsetjmp tests
The sigsetjmp analyzer tests use jmp_buf in sigsetjmp and siglongjmp
calls. Not every system that supports sigsetjmp uses the same data
structure for setjmp and sigsetjmp, which results in type mismatches.
This patch changes the tests to use sigjmp_buf, that is the
POSIX-specific type for use with sigsetjmp and siglongjmp.
for gcc/testsuite/ChnageLog
* gcc.dg/analyzer/sigsetjmp-5.c: Use sigjmp_buf.
* gcc.dg/analyzer/sigsetjmp-6.c: Likewise.
Alexandre Oliva [Thu, 14 Jan 2021 19:12:19 +0000 (16:12 -0300)]
declare getpass in analyzer/sensitive-1.c test
The getpass function is not available on all systems; and not
necessarily declared in unistd.h, as expected by the sensitive-1
analyzer test.
Since this is a compile-only test, it doesn't really matter if the
function is defined in the system libraries. All we need is a
declaration, to avoid warnings from calling an undeclared function.
This patch adds the declaration, in a way that is most unlikely to
conflict with any existing declaration.
for gcc/testsuite/ChangeLog
* gcc.dg/analyzer/sensitive-1.c: Declare getpass.
Thomas Schwinge [Tue, 28 Apr 2020 18:43:38 +0000 (20:43 +0200)]
[gcn offloading] Only supported in 64-bit configurations
Similar to nvptx offloading, see PR65099 "nvptx offloading: hard-coded 64-bit
assumptions".
gcc/
* config/gcn/mkoffload.c (main): Create an offload image only in
64-bit configurations.
François Dumont [Fri, 1 Jan 2021 16:35:56 +0000 (17:35 +0100)]
libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
libstdc++-v3/ChangeLog:
PR libstdc++/98466
* include/bits/hashtable_policy.h (_Node_iterator_base()): Set _M_cur to nullptr.
(_Node_iterator()): Make default.
(_Node_const_iterator()): Make default.
* include/debug/macros.h (__glibcxx_check_erae_range_after): Add _M_singular
iterator checks.
* include/debug/safe_iterator.h
(_GLIBCXX_DEBUG_VERIFY_OPERANDS): Accept if both iterator are value initialized.
* include/debug/safe_local_iterator.h (_GLIBCXX_DEBUG_VERIFY_OPERANDS):
Likewise.
* include/debug/safe_iterator.tcc (_Safe_iterator<>::_M_valid_range): Add
_M_singular checks on input iterators.
* src/c++11/debug.cc (_Safe_iterator_base::_M_can_compare): Remove _M_singular
checks.
* testsuite/23_containers/deque/debug/98466.cc: New test.
* testsuite/23_containers/unordered_map/debug/98466.cc: New test.
Harald Anlauf [Thu, 14 Jan 2021 18:21:05 +0000 (19:21 +0100)]
PR fortran/98661 - valgrind issues with error recovery
During error recovery after an invalid derived type specification it was
possible to try to resolve an invalid array specification. We now skip
this if the component has the ALLOCATABLE or POINTER attribute and the
shape is not deferred.
gcc/fortran/ChangeLog:
PR fortran/98661
* resolve.c (resolve_component): Derived type components with
ALLOCATABLE or POINTER attribute shall have a deferred shape.
gcc/testsuite/ChangeLog:
PR fortran/98661
* gfortran.dg/pr98661.f90: New test.
Harald Anlauf [Thu, 14 Jan 2021 18:17:05 +0000 (19:17 +0100)]
Revert "PR fortran/98661 - valgrind issues with error recovery"
This reverts commit
d0d2becf2dfe8316c9014d962e7f77773ec5c27e.
Harald Anlauf [Thu, 14 Jan 2021 18:13:16 +0000 (19:13 +0100)]
PR fortran/98661 - valgrind issues with error recovery
During error recovery after an invalid derived type specification it was
possible to try to resolve an invalid array specification. We now skip
this if the component has the ALLOCATABLE or POINTER attribute and the
shape is not deferred.
gcc/fortran/ChangeLog:
PR fortran/98661
* resolve.c (resolve_component): Derived type components with
ALLOCATABLE or POINTER attribute shall have a deferred shape.
gcc/testsuite/ChangeLog:
PR fortran/98661
* gfortran.dg/pr98661.f90: New test.
Ian Lance Taylor [Wed, 13 Jan 2021 19:54:15 +0000 (11:54 -0800)]
libgo: update hurd support
Patch from Svante Signell.
Fixes PR go/98496
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/283692
Thomas Schwinge [Mon, 30 Nov 2020 14:15:20 +0000 (15:15 +0100)]
[nvptx libgomp plugin] Build only in supported configurations
As recently again discussed in <https://gcc.gnu.org/PR97436> "[nvptx] -m32
support", nvptx offloading other than for 64-bit host has never been
implemented, tested, supported. So we simply should buildn't the nvptx libgomp
plugin in this case.
This avoids build problems if, for example, in a (standard) bi-arch
x86_64-pc-linux-gnu '-m64'/'-m32' build, libcuda is available only in a 64-bit
variant but not in a 32-bit one, which, for example, is the case if you build
GCC against the CUDA toolkit's 'stubs/libcuda.so' (see
<https://stackoverflow.com/a/
52784819>).
This amends PR65099 commit
a92defdab79a1268f4b9dcf42b937e4002a4cf15 (r225560)
"[nvptx offloading] Only 64-bit configurations are currently supported" to
match the way we're doing this for the HSA/GCN plugins.
libgomp/
PR libgomp/65099
* plugin/configfrag.ac (PLUGIN_NVPTX): Restrict to supported
configurations.
* configure: Regenerate.
* plugin/plugin-nvptx.c (nvptx_get_num_devices): Remove 64-bit
check.
Jonathan Wakely [Thu, 14 Jan 2021 14:26:19 +0000 (14:26 +0000)]
libstdc++: Define function to throw filesystem_error [PR 98471]
Fix ordering problem on Windows targets where filesystem_error was used
before being defined.
libstdc++-v3/ChangeLog:
PR libstdc++/98471
* include/bits/fs_path.h (__throw_conversion_error): New
function to throw or abort on character conversion errors.
(__wstr_from_utf8): Move definition after filesystem_error has
been defined. Use __throw_conversion_error.
(path::_S_convert<_EcharT>): Use __throw_conversion_error.
(path::_S_str_convert<_CharT, _Traits, _Allocator>): Likewise.
(path::u8string): Likewise.
Sebastian Huber [Thu, 14 Jan 2021 15:05:14 +0000 (16:05 +0100)]
RTEMS: Fix Ada build for riscv
gcc/ada/
PR ada/98595
* Makefile.rtl (LIBGNAT_TARGET_PAIRS) <riscv*-*-rtems*>: Use
wraplf version of Aux_Long_Long_Float.
Martin Liska [Thu, 14 Jan 2021 16:08:32 +0000 (17:08 +0100)]
gcov: add one more pytest
gcc/testsuite/ChangeLog:
* g++.dg/gcov/gcov-17.C: New test.
* g++.dg/gcov/test-gcov-17.py: New test.
Martin Liska [Thu, 14 Jan 2021 16:06:08 +0000 (17:06 +0100)]
mklog: skip unsupported files
This fixes an infinite loop one could see for:
git show
b87ec922c40 | ./contrib/mklog.py
contrib/ChangeLog:
* mklog.py: Fix infinite loop for unsupported files.
H.J. Lu [Thu, 14 Jan 2021 13:56:46 +0000 (05:56 -0800)]
x86: Error on -fcf-protection with incompatible target
-fcf-protection with CF_BRANCH inserts ENDBR32 at function entries.
ENDBR32 is NOP only on 64-bit processors and 32-bit TARGET_CMOV
processors. Issue an error for -fcf-protection with CF_BRANCH when
compiling for 32-bit non-TARGET_CMOV targets.
gcc/
PR target/98667
* config/i386/i386-options.c (ix86_option_override_internal):
Issue an error for -fcf-protection with CF_BRANCH when compiling
for 32-bit non-TARGET_CMOV targets.
gcc/testsuite/
PR target/98667
* gcc.target/i386/pr98667-1.c: New file.
* gcc.target/i386/pr98667-2.c: Likewise.
* gcc.target/i386/pr98667-3.c: Likewise.
Uros Bizjak [Thu, 14 Jan 2021 15:28:27 +0000 (16:28 +0100)]
i386: Resolve variable shadowing in i386-options.c [PR98671]
Also change global variable pta_size to unsigned.
2021-01-14 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/98671
* config/i386/i386-options.c (ix86_valid_target_attribute_inner_p):
Remove declaration and initialization of shadow variable "ret".
(ix86_option_override_internal): Remove delcaration of
shadow variable "i". Redeclare shadowed variable to unsigned.
* common/config/i386/i386-common.c (pta_size): Redeclare to unsigned.
* config/i386/i386-builtins.c (get_builtin_code_for_version):
Update for redeclaration.
* config/i386/i386.h (pta_size): Ditto.
Richard Biener [Thu, 14 Jan 2021 13:08:41 +0000 (14:08 +0100)]
tree-optimization/98674 - improve dependence analysis
This improves dependence analysis on refs that access the same
array but with different typed but same sized accesses. That's
obviously safe for the case of types that cannot have any
access function based off them. For the testcase this is
signed short vs. unsigned short.
2021-01-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/98674
* tree-data-ref.c (base_supports_access_fn_components_p): New.
(initialize_data_dependence_relation): For two bases without
possible access fns resort to type size equality when determining
shape compatibility.
* gcc.dg/vect/pr98674.c: New testcase.
H.J. Lu [Thu, 14 Jan 2021 14:56:17 +0000 (06:56 -0800)]
i386: Update PR target/95021 tests
Also pass -mpreferred-stack-boundary=4 -mno-stackrealign to avoid
disabling STV by:
/* Disable STV if -mpreferred-stack-boundary={2,3} or
-mincoming-stack-boundary={2,3} or -mstackrealign - the needed
stack realignment will be extra cost the pass doesn't take into
account and the pass can't realign the stack. */
if (ix86_preferred_stack_boundary < 128
|| ix86_incoming_stack_boundary < 128
|| opts->x_ix86_force_align_arg_pointer)
opts->x_target_flags &= ~MASK_STV;
PR target/98676
* gcc.target/i386/pr95021-1.c: Add -mpreferred-stack-boundary=4
-mno-stackrealign.
* gcc.target/i386/pr95021-3.c: Likewise.
Prathamesh Kulkarni [Thu, 14 Jan 2021 14:28:35 +0000 (19:58 +0530)]
arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon.h [PR66791]
gcc/
2021-01-14 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
PR target/66791
* config/arm/arm_neon.h: Replace calls to __builtin_vcge* by
<=, >= operators in vcle and vcge intrinsics respectively.
* config/arm/arm_neon_builtins.def: Remove entry for
vcge and vcgeu.
Jonathan Wakely [Thu, 14 Jan 2021 14:25:05 +0000 (14:25 +0000)]
libstdc++: Update copyright dates on new files
The patch adding these files was approved in 2020 but it wasn't
committed until 2021, so the copyright years were not updated along with
the years in all the existing files.
libstdc++-v3/ChangeLog:
* include/std/barrier: Update copyright years. Fix whitespace.
* include/std/version: Fix whitespace.
* testsuite/30_threads/barrier/1.cc: Update copyright years.
* testsuite/30_threads/barrier/2.cc: Likewise.
* testsuite/30_threads/barrier/arrive.cc: Likewise.
* testsuite/30_threads/barrier/arrive_and_drop.cc: Likewise.
* testsuite/30_threads/barrier/arrive_and_wait.cc: Likewise.
* testsuite/30_threads/barrier/completion.cc: Likewise.
Nathan Sidwell [Thu, 14 Jan 2021 13:15:33 +0000 (05:15 -0800)]
c++: Fix erroneous parm comparison logic [PR 98372]
I flubbed an application of De Morgan's law. Let's just express the
logic directly and let the compiler figure it out. This bug made it
look like pr52830 was fixed, but it is not.
PR c++/98372
gcc/cp/
* tree.c (cp_tree_equal): Correct map_context logic.
gcc/testsuite/
* g++.dg/cpp0x/constexpr-52830.C: Restore dg-ice
* g++.dg/template/pr98372.C: New.
Uros Bizjak [Thu, 14 Jan 2021 12:21:56 +0000 (13:21 +0100)]
i386: Remove reduntand assignment in i386-options.c [PR98671]
Also rename x86_prefetch_sse to ix86_prefetch_sse.
2021-01-14 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/98671
* config/i386/i386-options.c (ix86_function_specific_save):
Remove redundant assignment to opts->x_ix86_branch_cost.
* config/i386/i386.c (ix86_prefetch_sse):
Rename from x86_prefetch_sse. Update all uses.
* config/i386/i386.h: Update for rename.
* config/i386/i386-options.h: Ditto.
Jakub Jelinek [Thu, 14 Jan 2021 11:55:19 +0000 (12:55 +0100)]
i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [PR98670]
I've made two mistakes in the *sse4_1_zero_extend* define_insn_and_split
patterns. One is that when it uses vector_operand, it should use Bm rather
than m constraint, and the other one is that because it is a post-reload
splitter it needs isa attribute to select which alternatives are valid for
which ISAs. Sorry for messing this up.
2021-01-14 Jakub Jelinek <jakub@redhat.com>
PR target/98670
* config/i386/sse.md (*sse4_1_zero_extendv8qiv8hi2_3,
*sse4_1_zero_extendv4hiv4si2_3, *sse4_1_zero_extendv2siv2di2_3):
Use Bm instead of m for non-avx. Add isa attribute.
* gcc.target/i386/pr98670.c: New test.
Jakub Jelinek [Thu, 14 Jan 2021 11:50:33 +0000 (12:50 +0100)]
match.pd: Optimize ~(X >> Y) to ~X >> Y if ~X can be simplified [PR96688]
This patch optimizes two GIMPLE operations into just one.
As mentioned in the PR, there is some risk this might create more expensive
constants, but sometimes it will make them on the other side less expensive,
it really depends on the exact value.
And if it is an important issue, we should do it in md or during expansion.
2021-01-14 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/96688
* match.pd (~(X >> Y) -> ~X >> Y): New simplification if
~X can be simplified.
* gcc.dg/tree-ssa/pr96688.c: New test.
* gcc.dg/tree-ssa/reassoc-37.c: Adjust scan-tree-dump regex.
* gcc.target/i386/pr66821.c: Likewise.
Richard Sandiford [Thu, 14 Jan 2021 11:36:25 +0000 (11:36 +0000)]
vect: Account for unused IFN_LOAD_LANES results
At the moment, if we use only one vector of an LD4 result,
we'll treat the LD4 as having the cost of a single load.
But all 4 loads and any associated permutes take place
regardless of which results are actually used.
This patch therefore counts the cost of unused LOAD_LANES
results against the first statement in a group. An alternative
would be to multiply the ncopies of the first stmt by the group
size and treat other stmts in the group as having zero cost,
but I thought that might be more surprising when reading dumps.
gcc/
* tree-vect-stmts.c (vect_model_load_cost): Account for unused
IFN_LOAD_LANES results.
gcc/testsuite/
* gcc.target/aarch64/sve/cost_model_11.c: New test.
* gcc.target/aarch64/sve/mask_struct_load_5.c: Use
-fno-vect-cost-model.
Kyrylo Tkachov [Wed, 13 Jan 2021 12:48:57 +0000 (12:48 +0000)]
aarch64: Reimplememnt vmovn/vmovl intrinsics with builtins instead
Turns out __builtin_convertvector is not as good a fit for the widening
and narrowing intrinsics as I had hoped.
During the veclower phase we lower most of it to bitfield operations and
hope DCE cleans it back up into
vector pack/unpack and extend operations. I received reports that in
more complex cases GCC fails to do that
and we're left with many vector extract operations that clutter the
output.
I think veclower can be improved on that front, but for GCC 10 I'd like
to just implement these builtins
with a good old RTL builtin rather than inline asm.
gcc/
* config/aarch64/aarch64-simd.md (aarch64_<su>xtl<mode>):
Define.
(aarch64_xtn<mode>): Likewise.
* config/aarch64/aarch64-simd-builtins.def (sxtl, uxtl, xtn):
Define
builtins.
* config/aarch64/arm_neon.h (vmovl_s8): Reimplement using
builtin.
(vmovl_s16): Likewise.
(vmovl_s32): Likewise.
(vmovl_u8): Likewise.
(vmovl_u16): Likewise.
(vmovl_u32): Likewise.
(vmovn_s16): Likewise.
(vmovn_s32): Likewise.
(vmovn_s64): Likewise.
(vmovn_u16): Likewise.
(vmovn_u32): Likewise.
(vmovn_u64): Likewise.
Kyrylo Tkachov [Wed, 13 Jan 2021 12:14:30 +0000 (12:14 +0000)]
aarch64: reimplement vqmovn_high* intrinsics using builtins
This patch reimplements the saturating-truncate-and-insert-into-high
intrinsics using the appropriate RTL codes and builtins.
gcc/
* config/aarch64/aarch64-simd.md (aarch64_<su>qxtn2<mode>_le):
Define.
(aarch64_<su>qxtn2<mode>_be): Likewise.
(aarch64_<su>qxtn2<mode>): Likewise.
* config/aarch64/aarch64-simd-builtins.def (sqxtn2, uqxtn2):
Define builtins.
* config/aarch64/iterators.md (SAT_TRUNC): Define code_iterator.
(su): Handle ss_truncate and us_truncate.
* config/aarch64/arm_neon.h (vqmovn_high_s16): Reimplement using
builtin.
(vqmovn_high_s32): Likewise.
(vqmovn_high_s64): Likewise.
(vqmovn_high_u16): Likewise.
(vqmovn_high_u32): Likewise.
(vqmovn_high_u64): Likewise.
gcc/testsuite/
* gcc.target/aarch64/narrow_high-intrinsics.c: Update uqxtn2 and
sqxtn2 scan-assembler-times.
Kyrylo Tkachov [Tue, 12 Jan 2021 10:07:19 +0000 (10:07 +0000)]
aarch64: Reimplement vmovn_high_* intrinsics using builtins
The vmovn_high* intrinsics are supposed to map to XTN2 instructions that
narrow their source vector and instert it into the top half of the destination vector.
This patch reimplements them away from inline assembly to an RTL builtin
that performs a vec_concat with a truncate.
gcc/
* config/aarch64/aarch64-simd.md (aarch64_xtn2<mode>_le):
Define.
(aarch64_xtn2<mode>_be): Likewise.
(aarch64_xtn2<mode>): Likewise.
* config/aarch64/aarch64-simd-builtins.def (xtn2): Define
builtins.
* config/aarch64/arm_neon.h (vmovn_high_s16): Reimplement using
builtins.
(vmovn_high_s32): Likewise.
(vmovn_high_s64): Likewise.
(vmovn_high_u16): Likewise.
(vmovn_high_u32): Likewise.
(vmovn_high_u64): Likewise.
gcc/testsuite/
* gcc.target/aarch64/narrow_high-intrinsics.c: Adjust
scan-assembler-times for xtn2.
GCC Administrator [Thu, 14 Jan 2021 00:16:24 +0000 (00:16 +0000)]
Daily bump.
Stafford Horne [Sun, 22 Mar 2020 01:13:22 +0000 (10:13 +0900)]
or1k: Fixup exception header data encodings
While running glibc tests several *-textrel tests failed showing that
relocations remained against read only sections. It turned out this was
related to exception headers data encoding being wrong.
By default pointer encoding will always use the DW_EH_PE_absptr format.
This patch uses format DW_EH_PE_pcrel and DW_EH_PE_sdata4. Optionally
DW_EH_PE_indirect is included for global symbols. This eliminates the
relocations.
gcc/ChangeLog:
* config/or1k/or1k.h (ASM_PREFERRED_EH_DATA_FORMAT): New macro.
Stafford Horne [Sun, 22 Mar 2020 01:11:21 +0000 (10:11 +0900)]
or1k: Add note to indicate execstack
Define TARGET_ASM_FILE_END as file_end_indicate_exec_stack to allow
generation of the ".note.GNU-stack" section note. This allows binutils
to properly set PT_GNU_STACK in the program header.
This fixes a glibc execstack testsuite test failure found while working
on the OpenRISC glibc port.
gcc/ChangeLog:
* config/or1k/linux.h (TARGET_ASM_FILE_END): Define macro.
Stafford Horne [Fri, 24 Jan 2020 12:30:31 +0000 (21:30 +0900)]
or1k: Support for softfloat to emulate hw exceptions
This allows the openrisc softfloat implementation to set exceptions.
This also sets the correct tininess after rounding value to be
consistent with hardware and simulator implementations.
libgcc/ChangeLog:
* config/or1k/sfp-machine.h (FP_RND_NEAREST, FP_RND_ZERO,
FP_RND_PINF, FP_RND_MINF, FP_RND_MASK, FP_EX_OVERFLOW,
FP_EX_UNDERFLOW, FP_EX_INEXACT, FP_EX_INVALID, FP_EX_DIVZERO,
FP_EX_ALL): New constant macros.
(_FP_DECL_EX, FP_ROUNDMODE, FP_INIT_ROUNDMODE,
FP_HANDLE_EXCEPTIONS): New macros.
(_FP_TININESS_AFTER_ROUNDING): Change to 1.
Stafford Horne [Fri, 24 Jan 2020 12:31:00 +0000 (21:31 +0900)]
or1k: Add builtin define to detect hard float
This is used in libgcc and now glibc to detect when hardware floating
point operations are supported by the target.
gcc/ChangeLog:
* config/or1k/or1k.h (TARGET_CPU_CPP_BUILTINS): Add builtin
define for __or1k_hard_float__.
Stafford Horne [Mon, 14 Oct 2019 06:14:20 +0000 (15:14 +0900)]
or1k: Implement profile hook calling _mcount
Defining this to not abort as found when working on running tests in
the glibc test suite.
We implement this with a call to _mcount with no arguments. The required
return address's will be pulled from the stack. Passing the LR (r9) as
an argument had problems as sometimes r9 is clobbered by the GOT logic
in the prologue before the call to _mcount.
gcc/ChangeLog:
* config/or1k/or1k.h (NO_PROFILE_COUNTERS): Define as 1.
(PROFILE_HOOK): Define to call _mcount.
(FUNCTION_PROFILER): Change from abort to no-op.
Marek Polacek [Wed, 13 Jan 2021 16:09:14 +0000 (11:09 -0500)]
c++: Failure to lookup using-decl name [PR98231]
In r11-4690 we removed the call to finish_nonmember_using_decl in
tsubst_expr/DECL_EXPR in the USING_DECL block. This was done not
to perform name lookup twice for a non-dependent using-decl, which
sounds sensible.
However, finish_nonmember_using_decl also pushes the decl's bindings
which we still have to do so that we can find the USING_DECL's name
later. In this case, we've got a USING_DECL N::operator<< that we are
tsubstituting. We already looked it up while parsing the template
"foo", and lookup_using_decl stashed the OVERLOAD it found into
USING_DECL_DECLS. Now we just have to update the IDENTIFIER_BINDING of
the identifier for operator<< with the overload the name is bound to.
I didn't want to export push_local_binding so I've introduced a new
wrapper.
gcc/cp/ChangeLog:
PR c++/98231
* name-lookup.c (push_using_decl_bindings): New.
* name-lookup.h (push_using_decl_bindings): Declare.
* pt.c (tsubst_expr): Call push_using_decl_bindings.
gcc/testsuite/ChangeLog:
PR c++/98231
* g++.dg/lookup/using63.C: New test.
Jakub Jelinek [Wed, 13 Jan 2021 18:54:49 +0000 (19:54 +0100)]
match.pd: Fold (~X | C) ^ D into (X | C) ^ (~D ^ C) if (~D ^ C) can be simplified [PR96691]
These simplifications are only simplifications if the (~D ^ C) or (D ^ C)
expressions fold into gimple vals, but in that case they decrease number of
operations by 1.
2021-01-13 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/96691
* match.pd ((~X | C) ^ D -> (X | C) ^ (~D ^ C),
(~X & C) ^ D -> (X & C) ^ (D ^ C)): New simplifications if
(~D ^ C) or (D ^ C) can be simplified.
* gcc.dg/tree-ssa/pr96691.c: New test.
Martin Liska [Wed, 13 Jan 2021 15:54:02 +0000 (16:54 +0100)]
gcc-changelog: Support multiline parentheses wrapping
contrib/ChangeLog:
* gcc-changelog/git_commit.py: Support wrapping of functions
in parentheses that can take multiple lines.
* gcc-changelog/test_email.py: Add tests for it.
* gcc-changelog/test_patches.txt: Add 2 patches.
Richard Biener [Wed, 13 Jan 2021 12:48:31 +0000 (13:48 +0100)]
tree-optimization/92645 - avoid harmful early BIT_FIELD_REF canonicalization
This avoids canonicalizing BIT_FIELD_REF <T1> (a, <sz>, 0) to
(T1)a on integer typed a. This confuses the vectorizer SLP matching.
With this delayed to after vector lowering the testcase in PR92645
from Skia is now finally optimized to reasonable assembly.
2021-01-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/92645
* match.pd (BIT_FIELD_REF to conversion): Delay canonicalization
until after vector lowering.
* gcc.target/i386/pr92645-7.c: New testcase.
* gcc.dg/tree-ssa/ssa-fre-54.c: Adjust.
* gcc.dg/pr69047.c: Likewise.
Martin Liska [Wed, 13 Jan 2021 13:33:43 +0000 (14:33 +0100)]
mklog: support define_insn_and_split format
contrib/ChangeLog:
* mklog.py: Parse also define_insn_and_split and similar
directives in .md files.
* test_mklog.py: Test.
Nathan Sidwell [Wed, 13 Jan 2021 13:13:12 +0000 (05:13 -0800)]
c++: Fix cp_build_function_call_vec [PR 98626]
I misunderstood the cp_build_function_call_vec API, thinking a NULL
vector was an acceptable way of passing no arguments. You need to
pass a vector of no elements.
PR c++/98626
gcc/cp/
* module.cc (module_add_import_initializers): Pass a
zero-element argument vector.
Richard Sandiford [Wed, 13 Jan 2021 13:00:13 +0000 (13:00 +0000)]
aarch64: Add support for unpacked SVE MLS and MSB
This patch extends the MLS/MSB patterns to support unpacked
integer vectors. The type suffix could be either the element
size or the container size, but using the element size should
be more efficient.
gcc/
* config/aarch64/aarch64-sve.md (fnma<mode>4): Extend from SVE_FULL_I
to SVE_I.
(@aarch64_pred_fnma<mode>, cond_fnma<mode>, *cond_fnma<mode>_2)
(*cond_fnma<mode>_4, *cond_fnma<mode>_any): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/mls_2.c: New test.
* g++.target/aarch64/sve/cond_mls_1.C: Likewise.
* g++.target/aarch64/sve/cond_mls_2.C: Likewise.
* g++.target/aarch64/sve/cond_mls_3.C: Likewise.
* g++.target/aarch64/sve/cond_mls_4.C: Likewise.
* g++.target/aarch64/sve/cond_mls_5.C: Likewise.
Richard Sandiford [Wed, 13 Jan 2021 13:00:12 +0000 (13:00 +0000)]
aarch64: Add support for unpacked SVE MLA and MAD
This patch extends the MLA/MAD patterns to support unpacked
integer vectors. The type suffix could be either the element
size or the container size, but using the element size should
be more efficient.
gcc/
* config/aarch64/aarch64-sve.md (fma<mode>4): Extend from SVE_FULL_I
to SVE_I.
(@aarch64_pred_fma<mode>, cond_fma<mode>, *cond_fma<mode>_2)
(*cond_fma<mode>_4, *cond_fma<mode>_any): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/mla_2.c: New test.
* g++.target/aarch64/sve/cond_mla_1.C: Likewise.
* g++.target/aarch64/sve/cond_mla_2.C: Likewise.
* g++.target/aarch64/sve/cond_mla_3.C: Likewise.
* g++.target/aarch64/sve/cond_mla_4.C: Likewise.
* g++.target/aarch64/sve/cond_mla_5.C: Likewise.
Richard Biener [Wed, 13 Jan 2021 11:40:01 +0000 (12:40 +0100)]
tree-optimization/92645 - improve SLP with existing vectors
This improves SLP discovery in the face of existing vectors allowing
punning of the vector shape (or even punning from an integer type).
For punning from integer types this does not yet handle lane zero
extraction being represented as conversion rather than BIT_FIELD_REF.
2021-01-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/92645
* tree-vect-slp.c (vect_build_slp_tree_1): Relax supported
BIT_FIELD_REF argument.
(vect_build_slp_tree_2): Record the desired vector type
on the external vector def.
(vectorizable_slp_permutation): Handle required punning
of existing vector defs.
* gcc.target/i386/pr92645-6.c: New testcase.
Richard Sandiford [Wed, 13 Jan 2021 11:49:45 +0000 (11:49 +0000)]
aarch64: Tighten condition on sve/sel* tests
Noticed while testing on a different machine that the sve/sel_*.c
tests require .variant_pcs support but don't test for it.
.variant_pcs post-dates SVE so there shouldn't be a need to test
for both.
gcc/testsuite/
* gcc.target/aarch64/sve/sel_1.c: Require aarch64_variant_pcs.
* gcc.target/aarch64/sve/sel_2.c: Likewise.
* gcc.target/aarch64/sve/sel_3.c: Likewise.
Richard Sandiford [Wed, 13 Jan 2021 11:43:36 +0000 (11:43 +0000)]
rtl-ssa: Fix reversed comparisons in accesses.h comment
Noticed while looking at something else that the comment above
def_lookup got the description of the comparisons the wrong way
round.
gcc/
* rtl-ssa/accesses.h (def_lookup): Fix order of comparison results.
Richard Sandiford [Wed, 13 Jan 2021 11:37:18 +0000 (11:37 +0000)]
sh: Remove match_scratch operand test
This patch fixes a regression on sh4 introduced by the rtl-ssa stuff.
The port had a pattern:
(define_insn "movsf_ie"
[(set (match_operand:SF 0 "general_movdst_operand"
"=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
(match_operand:SF 1 "general_movsrc_operand"
" f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
(use (reg:SI FPSCR_MODES_REG))
(clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
"TARGET_SH2E
&& (arith_reg_operand (operands[0], SFmode)
|| fpul_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode)
|| fpul_operand (operands[1], SFmode)
|| arith_reg_operand (operands[2], SImode))"
But recog can generate this pattern from something that matches:
[(set (match_operand:SF 0 "general_movdst_operand")
(match_operand:SF 1 "general_movsrc_operand")
(use (reg:SI FPSCR_MODES_REG))]
with recog adding the (clobber (match_scratch:SI)) automatically.
recog tests the C condition before adding the clobber, so there might
not be an operands[2] to test.
Similarly, gen_movsf_ie takes only two arguments, with operand 2
being filled in automatically. The only way to create this pattern
with a REG operands[2] before RA would be to generate it directly
from RTL. AFAICT the only things that do this are the secondary
reload patterns, which are generated during RA and come with
pre-vetted operands.
arith_reg_operand rejects 6 specific registers:
return (regno != T_REG && regno != PR_REG
&& regno != FPUL_REG && regno != FPSCR_REG
&& regno != MACH_REG && regno != MACL_REG);
The fpul_operand tests allow FPUL_REG, leaving 5 invalid registers.
However, in all alternatives of movsf_ie, either operand 0 or
operand 1 is a register that belongs r, f or y, none of which
include any of the 5 rejected registers. This means that any
post-RA pattern would satisfy the operands[0] or operands[1]
condition without the operands[2] test being necessary.
gcc/
* config/sh/sh.md (movsf_ie): Remove operands[2] test.
Samuel Thibault [Sun, 8 Nov 2020 22:52:51 +0000 (23:52 +0100)]
Hurd: Enable ifunc by default
The binutils bugs seem to have been fixed.
gcc/
* config.gcc [$target == *-*-gnu*]: Enable
'default_gnu_indirect_function'.
Jonathan Wakely [Wed, 13 Jan 2021 11:01:58 +0000 (11:01 +0000)]
libstdc++: Fix typo in ChangeLog-2020
Martin Liska [Wed, 13 Jan 2021 10:55:29 +0000 (11:55 +0100)]
gcc-changelog: Allow modifications to old ChangeLogs without entry
contrib/ChangeLog:
* gcc-changelog/git_commit.py: Allow modifications of older
ChangeLog (or specific) files without need to make a ChangeLog
entry.
* gcc-changelog/test_email.py: Test it.
* gcc-changelog/test_patches.txt: Add new patch.
Samuel Thibault [Mon, 21 Dec 2020 14:36:30 +0000 (15:36 +0100)]
hurd: libgcc unwinding over signal trampolines with SIGINFO
When the application sets SA_SIGINFO, the signal trampoline parameters
are different to follow POSIX.
libgcc/
* config/i386/gnu-unwind.h (x86_gnu_fallback_frame_state): Add the
posix siginfo case to struct handler_args. Detect between legacy
and siginfo from the second parameter, which is a small sigcode in
the legacy case, and a pointer in the siginfo case.
Jakub Jelinek [Wed, 13 Jan 2021 10:28:48 +0000 (11:28 +0100)]
i386, expand: Optimize also 256-bit and 512-bit permutatations as vpmovzx if possible [PR95905]
The following patch implements what I've talked about, i.e. to no longer
force operands of vec_perm_const into registers in the generic code, but let
each of the (currently 8) targets force it into registers individually,
giving the targets better control on if it does that and when and allowing
them to do something special with some particular operands.
And then defines the define_insn_and_split for the 256-bit and 512-bit
permutations into vpmovzx* (only the bw, wd and dq cases, in theory we could
add define_insn_and_split patterns also for the bd, bq and wq).
2021-01-13 Jakub Jelinek <jakub@redhat.com>
PR target/95905
* optabs.c (expand_vec_perm_const): Don't force v0 and v1 into
registers before calling targetm.vectorize.vec_perm_const, only after
that.
* config/i386/i386-expand.c (ix86_vectorize_vec_perm_const): Handle
two argument permutation when one operand is zero vector and only
after that force operands into registers.
* config/i386/sse.md (*avx2_zero_extendv16qiv16hi2_1): New
define_insn_and_split pattern.
(*avx512bw_zero_extendv32qiv32hi2_1): Likewise.
(*avx512f_zero_extendv16hiv16si2_1): Likewise.
(*avx2_zero_extendv8hiv8si2_1): Likewise.
(*avx512f_zero_extendv8siv8di2_1): Likewise.
(*avx2_zero_extendv4siv4di2_1): Likewise.
* config/mips/mips.c (mips_vectorize_vec_perm_const): Force operands
into registers.
* config/arm/arm.c (arm_vectorize_vec_perm_const): Likewise.
* config/sparc/sparc.c (sparc_vectorize_vec_perm_const): Likewise.
* config/ia64/ia64.c (ia64_vectorize_vec_perm_const): Likewise.
* config/aarch64/aarch64.c (aarch64_vectorize_vec_perm_const): Likewise.
* config/rs6000/rs6000.c (rs6000_vectorize_vec_perm_const): Likewise.
* config/gcn/gcn.c (gcn_vectorize_vec_perm_const): Likewise. Use std::swap.
* gcc.target/i386/pr95905-2.c: Use scan-assembler-times instead of
scan-assembler. Add tests with zero vector as first __builtin_shuffle
operand.
* gcc.target/i386/pr95905-3.c: New test.
* gcc.target/i386/pr95905-4.c: New test.
Martin Liska [Tue, 12 Jan 2021 12:40:44 +0000 (13:40 +0100)]
if-to-switch: fix also virtual phis
gcc/ChangeLog:
PR tree-optimization/98455
* gimple-if-to-switch.cc (condition_info::record_phi_mapping):
Record also virtual PHIs.
(pass_if_to_switch::execute): Return TODO_cleanup_cfg only
conditionally.
gcc/testsuite/ChangeLog:
PR tree-optimization/98455
* gcc.dg/tree-ssa/pr98455.c: New test.
Jonathan Wakely [Wed, 13 Jan 2021 10:27:52 +0000 (10:27 +0000)]
libstdc++: Remove <debug/array> from Doxygen config
This header was removed recently, so Doxygen shouldn't try to process
it.
libstdc++-v3/ChangeLog:
* doc/doxygen/user.cfg.in (INPUT): Remove include/debug/array.
Jonathan Wakely [Sat, 9 Jan 2021 14:31:48 +0000 (14:31 +0000)]
doc: Fix typos in C++ Modules documentation
gcc/ChangeLog:
* doc/invoke.texi (C++ Modules): Fix typos.
Richard Biener [Wed, 13 Jan 2021 08:43:52 +0000 (09:43 +0100)]
tree-optimization/98640 - fix bogus sign-extension with VN
VN tried to express a sign extension from int to long of
a trucated quantity with a plain conversion but that loses the
truncation. Since there's no single operand doing truncate plus
sign extend (there was a proposed SEXT_EXPR to do that at some
point mapping to RTL sign_extract) don't bother to appropriately
model this with two ops (which the VN insert machinery doesn't
handle and which is unlikely to CSE fully).
2021-01-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/98640
* tree-ssa-sccvn.c (visit_nary_op): Do not try to
handle plus or minus from a truncated operand to be
sign-extended.
* gcc.dg/torture/pr98640.c: New testcase.
Jakub Jelinek [Wed, 13 Jan 2021 09:15:13 +0000 (10:15 +0100)]
i386: Add define_insn_and_split patterns for btrl [PR96938]
In the following testcase we only optimize f2 and f7 to btrl, although we
should optimize that way all of the functions. The problem is the type
demotion/narrowing (which is performed solely during the generic folding and
not later), without it we see the AND performed in SImode and match it as
btrl, but with it while the shifts are still performed in SImode, the
AND is already done in QImode or HImode low part of the shift.
2021-01-13 Jakub Jelinek <jakub@redhat.com>
PR target/96938
* config/i386/i386.md (*btr<mode>_1, *btr<mode>_2): New
define_insn_and_split patterns.
(splitter after *btr<mode>_2): New splitter.
* gcc.target/i386/pr96938.c: New test.
Martin Liska [Wed, 13 Jan 2021 08:25:31 +0000 (09:25 +0100)]
ipa: remove a dead code
gcc/ChangeLog:
PR ipa/98652
* cgraphunit.c (analyze_functions): Remove dead code.
Qian Jianhua [Wed, 13 Jan 2021 07:22:09 +0000 (15:22 +0800)]
[PATCH v2] aarch64: Add cpu cost tables for A64FX
This patch add cost tables for A64FX.
2021-01-13 Qian jianhua <qianjh@cn.fujitsu.com>
gcc/
* config/aarch64/aarch64-cost-tables.h (a64fx_extra_costs): New.
* config/aarch64/aarch64.c (a64fx_addrcost_table): New.
(a64fx_regmove_cost, a64fx_vector_cost): New.
(a64fx_tunings): Use the new added cost tables.
Jakub Jelinek [Wed, 13 Jan 2021 07:02:54 +0000 (08:02 +0100)]
i386: Optimize _mm_unpacklo_epi8 of 0 vector as second argument or similar VEC_PERM_EXPRs into pmovzx [PR95905]
The following patch adds patterns (so far 128-bit only) for permutations
like { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 } where the second
operand is CONST0_RTX CONST_VECTOR to be emitted as pmovzx.
2021-01-13 Jakub Jelinek <jakub@redhat.com>
PR target/95905
* config/i386/predicates.md (pmovzx_parallel): New predicate.
* config/i386/sse.md (*sse4_1_zero_extendv8qiv8hi2_3): New
define_insn_and_split pattern.
(*sse4_1_zero_extendv4hiv4si2_3): Likewise.
(*sse4_1_zero_extendv2siv2di2_3): Likewise.
* gcc.target/i386/pr95905-1.c: New test.
* gcc.target/i386/pr95905-2.c: New test.
Julian Brown [Wed, 25 Nov 2020 00:42:55 +0000 (16:42 -0800)]
amdgcn: Remove dead code for fixed v0 register
This patch removes code to fix the v0 register in
gcn_conditional_register_usage that was missed out of the previous patch
removing the need for that:
https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534284.html
2021-01-13 Julian Brown <julian@codesourcery.com>
gcc/
* config/gcn/gcn.c (gcn_conditional_register_usage): Remove dead code
to fix v0 register.
Julian Brown [Fri, 6 Nov 2020 22:53:29 +0000 (14:53 -0800)]
amdgcn: Fix exec register live-on-entry to BB in md-reorg
This patch fixes a corner case in the AMD GCN md-reorg pass when the
EXEC register is live on entry to a BB, and could be clobbered by code
inserted by the pass before a use in (e.g.) a different BB.
2021-01-13 Julian Brown <julian@codesourcery.com>
gcc/
* config/gcn/gcn.c (gcn_md_reorg): Fix case where EXEC reg is live
on entry to a BB.
Julian Brown [Mon, 30 Nov 2020 19:10:04 +0000 (11:10 -0800)]
amdgcn: Improve FP division accuracy
GCN has a reciprocal-approximation instruction but no
hardware divide. This patch adjusts the open-coded reciprocal
approximation/Newton-Raphson refinement steps to use fused multiply-add
instructions as is necessary to obtain a properly-rounded result, and
adds further refinement steps to correctly round the full division result.
The patterns in question are still guarded by a flag_reciprocal_math
condition, and do not yet support denormals.
2021-01-13 Julian Brown <julian@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (recip<mode>2<exec>, recip<mode>2): Use unspec
for reciprocal-approximation instructions.
(div<mode>3): Use fused multiply-accumulate operations for reciprocal
refinement and division result.
* config/gcn/gcn.md (UNSPEC_RCP): New unspec constant.
gcc/testsuite/
* gcc.target/gcn/fpdiv.c: New test.
Julian Brown [Mon, 30 Nov 2020 20:01:37 +0000 (12:01 -0800)]
amdgcn: Fix subdf3 pattern
This patch fixes a typo in the subdf3 pattern that meant it had a
non-standard name and thus the compiler would emit a libcall rather than
the proper hardware instruction for DFmode subtraction.
2021-01-13 Julian Brown <julian@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (subdf): Rename to...
(subdf3): This.
GCC Administrator [Wed, 13 Jan 2021 00:16:36 +0000 (00:16 +0000)]
Daily bump.
Paul E. Murphy [Fri, 8 Jan 2021 21:43:54 +0000 (15:43 -0600)]
syscall: ensure openat uses variadic libc wrapper
On powerpc64le, this caused a failure in TestUnshareUidGidMapping
due to stack corruption which resulted in a bogus execve syscall.
Use the existing c wrapper to ensure we respect the ppc abi for
variadic functions.
Fixes PR go/98610
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/282717
Martin Sebor [Tue, 12 Jan 2021 19:58:27 +0000 (12:58 -0700)]
Avoid a couple more ICEs in print_mem_ref (PR c/98597).
Resolves:
PR c/98597 - ICE in -Wuninitialized printing a MEM_REF
PR c/98592 - ICE in gimple_canonical_types_compatible_p while formatting
gcc/c-family/ChangeLog:
PR c/98597
PR c/98592
* c-pretty-print.c (print_mem_ref): Avoid assuming MEM_REF operand
has pointer type. Remove redundant code. Avoid calling
gimple_canonical_types_compatible_p.
gcc/testsuite/ChangeLog:
PR c/98597
PR c/98592
* g++.dg/warn/Wuninitialized-13.C: New test.
gcc.dg/uninit-39.c: New test.
#
Segher Boessenkool [Tue, 12 Jan 2021 18:39:10 +0000 (18:39 +0000)]
MAINTAINERS: Fix spacing
We indent with tabs, not spaces. This fixes it.
2021-01-12 Segher Boessenkool <segher@kernel.crashing.org>
* MAINTAINERS: Fix spacing.
Nathan Sidwell [Mon, 11 Jan 2021 16:50:21 +0000 (08:50 -0800)]
libcody: Simplify configure [PR 98414, 98509]
Libcody's configurey was overly 'clever'. That didn't play well with
GCC's structure. This removes lots of that overengineering, using
libcpp as an example.
libcody/
* Makefile.in: Remove auto parallelize, swallow Makesub.in. Don't
check compiler name here.
* Makesub.in: Delete.
* build-aux/config.guess: Delete.
* build-aux/config.sub: Delete.
* build-aux/install-sh: Delete.
* dox.cfg.in: Delete.
* gdbinit.in: Delete.
* internal.hh (BuildNote): Delete.
* fatal.cc (BuildNote): Delete.
* config.m4: Remove unneeded fns.
* configure.ac: Remove unneccessary checks and configures.
* configure: Rebuilt.
* config.h.in: Rebuilt.
Martin Liska [Tue, 12 Jan 2021 17:16:05 +0000 (18:16 +0100)]
gcov: fix printf format for 32-bit hosts
gcc/ChangeLog:
* gcov.c (source_info::debug): Fix printf format for 32-bit hosts.
Andrea Corallo [Tue, 12 Jan 2021 16:52:52 +0000 (17:52 +0100)]
Fix typo in function-abi.h
gcc/Changelog
2021-01-12 Andrea Corallo <andrea.corallo@arm.com>
* function-abi.h: Fix typo.
Christophe Lyon [Tue, 12 Jan 2021 16:47:27 +0000 (16:47 +0000)]
arm: Add movmisalign patterns for MVE (PR target/97875)
This patch adds new movmisalign<mode>_mve_load and store patterns for
MVE to help vectorization. They are very similar to their Neon
counterparts, but use different iterators and instructions.
Indeed MVE supports less vectors modes than Neon, so we use the
MVE_VLD_ST iterator where Neon uses VQX.
Since the supported modes are different from the ones valid for
arithmetic operators, we introduce two new sets of macros:
ARM_HAVE_NEON_<MODE>_LDST
true if Neon has vector load/store instructions for <MODE>
ARM_HAVE_<MODE>_LDST
true if any vector extension has vector load/store instructions for <MODE>
We move the movmisalign<mode> expander from neon.md to vec-commond.md, and
replace the TARGET_NEON enabler with ARM_HAVE_<MODE>_LDST.
The patch also updates the mve-vneg.c test to scan for the better code
generation when loading and storing the vectors involved: it checks
that no 'orr' instruction is generated to cope with misalignment at
runtime.
This test was chosen among the other mve tests, but any other should
be OK. Using a plain vector copy loop (dest[i] = a[i]) is not a good
test because the compiler chooses to use memcpy.
For instance we now generate:
test_vneg_s32x4:
vldrw.32 q3, [r1]
vneg.s32 q3, q3
vstrw.32 q3, [r0]
bx lr
instead of:
test_vneg_s32x4:
orr r3, r1, r0
lsls r3, r3, #28
bne .L15
vldrw.32 q3, [r1]
vneg.s32 q3, q3
vstrw.32 q3, [r0]
bx lr
.L15:
push {r4, r5}
ldrd r2, r3, [r1, #8]
ldrd r5, r4, [r1]
rsbs r2, r2, #0
rsbs r5, r5, #0
rsbs r4, r4, #0
rsbs r3, r3, #0
strd r5, r4, [r0]
pop {r4, r5}
strd r2, r3, [r0, #8]
bx lr
2021-01-12 Christophe Lyon <christophe.lyon@linaro.org>
PR target/97875
gcc/
* config/arm/arm.h (ARM_HAVE_NEON_V8QI_LDST): New macro.
(ARM_HAVE_NEON_V16QI_LDST, ARM_HAVE_NEON_V4HI_LDST): Likewise.
(ARM_HAVE_NEON_V8HI_LDST, ARM_HAVE_NEON_V2SI_LDST): Likewise.
(ARM_HAVE_NEON_V4SI_LDST, ARM_HAVE_NEON_V4HF_LDST): Likewise.
(ARM_HAVE_NEON_V8HF_LDST, ARM_HAVE_NEON_V4BF_LDST): Likewise.
(ARM_HAVE_NEON_V8BF_LDST, ARM_HAVE_NEON_V2SF_LDST): Likewise.
(ARM_HAVE_NEON_V4SF_LDST, ARM_HAVE_NEON_DI_LDST): Likewise.
(ARM_HAVE_NEON_V2DI_LDST): Likewise.
(ARM_HAVE_V8QI_LDST, ARM_HAVE_V16QI_LDST): Likewise.
(ARM_HAVE_V4HI_LDST, ARM_HAVE_V8HI_LDST): Likewise.
(ARM_HAVE_V2SI_LDST, ARM_HAVE_V4SI_LDST, ARM_HAVE_V4HF_LDST): Likewise.
(ARM_HAVE_V8HF_LDST, ARM_HAVE_V4BF_LDST, ARM_HAVE_V8BF_LDST): Likewise.
(ARM_HAVE_V2SF_LDST, ARM_HAVE_V4SF_LDST, ARM_HAVE_DI_LDST): Likewise.
(ARM_HAVE_V2DI_LDST): Likewise.
* config/arm/mve.md (*movmisalign<mode>_mve_store): New pattern.
(*movmisalign<mode>_mve_load): New pattern.
* config/arm/neon.md (movmisalign<mode>): Move to ...
* config/arm/vec-common.md: ... here.
PR target/97875
gcc/testsuite/
* gcc.target/arm/simd/mve-vneg.c: Update test.
Vladimir N. Makarov [Tue, 12 Jan 2021 16:26:15 +0000 (11:26 -0500)]
[PR97969] LRA: Transform pattern `plus (plus (hard reg, const), pseudo)` after elimination
LRA can loop infinitely on targets without `reg + imm` insns. Register elimination
on such targets can increase register pressure resulting in permanent
stack size increase and changing elimination offset. To avoid such situation, a simple
transformation can be done to avoid register pressure increase after
generating reload insns containing eliminated hard regs.
gcc/ChangeLog:
PR target/97969
* lra-eliminations.c (eliminate_regs_in_insn): Add transformation
of pattern 'plus (plus (hard reg, const), pseudo)'.
gcc/testsuite/ChangeLog:
PR target/97969
* gcc.target/arm/pr97969.c: New.
Patrick Palka [Tue, 12 Jan 2021 14:34:41 +0000 (09:34 -0500)]
c++: Fix ICE with CTAD in concept [PR98611]
This patch teaches cp_walk_subtrees to visit the template represented
by a CTAD placeholder, which would otherwise be not visited during
find_template_parameters. The template may be a template template
parameter (as in the first testcase), or it may implicitly use the
template parameters of an enclosing class template (as in the second
testcase), and in either case we need to visit this tree to record the
template parameters used therein for later satisfaction.
gcc/cp/ChangeLog:
PR c++/98611
* tree.c (cp_walk_subtrees) <case TEMPLATE_TYPE_PARM>: Visit
the template of a CTAD placeholder.
gcc/testsuite/ChangeLog:
PR c++/98611
* g++.dg/cpp2a/concepts-ctad1.C: New test.
* g++.dg/cpp2a/concepts-ctad2.C: New test.
Richard Biener [Tue, 12 Jan 2021 10:17:33 +0000 (11:17 +0100)]
tree-optimization/98550 - fix BB vect unrolling check
This fixes the check that disqualifies BB vectorization because of
required unrolling to match up with the later exact_div we do. To
not disable the ability to split groups that do not match up
exactly with a choosen vector type this also introduces a soft-fail
mechanism to vect_build_slp_tree_1 which delays failing to after
the matches[] array is populated from other checks and only then
determines the split point according to the vector type.
2021-01-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/98550
* tree-vect-slp.c (vect_record_max_nunits): Check whether
the group size is a multiple of the vector element count.
(vect_build_slp_tree_1): When we need to fail because
the vector type choosen causes unrolling do so lazily
without affecting matches only at the end to guide group splitting.
* g++.dg/opt/pr98550.C: New testcase.
Martin Liska [Tue, 12 Jan 2021 12:20:18 +0000 (13:20 +0100)]
options: properly compare string arguments
Similarly to
7f967bd2a7ba156ede3fbb147e66dea5fb7137a6, we need to
compare string with strcmp.
gcc/ChangeLog:
PR c++/97284
* optc-save-gen.awk: Compare also n_target_save vars with
strcmp.
Martin Liska [Tue, 12 Jan 2021 10:27:34 +0000 (11:27 +0100)]
gcov: add more debugging facility
gcc/ChangeLog:
* gcov.c (source_info::debug): New.
(print_usage): Add --debug (-D) option.
(process_args): Likewise.
(generate_results): Call src->debug after
accumulate_line_counts.
(read_graph_file): Properly assign id for EXIT_BLOCK.
* profile.c (branch_prob): Dump function body before it is
instrumented.
Jakub Jelinek [Tue, 12 Jan 2021 10:04:46 +0000 (11:04 +0100)]
widening_mul: Fix up ICE caused by my signed multiplication overflow pattern recognition changes [PR98629]
As the testcase shows, my latest changes caused ICE on that testcase.
The problem is that arith_overflow_check_p now can change the use_stmt
argument (has a reference), so that if it succeeds (returns non-zero),
it points it to the GIMPLE_COND or EQ/NE or COND_EXPR assignment from the
TRUNC_DIV_EXPR assignment.
The problem was that it would change use_stmt also if it returned 0 in some
cases, such as multiple imm uses of the division, and in one of the callers
if arith_overflow_check_p returns 0 it looks at use_stmt again and performs
other checks, which of course assumes that use_stmt is the one passed
to arith_overflow_check_p and not e.g. NULL instead or some other unrelated
stmt.
The following patch fixes that by only changing use_stmt when we are about
to return non-zero (for the MULT_EXPR case, which is the only one with the
need to use different use_stmt).
2021-01-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/98629
* tree-ssa-math-opts.c (arith_overflow_check_p): Don't update use_stmt
unless returning non-zero.
* gcc.c-torture/compile/pr98629.c: New test.
Jakub Jelinek [Tue, 12 Jan 2021 10:03:40 +0000 (11:03 +0100)]
reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 etc. [PR95731]
We already had x != 0 && y != 0 to (x | y) != 0 and
x != -1 && y != -1 to (x & y) != -1 and
x < 32U && y < 32U to (x | y) < 32U, this patch adds signed
x < 0 && y < 0 to (x | y) < 0. In that case, the low/high seem to be
always the same and just in_p indices whether it is >= 0 or < 0,
also, all types in the same bucket (same precision) should be type
compatible, but we can have some >= 0 and some < 0 comparison mixed,
so the patch handles that by using the right BIT_IOR_EXPR or BIT_AND_EXPR
and doing one set of < 0 or >= 0 first, then BIT_NOT_EXPR and then the other
one. I had to move optimize_range_tests_var_bound before this optimization
because that one deals with signed a >= 0 && a < b, and limited it to the
last reassoc pass as reassoc itself can't virtually undo this optimization
yet (and not sure if vrp would be able to).
2021-01-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/95731
* tree-ssa-reassoc.c (optimize_range_tests_cmp_bitwise): Also optimize
x < 0 && y < 0 && z < 0 into (x | y | z) < 0 for signed x, y, z.
(optimize_range_tests): Call optimize_range_tests_cmp_bitwise
only after optimize_range_tests_var_bound.
* gcc.dg/tree-ssa/pr95731.c: New test.
* gcc.c-torture/execute/pr95731.c: New test.
Jakub Jelinek [Tue, 12 Jan 2021 10:02:16 +0000 (11:02 +0100)]
configure, make: Fix up --enable-link-serialization
As reported by Matthias, --enable-link-serialization=1 can currently start
two concurrent links first (e.g. gnat1 and cc1).
The problem is that make var = value values seem to work differently between
dependencies and actual rules (where it was tested).
As the language make fragments can be in different order, we can have:
ada.prev = ... magic that will become $(c.serial) under --enable-link-serialization=1
gnat1$(exe): ..... $(ada.prev)
...
c.serial = cc1$(exe)
and while if I add echo $(ada.prev) in the gnat1 rule's command, it prints
cc1, the dependencies are actually evaluated during reading of the goal or
when.
The configure creates (and puts into Makefile) some serialization order of
the languages and in that order c always comes first, and the rest is
actually sorted the way the all_lang_makefrags are already sorted,
so just by forcing c/Make-lang.in first we achieve that X.serial variable
is always defined before some other Y.prev will use it in its goal
dependencies.
2021-01-12 Jakub Jelinek <jakub@redhat.com>
* configure.ac: Ensure c/Make-lang.in comes first in @all_lang_makefrags@.
* configure: Regenerated.
Qian Jianhua [Tue, 12 Jan 2021 07:32:43 +0000 (15:32 +0800)]
MAINTAINERS: Add myself for write after approval
ChangeLog:
2021-01-12 Qian Jianhua <qianjh@cn.fujitsu.com>
* MAINTAINERS (Write After Approval): Add myself
Marek Polacek [Mon, 11 Jan 2021 16:44:36 +0000 (11:44 -0500)]
c++: -Wmissing-field-initializers in unevaluated ctx [PR98620]
This PR wants us not to warn about missing field initializers when
the code in question takes places in decltype and similar. Fixed
thus.
gcc/cp/ChangeLog:
PR c++/98620
* typeck2.c (process_init_constructor_record): Don't emit
-Wmissing-field-initializers warnings in unevaluated contexts.
gcc/testsuite/ChangeLog:
PR c++/98620
* g++.dg/warn/Wmissing-field-initializers-2.C: New test.
liuhongt [Mon, 11 Jan 2021 06:47:49 +0000 (14:47 +0800)]
Delete dead code in ix86_expand_sse_comi.
d->flag is always 0 for builtins located in
BDESC_FIRST (comi,COMI,...)
...
BDESC_END (COMI, PCMPESTR)
gcc/ChangeLog:
PR target/98612
* config/i386/i386-builtins.h (BUILTIN_DESC_SWAP_OPERANDS):
Deleted.
* config/i386/i386-expand.c (ix86_expand_sse_comi): Delete
dead code.
Alexandre Oliva [Tue, 12 Jan 2021 02:37:59 +0000 (23:37 -0300)]
make FOR_EACH_IMM_USE_STMT safe for early exits
Use a dtor to automatically remove ITER from IMM_USE list in
FOR_EACH_IMM_USE_STMT.
for gcc/ChangeLog
* ssa-iterators.h (end_imm_use_stmt_traverse): Forward
declare.
(auto_end_imm_use_stmt_traverse): New struct.
(FOR_EACH_IMM_USE_STMT): Use it.
(BREAK_FROM_IMM_USE_STMT, RETURN_FROM_IMM_USE_STMT): Remove,
along with uses...
* gimple-ssa-strength-reduction.c: ... here, ...
* graphite-scop-detection.c: ... here, ...
* ipa-modref.c, ipa-pure-const.c, ipa-sra.c: ... here, ...
* tree-predcom.c, tree-ssa-ccp.c: ... here, ...
* tree-ssa-dce.c, tree-ssa-dse.c: ... here, ...
* tree-ssa-loop-ivopts.c, tree-ssa-math-opts.c: ... here, ...
* tree-ssa-phiprop.c, tree-ssa.c: ... here, ...
* tree-vect-slp.c: ... and here, ...
* doc/tree-ssa.texi: ... and the example here.
David Malcolm [Tue, 12 Jan 2021 01:23:41 +0000 (20:23 -0500)]
analyzer: fix ICE merging dereferencing unknown ptrs [PR98628]
gcc/analyzer/ChangeLog:
PR analyzer/98628
* store.cc (binding_cluster::make_unknown_relative_to): Don't mark
dereferenced unknown pointers as having escaped.
gcc/testsuite/ChangeLog:
PR analyzer/98628
* gcc.dg/analyzer/pr98628.c: New test.
GCC Administrator [Tue, 12 Jan 2021 00:16:22 +0000 (00:16 +0000)]
Daily bump.
Richard Sandiford [Mon, 11 Jan 2021 18:03:26 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE ASRD
This patch adds support for both conditional and unconditional unpacked
ASRD. This meant adding a new define_insn for the unconditional form,
instead of reusing the conditional instructions. It also meant
extending the current conditional patterns to support merging with
any independent value, not just zero.
gcc/
* config/aarch64/aarch64-sve.md (sdiv_pow2<mode>3): Extend from
SVE_FULL_I to SVE_I. Generate an UNSPEC_PRED_X.
(*sdiv_pow2<mode>3): New pattern.
(@cond_<sve_int_op><mode>): Extend from SVE_FULL_I to SVE_I.
Wrap the ASRD in an UNSPEC_PRED_X.
(*cond_<sve_int_op><mode>_2): Likewise. Replace the UNSPEC_PRED_X
predicate with a constant PTRUE, if it isn't already.
(*cond_<sve_int_op><mode>_z): Replace with...
(*cond_<sve_int_op><mode>_any): ...this new pattern.
gcc/testsuite/
* gcc.target/aarch64/sve/asrdiv_4.c: New test.
* gcc.target/aarch64/sve/cond_asrd_1.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_2.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_3.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_3_run.c: Likewise.
Richard Sandiford [Mon, 11 Jan 2021 18:03:25 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE conditional BIC
This patch adds support for unpacked conditional BIC. The type suffix
could be taken from the element size or the container size, so the
patch continues to use the element size. This is consistent with
the existing support for unconditional BIC.
gcc/
* config/aarch64/aarch64-sve.md (*cond_bic<mode>_2): Extend from
SVE_FULL_I to SVE_I.
(*cond_bic<mode>_any): Likewise.
gcc/testsuite/
* g++.target/aarch64/sve/cond_bic_1.C: New test.
* g++.target/aarch64/sve/cond_bic_2.C: Likewise.
* g++.target/aarch64/sve/cond_bic_3.C: Likewise.
* g++.target/aarch64/sve/cond_bic_4.C: Likewise.
Richard Sandiford [Mon, 11 Jan 2021 18:03:24 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE MULH
This patch extends the SMULH and UMULH support to unpacked vectors.
The type suffix must be taken from the element size rather than the
container size.
The main use of these patterns is to support division and modulus
by a constant. The conditional forms would be hard to trigger from
non-ACLE code, and ACLE code needs fully-packed vectors only.
gcc/
* config/aarch64/aarch64-sve.md (<su>mul<mode>3_highpart)
(@aarch64_pred_<MUL_HIGHPART:optab><mode>): Extend from SVE_FULL_I
to SVE_I.
gcc/testsuite/
* gcc.target/aarch64/sve/mul_highpart_3.c: New test.
Richard Sandiford [Mon, 11 Jan 2021 18:03:23 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE ABD
This patch adds support for unpacked SVE SABD and UABD.
It also rewrites the patterns so that they match as combine
patterns without the need for REG_EQUAL notes. Finally,
there was no pattern for merging with the second input,
which can be handled by reversing the operands.
The type suffix needs to be taken from the element size rather
than the container size.
gcc/
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Extend from
SVE_FULL_I to SVE_I.
(*aarch64_cond_<su>abd<mode>_2): Likewise.
(*aarch64_cond_<su>abd<mode>_any): Likewise.
(@aarch64_pred_<su>abd<mode>): Likewise. Use UNSPEC_PRED_X
for the max and min but not for the minus.
(*aarch64_cond_<su>abd<mode>_3): New pattern.
gcc/testsuite/
* g++.target/aarch64/sve/abd_1.C: New test.
* g++.target/aarch64/sve/cond_abd_1.C: Likewise.
* g++.target/aarch64/sve/cond_abd_2.C: Likewise.
* g++.target/aarch64/sve/cond_abd_3.C: Likewise.
* g++.target/aarch64/sve/cond_abd_4.C: Likewise.