litex.git
4 years agoMerge branch 'master' of https://github.com/enjoy-digital/litex
Florent Kermarrec [Mon, 2 Mar 2020 08:31:45 +0000 (09:31 +0100)]
Merge branch 'master' of https://github.com/enjoy-digital/litex

4 years agointegration/soc_core: change disable parameters to no-xxyy.
Florent Kermarrec [Mon, 2 Mar 2020 08:31:32 +0000 (09:31 +0100)]
integration/soc_core: change disable parameters to no-xxyy.

4 years agoMerge pull request #405 from sajattack/sifive-triple
enjoy-digital [Mon, 2 Mar 2020 08:30:05 +0000 (09:30 +0100)]
Merge pull request #405 from sajattack/sifive-triple

add riscv-sifive-elf triple

4 years agointegration/soc: add auto_int type and use it on all int parameters.
Florent Kermarrec [Mon, 2 Mar 2020 08:07:31 +0000 (09:07 +0100)]
integration/soc: add auto_int type and use it on all int parameters.

Allow passing parameters as int or hex values.

4 years agotargets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.
Florent Kermarrec [Mon, 2 Mar 2020 08:01:05 +0000 (09:01 +0100)]
targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.

4 years agointegration/soc: add ethphy CSR in target.
Florent Kermarrec [Mon, 2 Mar 2020 07:42:59 +0000 (08:42 +0100)]
integration/soc: add ethphy CSR in target.

4 years agotargets/nexys4ddr: use soc.add_ethernet method.
Florent Kermarrec [Sun, 1 Mar 2020 19:50:44 +0000 (20:50 +0100)]
targets/nexys4ddr: use soc.add_ethernet method.

4 years agointegration/soc: add add_ethernet method.
Florent Kermarrec [Sun, 1 Mar 2020 19:50:13 +0000 (20:50 +0100)]
integration/soc: add add_ethernet method.

4 years agointegration/soc: mode litedram imports to add_sdram, remove some separators.
Florent Kermarrec [Sun, 1 Mar 2020 17:58:55 +0000 (18:58 +0100)]
integration/soc: mode litedram imports to add_sdram, remove some separators.

4 years agoadd riscv-sifive-elf triple
Paul Sajna [Sun, 1 Mar 2020 09:39:03 +0000 (01:39 -0800)]
add riscv-sifive-elf triple

4 years agotest/test_targets: use uart-name=stub.
Florent Kermarrec [Sat, 29 Feb 2020 10:07:06 +0000 (11:07 +0100)]
test/test_targets: use uart-name=stub.

4 years agosoc/uart: add configurable UART FIFO depth.
Florent Kermarrec [Fri, 28 Feb 2020 21:34:11 +0000 (22:34 +0100)]
soc/uart: add configurable UART FIFO depth.

4 years agocores/uart: cleanup
Florent Kermarrec [Fri, 28 Feb 2020 21:11:51 +0000 (22:11 +0100)]
cores/uart: cleanup

4 years agosoc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
Florent Kermarrec [Fri, 28 Feb 2020 21:03:40 +0000 (22:03 +0100)]
soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.

4 years agointerconnect/stream/SyncFIFO: allow depth down to 0.
Florent Kermarrec [Fri, 28 Feb 2020 19:03:47 +0000 (20:03 +0100)]
interconnect/stream/SyncFIFO: allow depth down to 0.

4 years agointerconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.
Florent Kermarrec [Fri, 28 Feb 2020 15:33:18 +0000 (16:33 +0100)]
interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.

4 years agointerconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
Florent Kermarrec [Fri, 28 Feb 2020 15:25:09 +0000 (16:25 +0100)]
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.

4 years agointerconnect/axi: set default data_width/address_width to 32-bit.
Florent Kermarrec [Fri, 28 Feb 2020 12:19:10 +0000 (13:19 +0100)]
interconnect/axi: set default data_width/address_width to 32-bit.

4 years agotargets: default to trellis toolchain on all ECP5 targets (now able to build all...
Florent Kermarrec [Fri, 28 Feb 2020 08:48:48 +0000 (09:48 +0100)]
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).

4 years agocores/gpio: use separate TSTriple for each bit.
Florent Kermarrec [Fri, 28 Feb 2020 08:10:28 +0000 (09:10 +0100)]
cores/gpio: use separate TSTriple for each bit.

This fixes per bit OE control.

4 years agolattice/yosys: don't use quiet operation since logs are useful and for consistency...
Florent Kermarrec [Fri, 28 Feb 2020 07:32:29 +0000 (08:32 +0100)]
lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.

4 years agotargets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
Florent Kermarrec [Thu, 27 Feb 2020 12:00:35 +0000 (13:00 +0100)]
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.

4 years agosoftware/bios/sdram: allow setting CLK/CMD delay from user design and configure it...
Florent Kermarrec [Thu, 27 Feb 2020 11:25:37 +0000 (12:25 +0100)]
software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling.

Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:

Before (delay = 0 taps):
Write leveling:
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: 00
m5: |11111111110000000000000111| delay: 00
m6: |11111111111000000000000001| delay: 00
m7: |11111111111000000000000011| delay: 00

After (delay = 12 taps):
Write leveling:
m0: |11111111111111000000000000| delay: 00
m1: |11111111111100000000000001| delay: 00
m2: |00011111111111110000000000| delay: 03
m3: |00011111111111110000000000| delay: 03
m4: |00000000111111111111110000| delay: 08
m5: |00000000111111111111110000| delay: 08
m6: |00000000001111111111111000| delay: 10
m7: |00000000001111111111111000| delay: 10

4 years agoboards: keep in sync with LiteX-boards
Florent Kermarrec [Thu, 27 Feb 2020 10:18:14 +0000 (11:18 +0100)]
boards: keep in sync with LiteX-boards

4 years agointerconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
Florent Kermarrec [Wed, 26 Feb 2020 14:13:16 +0000 (15:13 +0100)]
interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)

4 years agointegration/soc: -x on soc.py
Florent Kermarrec [Wed, 26 Feb 2020 13:43:01 +0000 (14:43 +0100)]
integration/soc: -x on soc.py

4 years agosoc/cores/bitbang: fix missing self.comb on miso.
Florent Kermarrec [Tue, 25 Feb 2020 14:56:27 +0000 (15:56 +0100)]
soc/cores/bitbang: fix missing self.comb on miso.

4 years agoMerge pull request #402 from antmicro/litex-gen-fix-uart-pins
enjoy-digital [Tue, 25 Feb 2020 14:53:13 +0000 (15:53 +0100)]
Merge pull request #402 from antmicro/litex-gen-fix-uart-pins

tools: litex_gen: fix missing UART pins

4 years agosoftware: disable LTO with LM32 (not supported by old GCC versions easily available).
Florent Kermarrec [Tue, 25 Feb 2020 14:31:27 +0000 (15:31 +0100)]
software: disable LTO with LM32 (not supported by old GCC versions easily available).

4 years agoMerge pull request #401 from antmicro/enable-lto
enjoy-digital [Tue, 25 Feb 2020 14:32:12 +0000 (15:32 +0100)]
Merge pull request #401 from antmicro/enable-lto

software: enable link time optimization (LTO)

4 years agotools: litex_gen: fix missing UART pins
Jan Kowalewski [Tue, 25 Feb 2020 13:24:29 +0000 (14:24 +0100)]
tools: litex_gen: fix missing UART pins

4 years agosoftware: enable link time optimization (LTO)
Tim 'mithro' Ansell [Tue, 27 Nov 2018 08:48:44 +0000 (00:48 -0800)]
software: enable link time optimization (LTO)

Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
4 years agoMerge pull request #400 from Xiretza/ecp5-pll-freqfix
enjoy-digital [Mon, 24 Feb 2020 13:49:35 +0000 (14:49 +0100)]
Merge pull request #400 from Xiretza/ecp5-pll-freqfix

Fix ECP5PLL VCO frequency range

4 years agoFix ECP5PLL VCO frequency range
Xiretza [Mon, 24 Feb 2020 13:39:44 +0000 (14:39 +0100)]
Fix ECP5PLL VCO frequency range

See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".

4 years agointegration/soc: improve presentation of SoCLocHandler's locations.
Florent Kermarrec [Mon, 24 Feb 2020 12:37:38 +0000 (13:37 +0100)]
integration/soc: improve presentation of SoCLocHandler's locations.

4 years agointerconnect/axi: remove bus_name on connect_to_pads
Florent Kermarrec [Mon, 24 Feb 2020 12:24:32 +0000 (13:24 +0100)]
interconnect/axi: remove bus_name on connect_to_pads

4 years agotools/litex_gen: add bus parameter and AXI (Lite) support.
Florent Kermarrec [Mon, 24 Feb 2020 11:49:42 +0000 (12:49 +0100)]
tools/litex_gen: add bus parameter and AXI (Lite) support.

4 years agolitex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
Florent Kermarrec [Mon, 24 Feb 2020 11:48:52 +0000 (12:48 +0100)]
litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.

4 years agolitex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.
Florent Kermarrec [Mon, 24 Feb 2020 10:58:27 +0000 (11:58 +0100)]
litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.

4 years agotools: rename litex_extract to litex_gen (use similar name than litedram/liteeth...
Florent Kermarrec [Mon, 24 Feb 2020 09:25:18 +0000 (10:25 +0100)]
tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify.

4 years agoMerge pull request #396 from antmicro/external-wb
enjoy-digital [Mon, 24 Feb 2020 09:01:16 +0000 (10:01 +0100)]
Merge pull request #396 from antmicro/external-wb

Add a script that allows to generate standalone cores

4 years agoMerge pull request #397 from gsomlo/gls-csr-volatile
enjoy-digital [Fri, 21 Feb 2020 20:08:22 +0000 (21:08 +0100)]
Merge pull request #397 from gsomlo/gls-csr-volatile

Add 'volatile' qualifier to new CSR accessors

4 years agoAdd 'volatile' qualifier to new CSR accessors
Gabriel Somlo [Thu, 6 Feb 2020 23:30:22 +0000 (18:30 -0500)]
Add 'volatile' qualifier to new CSR accessors

Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.

Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.

No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
4 years agotools: add script for extracting wishbone cores
Piotr Binkowski [Fri, 21 Feb 2020 13:43:15 +0000 (14:43 +0100)]
tools: add script for extracting wishbone cores

4 years agoaxi: add to_pads method
Karol Gugala [Mon, 3 Feb 2020 13:38:24 +0000 (14:38 +0100)]
axi: add to_pads method

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
4 years agowishbone: add extracting module signals to the top
Jan Kowalewski [Thu, 13 Feb 2020 15:41:11 +0000 (16:41 +0100)]
wishbone: add extracting module signals to the top

4 years agodoc/socdoc: fix example
Florent Kermarrec [Thu, 20 Feb 2020 18:47:15 +0000 (19:47 +0100)]
doc/socdoc: fix example

4 years agocpu/blackparrot: first cleanup pass
Florent Kermarrec [Thu, 20 Feb 2020 17:50:13 +0000 (18:50 +0100)]
cpu/blackparrot: first cleanup pass

4 years agointegration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with...
Florent Kermarrec [Thu, 20 Feb 2020 15:16:07 +0000 (16:16 +0100)]
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.

4 years agobuild/sim: add Verilator FST tracing support.
Florent Kermarrec [Thu, 20 Feb 2020 12:46:39 +0000 (13:46 +0100)]
build/sim: add Verilator FST tracing support.

4 years agoMerge pull request #390 from gsomlo/gls-add-sdcard
enjoy-digital [Thu, 20 Feb 2020 07:17:54 +0000 (08:17 +0100)]
Merge pull request #390 from gsomlo/gls-add-sdcard

Import LiteSDCard support in to LiteX, using nexys4ddr as the initial test target

4 years agotargets/nexys4ddr: add optional sdcard support
Gabriel Somlo [Thu, 20 Feb 2020 01:14:10 +0000 (20:14 -0500)]
targets/nexys4ddr: add optional sdcard support

Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agobios: add litesdcard test routines to boot menu
Gabriel Somlo [Wed, 8 Jan 2020 17:49:52 +0000 (12:49 -0500)]
bios: add litesdcard test routines to boot menu

This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agotargets/nexys4ddr: add ethernet via method instead of inheritance
Gabriel Somlo [Thu, 20 Feb 2020 01:10:32 +0000 (20:10 -0500)]
targets/nexys4ddr: add ethernet via method instead of inheritance

Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agosoc_core: fix missing init on main_ram
Florent Kermarrec [Wed, 19 Feb 2020 13:58:55 +0000 (14:58 +0100)]
soc_core: fix missing init on main_ram

4 years agoMerge pull request #389 from antmicro/linux_flash_offsets
enjoy-digital [Tue, 18 Feb 2020 16:54:13 +0000 (17:54 +0100)]
Merge pull request #389 from antmicro/linux_flash_offsets

bios/boot: allow to customize flash offsets of Linux images

4 years agocores/cpu: use standard+debug variant when only debug is specified.
Florent Kermarrec [Tue, 18 Feb 2020 15:59:55 +0000 (16:59 +0100)]
cores/cpu: use standard+debug variant when only debug is specified.

4 years agobios/boot: allow to customize flash offsets of Linux images
Mateusz Holenko [Mon, 17 Feb 2020 15:52:08 +0000 (16:52 +0100)]
bios/boot: allow to customize flash offsets of Linux images

4 years agosoc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
Florent Kermarrec [Tue, 18 Feb 2020 09:15:01 +0000 (10:15 +0100)]
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL

4 years agosoc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width...
Florent Kermarrec [Tue, 18 Feb 2020 08:11:40 +0000 (09:11 +0100)]
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)

4 years agointegration/soc: improve Region logger
Florent Kermarrec [Tue, 18 Feb 2020 07:27:59 +0000 (08:27 +0100)]
integration/soc: improve Region logger

4 years agobios/boot: update and fix flashboot, improve verbosity
Florent Kermarrec [Mon, 17 Feb 2020 18:21:35 +0000 (19:21 +0100)]
bios/boot: update and fix flashboot, improve verbosity

4 years agosoc: increase supporteds address_width/paging
Florent Kermarrec [Mon, 17 Feb 2020 07:36:36 +0000 (08:36 +0100)]
soc: increase supporteds address_width/paging

4 years agosoc_core: expose CSR paging
Florent Kermarrec [Mon, 17 Feb 2020 07:34:10 +0000 (08:34 +0100)]
soc_core: expose CSR paging

4 years agosoc/csr_bus: improve CSR paging genericity
Florent Kermarrec [Mon, 17 Feb 2020 07:28:56 +0000 (08:28 +0100)]
soc/csr_bus: improve CSR paging genericity

4 years agotools/litex_sim: use new sdram verbosity parameter
Florent Kermarrec [Sun, 16 Feb 2020 15:09:06 +0000 (16:09 +0100)]
tools/litex_sim: use new sdram verbosity parameter

4 years agointegration/soc: add configurable CSR Paging
Florent Kermarrec [Sun, 16 Feb 2020 11:32:05 +0000 (12:32 +0100)]
integration/soc: add configurable CSR Paging

4 years agosoc_core: add back identifier
Florent Kermarrec [Sat, 15 Feb 2020 18:04:47 +0000 (19:04 +0100)]
soc_core: add back identifier

4 years agoMerge pull request #387 from BracketMaster/master
enjoy-digital [Sat, 15 Feb 2020 16:05:50 +0000 (17:05 +0100)]
Merge pull request #387 from BracketMaster/master

litex_sim now working on MacOS and Linux

4 years agoupdate to work with mac
Yehowshua Immanuel [Fri, 14 Feb 2020 22:53:25 +0000 (17:53 -0500)]
update to work with mac

4 years agotools/litex_sim: specify default local/remote-ip addresses.
Florent Kermarrec [Sat, 15 Feb 2020 13:04:44 +0000 (14:04 +0100)]
tools/litex_sim: specify default local/remote-ip addresses.

4 years agotools/litex_sim: add ethernet local/remote-ip arguments.
Florent Kermarrec [Sat, 15 Feb 2020 13:01:46 +0000 (14:01 +0100)]
tools/litex_sim: add ethernet local/remote-ip arguments.

4 years agointerconnect/stream: cleanup imports/idents
Florent Kermarrec [Fri, 14 Feb 2020 07:08:19 +0000 (08:08 +0100)]
interconnect/stream: cleanup imports/idents

4 years agoMerge pull request #386 from antmicro/sdram-timing-checker
enjoy-digital [Thu, 13 Feb 2020 15:53:12 +0000 (16:53 +0100)]
Merge pull request #386 from antmicro/sdram-timing-checker

tools/litex_sim: add cli options to control SDRAM timing checker

4 years agotools/litex_sim: add cli options to control SDRAM timing checker
Piotr Binkowski [Thu, 13 Feb 2020 13:45:15 +0000 (14:45 +0100)]
tools/litex_sim: add cli options to control SDRAM timing checker

4 years agosoc_core: fix cpu_variant renaming regression
Florent Kermarrec [Thu, 13 Feb 2020 07:34:16 +0000 (08:34 +0100)]
soc_core: fix cpu_variant renaming regression

4 years agodoc: rename lxsocdoc -> socdoc and update readme
Sean Cross [Thu, 13 Feb 2020 00:47:58 +0000 (08:47 +0800)]
doc: rename lxsocdoc -> socdoc and update readme

With the merge of lxsocdoc into upstream litex, the old name of
"lxsocdoc" doesn't make as much sense.  Additionally, the import paths
are now different.

Rename this file to reflect the new home of `soc/doc`, and update the
code examples to work with the new name.

Signed-off-by: Sean Cross <sean@xobs.io>
4 years agodoc: fix regression with new irq manager
Sean Cross [Thu, 13 Feb 2020 00:32:44 +0000 (08:32 +0800)]
doc: fix regression with new irq manager

Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts.  This has been subsumed
into a more general `irq` object that manages the interrupts.

Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.

This fixes #385.

Signed-off-by: Sean Cross <sean@xobs.io>
4 years agosoc/CSR: show alignment in report and add info when updating.
Florent Kermarrec [Wed, 12 Feb 2020 20:55:30 +0000 (21:55 +0100)]
soc/CSR: show alignment in report and add info when updating.

4 years agosoc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
Florent Kermarrec [Wed, 12 Feb 2020 20:25:20 +0000 (21:25 +0100)]
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket

4 years agointegration/soc: fix refactoring issues
Florent Kermarrec [Wed, 12 Feb 2020 17:16:38 +0000 (18:16 +0100)]
integration/soc: fix refactoring issues

4 years agosoc/integration/builder: update copyright, align arguments
Florent Kermarrec [Wed, 12 Feb 2020 15:43:11 +0000 (16:43 +0100)]
soc/integration/builder: update copyright, align arguments

4 years agoMerge pull request #383 from Xiretza/builder-directories
enjoy-digital [Wed, 12 Feb 2020 15:38:04 +0000 (16:38 +0100)]
Merge pull request #383 from Xiretza/builder-directories

Unify output directory handling in builder

4 years agoUnify output directory handling in builder
Xiretza [Wed, 12 Feb 2020 13:35:23 +0000 (14:35 +0100)]
Unify output directory handling in builder

4 years agoMerge pull request #382 from enjoy-digital/new_soc
enjoy-digital [Tue, 11 Feb 2020 17:39:33 +0000 (18:39 +0100)]
Merge pull request #382 from enjoy-digital/new_soc

Add new SoC/LiteXSoC classes and use it for SoCCore/SoCSDRAM

4 years agosoc_core/soc_sdram: add disclaimer
Florent Kermarrec [Tue, 11 Feb 2020 17:28:05 +0000 (18:28 +0100)]
soc_core/soc_sdram: add disclaimer

4 years agosoc_core: provide full retro-compatibily when add_wb_slave is called before add_memor...
Florent Kermarrec [Tue, 11 Feb 2020 17:21:41 +0000 (18:21 +0100)]
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region

4 years agosoc: fix busword typo
Florent Kermarrec [Tue, 11 Feb 2020 16:50:26 +0000 (17:50 +0100)]
soc: fix busword typo

4 years agotargets/EthernetSoC: be sure memory region is added before adding Wishbone Slave...
Florent Kermarrec [Tue, 11 Feb 2020 16:44:24 +0000 (17:44 +0100)]
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)

4 years agoMerge branch 'master' into new_soc
enjoy-digital [Tue, 11 Feb 2020 16:22:06 +0000 (17:22 +0100)]
Merge branch 'master' into new_soc

4 years agosoc/integration: move mem_decoder to soc_core
Florent Kermarrec [Tue, 11 Feb 2020 16:19:22 +0000 (17:19 +0100)]
soc/integration: move mem_decoder to soc_core

4 years agosoc/integration/common: simplify get_version
Florent Kermarrec [Tue, 11 Feb 2020 16:16:24 +0000 (17:16 +0100)]
soc/integration/common: simplify get_version

4 years agosoc/add_uart: fix bridge
Florent Kermarrec [Tue, 11 Feb 2020 15:55:37 +0000 (16:55 +0100)]
soc/add_uart: fix bridge

4 years agosoc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
Florent Kermarrec [Tue, 11 Feb 2020 15:44:17 +0000 (16:44 +0100)]
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)

4 years agosoc: avoid double definition of main_ram
Florent Kermarrec [Tue, 11 Feb 2020 15:39:37 +0000 (16:39 +0100)]
soc: avoid double definition of main_ram

4 years agosoc: improve log colors on error reporting
Florent Kermarrec [Tue, 11 Feb 2020 15:24:57 +0000 (16:24 +0100)]
soc: improve log colors on error reporting

4 years agosoc: add linker regions management
Florent Kermarrec [Tue, 11 Feb 2020 14:28:02 +0000 (15:28 +0100)]
soc: add linker regions management

4 years agosoc: improve log presentation/colors
Florent Kermarrec [Tue, 11 Feb 2020 13:50:16 +0000 (14:50 +0100)]
soc: improve log presentation/colors

4 years agosoc: fix cpu_reset_address
Florent Kermarrec [Tue, 11 Feb 2020 13:17:32 +0000 (14:17 +0100)]
soc: fix cpu_reset_address

4 years agotools/litex_sim_new: remove
Florent Kermarrec [Tue, 11 Feb 2020 13:05:01 +0000 (14:05 +0100)]
tools/litex_sim_new: remove