nmigen.git
2 years agoworking on implementing smtlib2
Jacob Lifshay [Fri, 20 May 2022 04:53:16 +0000 (21:53 -0700)]
working on implementing smtlib2

2 years agoMerge branch 'add-missing-prst-pins' into smtlib2-expr-support
Jacob Lifshay [Fri, 20 May 2022 02:18:15 +0000 (19:18 -0700)]
Merge branch 'add-missing-prst-pins' into smtlib2-expr-support

2 years agoadd missing *_prst pins
Jacob Lifshay [Fri, 20 May 2022 02:08:43 +0000 (19:08 -0700)]
add missing *_prst pins

2 years agoworking on adding smtlib2 expression support
Jacob Lifshay [Thu, 19 May 2022 08:00:01 +0000 (01:00 -0700)]
working on adding smtlib2 expression support

2 years agoimprove gpio.py basic example by passing in a list of pins.
Luke Kenneth Casson Leighton [Thu, 12 May 2022 09:14:04 +0000 (10:14 +0100)]
improve gpio.py basic example by passing in a list of pins.
the previous version was a little... odd: enumerating the actual bits
of an 8-bit Signal as an Array

2 years agoremove SIM_DEVICES parameter temporarily which is not in
Luke Kenneth Casson Leighton [Mon, 9 May 2022 11:25:28 +0000 (12:25 +0100)]
remove SIM_DEVICES parameter temporarily which is not in
v2016.2.
https://gitlab.com/nmigen/nmigen/-/issues/4

2 years agoadd override options to nextpnr-xilinx
Luke Kenneth Casson Leighton [Tue, 3 May 2022 08:59:43 +0000 (09:59 +0100)]
add override options to nextpnr-xilinx
(identical method to nextpnr-ecp5)

2 years agocleanup on nextpnr-xilinx setup
Luke Kenneth Casson Leighton [Sun, 1 May 2022 10:45:58 +0000 (11:45 +0100)]
cleanup on nextpnr-xilinx setup
* use rtlil instead of verilog (top.il not top.v)
* similar to nextpnr-ecp5 write out a top.ys file
* add top.tim and top.rpt outputting into build and set "quiet"

2 years agocross-reference to symbiyosys in README,
Luke Kenneth Casson Leighton [Sun, 1 May 2022 10:13:25 +0000 (11:13 +0100)]
cross-reference to symbiyosys in README,
mentioning that Formal Correctness Proofs may be written and run from nmigen

2 years agoset nextpnr-xilinx seed 1 for deterministic behaviour
Luke Kenneth Casson Leighton [Mon, 25 Apr 2022 14:42:08 +0000 (15:42 +0100)]
set nextpnr-xilinx seed 1 for deterministic behaviour
may be over-ridden with an argument override adding an additional
--seed {value}

2 years agoannoying typo
Luke Kenneth Casson Leighton [Fri, 15 Apr 2022 10:02:35 +0000 (11:02 +0100)]
annoying typo

2 years agoadd input and output reset signals to Pin
Luke Kenneth Casson Leighton [Fri, 15 Apr 2022 09:40:44 +0000 (10:40 +0100)]
add input and output reset signals to Pin
https://gitlab.com/nmigen/nmigen/-/issues/2

the issue being encountered is that ECP5 2x, 4x and 7x phase-tapped
IO pads will come up 50% of the time in an incorrect phase
setting the RST line of IDDR71B and other IOpad instances to Const(0)
is the likely root cause.

unfortunately, to fix this, an actual Signal has to be passed in,
to the LatticeECP5Platform, for it to be able to pass it to the IOpad.
that in turn means that the Pin Record has to have a reset signal added.

current experiments with GRAM show that setting the reset signal equal
to the domain reset signal is not quite sufficient, but greatly improves
the number of times that the DQS and other DDR IOpads get a successful
lock.  this most likely because the 2x PLL has not been given enough
time to stabilise.  at least with the addition of reset signals
i_prst and o_prst to Pin, experimentation and investigation can proceed

2 years agowhoops markdown formatting of migen compat layer not quite right
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 18:47:21 +0000 (19:47 +0100)]
whoops markdown formatting of migen compat layer not quite right

2 years agoinclude mention of nextpnr-xilinx support in README
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 18:45:32 +0000 (19:45 +0100)]
include mention of nextpnr-xilinx support in README

2 years agofixup nextpnr-xilinx directory locations to match
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 18:50:52 +0000 (19:50 +0100)]
fixup nextpnr-xilinx directory locations to match
install locations of nextpnr-xilinx with a make PREFIX of
/usr/local/nextpnr-xilinx

2 years agoMerge branch 'master' into 'master'
luke leighton [Wed, 30 Mar 2022 09:24:57 +0000 (09:24 +0000)]
Merge branch 'master' into 'master'

Lock NextPNR seed to 1

See merge request nmigen/nmigen!5

2 years agoLock NextPNR seed to 1
Raptor Engineering Development Team [Wed, 30 Mar 2022 02:19:38 +0000 (21:19 -0500)]
Lock NextPNR seed to 1

This allows reproducible builds, and
should have nearly no downsides vs.
allowing random seeds to be generated.

Should a design fail on seed 1, this can
be extended to allow a different seed to
be passed to NextPNR via the command line.

2 years agonextpnr-xilinx can cope with the various IBUF/OBUFs,
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 13:41:27 +0000 (13:41 +0000)]
nextpnr-xilinx can cope with the various IBUF/OBUFs,
no need to fall back to standard platform Instance("$tristate") etc.

2 years agoabc9 bugs-out in synth_xilinx, fall back to abc for now
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 18:54:13 +0000 (18:54 +0000)]
abc9 bugs-out in synth_xilinx, fall back to abc for now

2 years agonextpnr-xilinx is still under development, and needs some workarounds
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:26:50 +0000 (13:26 +0000)]
nextpnr-xilinx is still under development, and needs some workarounds
the first (already added) is "-nocarry", the second (added now)
is "scratchpad -set xilinx_dsp.multonly 1"
this is explained here:
https://github.com/gatecat/nextpnr-xilinx/issues/22#issuecomment-706710984

2 years agoadd option for adding synthesis attributes to the Memory behind
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 10:49:53 +0000 (10:49 +0000)]
add option for adding synthesis attributes to the Memory behind
ASyncFIFO and SyncFIFOBuffered as well

2 years agoadd the option to pass synthesis attributes through to the
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 10:39:40 +0000 (10:39 +0000)]
add the option to pass synthesis attributes through to the
underlying Memory of a SyncFIFO

2 years agoadd -nocarry option to synth_xilinx to avoid nextpnr-xilinx lock-up
Luke Kenneth Casson Leighton [Fri, 11 Feb 2022 19:51:20 +0000 (19:51 +0000)]
add -nocarry option to synth_xilinx to avoid nextpnr-xilinx lock-up
situation when CARRY4 chains go about 23-25

2 years agoadd start of a tutorials/examples/talks section to README
Luke Kenneth Casson Leighton [Fri, 11 Feb 2022 19:50:31 +0000 (19:50 +0000)]
add start of a tutorials/examples/talks section to README

2 years agoMerge branch 'docfix-readme-yosys-url' into 'master'
luke leighton [Sat, 5 Feb 2022 13:13:24 +0000 (13:13 +0000)]
Merge branch 'docfix-readme-yosys-url' into 'master'

Fixed Yosys URL

See merge request nmigen/nmigen!3

2 years agoadd symbiflow part map for Arty-A7-100t in xilinx platform
Luke Kenneth Casson Leighton [Sat, 5 Feb 2022 11:43:16 +0000 (11:43 +0000)]
add symbiflow part map for Arty-A7-100t in xilinx platform

2 years agovendor/xilinx: support for yosys nextPNR toolchain
Gwenhael Goavec-Merou [Sun, 30 Jan 2022 17:12:15 +0000 (18:12 +0100)]
vendor/xilinx: support for yosys nextPNR toolchain

2 years agoFixed Yosys URL
Sureal Cereal [Fri, 21 Jan 2022 20:24:07 +0000 (20:24 +0000)]
Fixed Yosys URL

Was http://www.clifford.at/yosys/ (404), now https://yosyshq.net/yosys/

2 years agoupdate docs folder in README
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 22:53:50 +0000 (22:53 +0000)]
update docs folder in README

2 years agoMerge branch 'display-patch' into 'master'
luke leighton [Fri, 31 Dec 2021 21:06:12 +0000 (21:06 +0000)]
Merge branch 'display-patch' into 'master'

add on_Display, by jeanthom

See merge request nmigen/nmigen!2

2 years agoadd on_Display, by jeanthom
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 21:03:57 +0000 (21:03 +0000)]
add on_Display, by jeanthom
https://gist.github.com/jeanthom/f97f5b928720d4adda9d295e8a5bc078

2 years agoallow yosys version 0.9
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 20:46:34 +0000 (20:46 +0000)]
allow yosys version 0.9

2 years agodocs: update sphinx-rtd-theme.
Catherine [Tue, 28 Dec 2021 20:41:19 +0000 (20:41 +0000)]
docs: update sphinx-rtd-theme.

Incorporate the fix for readthedocs/sphinx_rtd_theme#1168.

2 years agoCI: publish documentation for tagged commits.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 20:42:21 +0000 (20:42 +0000)]
CI: publish documentation for tagged commits.

2 years agodocs: don't call Python modules "packages".
Catherine [Thu, 16 Dec 2021 15:44:08 +0000 (15:44 +0000)]
docs: don't call Python modules "packages".

2 years agosim.pysim: use "bench" as a top level root for testbench signals.
Irides [Thu, 16 Dec 2021 01:47:48 +0000 (19:47 -0600)]
sim.pysim: use "bench" as a top level root for testbench signals.

Fixes #561.

2 years agoRevert "setup: add workaround for pypa/pip#7953."
Catherine [Thu, 16 Dec 2021 15:00:21 +0000 (15:00 +0000)]
Revert "setup: add workaround for pypa/pip#7953."

This reverts commit b1f5664b05725676cafa6c9313096c6fba0a47be.

2 years agoexamples/uart: acknowledging RX data should deassert RX ready.
Ben Newhouse [Thu, 16 Dec 2021 13:31:32 +0000 (08:31 -0500)]
examples/uart: acknowledging RX data should deassert RX ready.

2 years agosetup: add workaround for pypa/pip#7953.
Irides [Tue, 14 Dec 2021 14:56:58 +0000 (08:56 -0600)]
setup: add workaround for pypa/pip#7953.

2 years agodocs: add changelog.
Catherine [Mon, 13 Dec 2021 06:40:55 +0000 (06:40 +0000)]
docs: add changelog.

2 years agoadd CHANGELOG
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 20:35:30 +0000 (20:35 +0000)]
add CHANGELOG

2 years agolib.fifo: clarify AsyncFIFO{,Buffered}.r_rst documentation. NFC.
Catherine [Mon, 13 Dec 2021 09:53:29 +0000 (09:53 +0000)]
lib.fifo: clarify AsyncFIFO{,Buffered}.r_rst documentation. NFC.

2 years agodocs: simplify. NFC.
Catherine [Mon, 13 Dec 2021 09:03:22 +0000 (09:03 +0000)]
docs: simplify. NFC.

2 years agodocs: cover `nmigen.vendor`.
Irides [Mon, 13 Dec 2021 09:10:40 +0000 (03:10 -0600)]
docs: cover `nmigen.vendor`.

2 years agosim: represent time internally as 1ps units
modwizcode [Mon, 13 Dec 2021 03:43:20 +0000 (21:43 -0600)]
sim: represent time internally as 1ps units

Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.

2 years agodocs: cover `nmigen.lib.fifo`.
modwizcode [Mon, 13 Dec 2021 06:38:30 +0000 (00:38 -0600)]
docs: cover `nmigen.lib.fifo`.

2 years agodocs: formatting and readability improvements.
Catherine [Mon, 13 Dec 2021 06:33:36 +0000 (06:33 +0000)]
docs: formatting and readability improvements.

2 years agoupdate nmigen/lib/cdc.py docstrings
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 20:27:17 +0000 (20:27 +0000)]
update nmigen/lib/cdc.py docstrings

2 years agodocs: cover `nmigen.lib.cdc`.
Catherine [Mon, 13 Dec 2021 06:23:12 +0000 (06:23 +0000)]
docs: cover `nmigen.lib.cdc`.

2 years agodocs: cover `nmigen.lib.coding`.
Catherine [Mon, 13 Dec 2021 05:48:31 +0000 (05:48 +0000)]
docs: cover `nmigen.lib.coding`.

2 years agoback.rtlil: support slicing on Parts
Irides [Sat, 11 Dec 2021 16:27:12 +0000 (10:27 -0600)]
back.rtlil: support slicing on Parts

Fixes #605.

2 years agobuild.dsl: check type of resource number.
whitequark [Sat, 11 Dec 2021 13:37:15 +0000 (13:37 +0000)]
build.dsl: check type of resource number.

Fixes #599.

2 years agosim.core: warn when driving a clock domain not in the simulation.
whitequark [Sat, 11 Dec 2021 13:22:24 +0000 (13:22 +0000)]
sim.core: warn when driving a clock domain not in the simulation.

Closes #566.

2 years agohdl.ir: reject elaboratables that elaborate to themselves.
whitequark [Sat, 11 Dec 2021 12:39:34 +0000 (12:39 +0000)]
hdl.ir: reject elaboratables that elaborate to themselves.

Fixes #592.

2 years agosim._pyrtl: reject very large values.
whitequark [Sat, 11 Dec 2021 13:00:46 +0000 (13:00 +0000)]
sim._pyrtl: reject very large values.

A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.

2 years agovendor.xilinx: support setting options on synth_design Closes #606.
Irides [Sat, 11 Dec 2021 12:02:39 +0000 (06:02 -0600)]
vendor.xilinx: support setting options on synth_design Closes #606.

2 years agoback.rtlil,cli: allow suppressing generation of `src` attributes.
whitequark [Sat, 11 Dec 2021 11:38:40 +0000 (11:38 +0000)]
back.rtlil,cli: allow suppressing generation of `src` attributes.

Fixes #572.

2 years agosim.pysim: refuse to write VCD files with whitespace in signal names.
whitequark [Sat, 11 Dec 2021 11:12:25 +0000 (11:12 +0000)]
sim.pysim: refuse to write VCD files with whitespace in signal names.

Closes #595.

2 years agohdl.ast: support division and modulo with negative divisor.
whitequark [Sat, 11 Dec 2021 08:52:14 +0000 (08:52 +0000)]
hdl.ast: support division and modulo with negative divisor.

Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.

2 years agoupdate install.rst yosys version
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 20:09:55 +0000 (20:09 +0000)]
update install.rst yosys version

2 years agoback.rtlil: extend unsigned operand of binop if another is signed.
whitequark [Sat, 11 Dec 2021 10:25:41 +0000 (10:25 +0000)]
back.rtlil: extend unsigned operand of binop if another is signed.

Fixes #580.

2 years agohdl.ast: warn on bare integer value used in Cat()/Repl().
whitequark [Sat, 11 Dec 2021 08:18:33 +0000 (08:18 +0000)]
hdl.ast: warn on bare integer value used in Cat()/Repl().

Fixes #639.

2 years ago_utils: don't crash trying to flatten() strings.
whitequark [Sat, 11 Dec 2021 07:39:35 +0000 (07:39 +0000)]
_utils: don't crash trying to flatten() strings.

Fixes #614.

2 years agodocs: fix download link in start.rst.
whitequark [Sat, 11 Dec 2021 06:32:32 +0000 (06:32 +0000)]
docs: fix download link in start.rst.

Fixes #647.

2 years agoCI: fix test discovery command.
whitequark [Fri, 10 Dec 2021 10:48:14 +0000 (10:48 +0000)]
CI: fix test discovery command.

2 years agoCI: only discover tests under tests/.
whitequark [Fri, 10 Dec 2021 10:45:05 +0000 (10:45 +0000)]
CI: only discover tests under tests/.

This avoids a crash importing the deprecated `nmigen` module with
PYTHONWARNINGS=error set.

2 years agoCI: preserve YoWASP cache as well.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
CI: preserve YoWASP cache as well.

2 years ago_toolchain.cxx: ignore another deprecation warning (on Python 3.10).
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
_toolchain.cxx: ignore another deprecation warning (on Python 3.10).

Sigh.

2 years ago_toolchain.cxx: ignore deprecation warning (on Python 3.6).
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
_toolchain.cxx: ignore deprecation warning (on Python 3.6).

This code really shouldn't be using distutils, but for now this will
have to do.

2 years agodocs: update requirements.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
docs: update requirements.

Sphinx 4.2 or later is required for compatibility with Python 3.10.

A released version of Pygments can now be used for highlighting.

2 years ago_toolchain.cxx: use distutils from setuptools.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
_toolchain.cxx: use distutils from setuptools.

The distutils module from the standard library is deprecated and will
be removed in Python 3.12, and PEP 632 recommends using
distutils.ccompiler from setuptools, instead.

This code should eventually be rewritten to use zig-pypi, but for now
this suffices.

2 years agovendor.xilinx_*: deprecate legacy Xilinx platform aliases.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
vendor.xilinx_*: deprecate legacy Xilinx platform aliases.

2 years agoRun tests on Python 3.10.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
Run tests on Python 3.10.

2 years agoSimplify CI workflow.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
Simplify CI workflow.

2 years agovendor.intel: add Mistral toolchain support.
Olivier Galibert [Thu, 14 Oct 2021 16:02:22 +0000 (18:02 +0200)]
vendor.intel: add Mistral toolchain support.

2 years agohdl.ast: improve interaction of ValueCastable with custom __getattr__.
whitequark [Sun, 3 Oct 2021 20:28:07 +0000 (20:28 +0000)]
hdl.ast: improve interaction of ValueCastable with custom __getattr__.

Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.

2 years agomention benefits of nmigen over MyHDL, ability to use full python OO
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 16:11:29 +0000 (16:11 +0000)]
mention benefits of nmigen over MyHDL, ability to use full python OO

2 years agomention MyHDL for compare/contrast to nmigen
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 16:09:35 +0000 (16:09 +0000)]
mention MyHDL for compare/contrast to nmigen

2 years agorestore nmigen logos, update wording on git format-patch
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 16:06:22 +0000 (16:06 +0000)]
restore nmigen logos, update wording on git format-patch

2 years agomore README whitespace
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:59:30 +0000 (15:59 +0000)]
more README whitespace

2 years agomention that git format-patch for contributions is perfectly fine
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:58:54 +0000 (15:58 +0000)]
mention that git format-patch for contributions is perfectly fine

2 years agowhitespace update on README.md
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:57:16 +0000 (15:57 +0000)]
whitespace update on README.md

2 years agoMerge branch 'update_to_2021oct08' into 'master'
luke leighton [Fri, 31 Dec 2021 15:54:49 +0000 (15:54 +0000)]
Merge branch 'update_to_2021oct08' into 'master'

sim._pyrtl: optimize uses of reflexive operators.

See merge request nmigen/nmigen!1

2 years agoMerge branch 'master' into 'update_to_2021oct08'
luke leighton [Fri, 31 Dec 2021 15:54:32 +0000 (15:54 +0000)]
Merge branch 'master' into 'update_to_2021oct08'

# Conflicts:
#   LICENSE.txt
#   README.md
#   nmigen/test/utils.py
#   nmigen/vendor/xilinx_7series.py
#   setup.py

2 years agocorrect IRC link
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:49:06 +0000 (15:49 +0000)]
correct IRC link

2 years agoreplace github with gitlab
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:45:23 +0000 (15:45 +0000)]
replace github with gitlab

2 years agoadd reference to nmigen Trademark
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:40:50 +0000 (15:40 +0000)]
add reference to nmigen Trademark

2 years agohdl.ast: simplify Mux implementation.
whitequark [Sat, 2 Oct 2021 14:18:02 +0000 (14:18 +0000)]
hdl.ast: simplify Mux implementation.

2 years agohdl.ast: add tests for casting bare integers in {Cat,Repl}.
whitequark [Sat, 2 Oct 2021 13:18:11 +0000 (13:18 +0000)]
hdl.ast: add tests for casting bare integers in {Cat,Repl}.

2 years agohdl.ast: remove quadratic time complexity in Statement.cast().
Anton Blanchard [Mon, 27 Sep 2021 01:00:56 +0000 (11:00 +1000)]
hdl.ast: remove quadratic time complexity in Statement.cast().

Using `sum(lst, [])` to flatten a list of lists has quadratic time
complexity. Use `chain.from_iterable()` instead. While not strictly
necessary to improve performance, convert to `map()`.

A test case writing out verilog for a 512k entry FIFO is 120x faster
with this applied.

2 years agovendor.xilinx: avoid using `/` for hierarchy in ISE constraint files.
H-S-S-11 [Sat, 25 Sep 2021 10:41:23 +0000 (11:41 +0100)]
vendor.xilinx: avoid using `/` for hierarchy in ISE constraint files.

2 years agoUnify Xilinx platforms into a single class, support more devices
Marcelina Kościelnicka [Wed, 16 Dec 2020 15:35:57 +0000 (16:35 +0100)]
Unify Xilinx platforms into a single class, support more devices

This merges existing code, and also adds support for:

- Virtex, Virtex E (also known as Spartan 2, Spartan 2E)
- Virtex 2, Virtex 2 Pro
- Spartan 3, Spartan 3E (in addition to existing Spartan 3A, Spartan 3A
  DSP support)
- Virtex 4
- Virtex 5
- Virtex 6
- ISE synthesis for Series 7

Fixes #552.

2 years ago_toolchain: Properly set compiler/linker executables on Gentoo
Adam Jeliński [Tue, 21 Sep 2021 08:33:26 +0000 (10:33 +0200)]
_toolchain: Properly set compiler/linker executables on Gentoo

The `test_toolchain_cxx.py` tests on Gentoo definitely use compiler and
linker set with `_so_cxx`-suffixed executables. Tests use a proper
executable instead of `c++` after this change.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
2 years agovendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical
Robin Ole Heinemann [Mon, 16 Aug 2021 21:31:57 +0000 (23:31 +0200)]
vendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical

Signed-off-by: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>
2 years ago_toolchain: substitute '+' with 'X' in tool_env_var().
Jean-François Nguyen [Fri, 16 Jul 2021 17:16:56 +0000 (19:16 +0200)]
_toolchain: substitute '+' with 'X' in tool_env_var().

2 years agoREADME: update IRC channel.
whitequark [Thu, 20 May 2021 03:07:51 +0000 (03:07 +0000)]
README: update IRC channel.

2 years agorpc: fix parsing of negative signed parameters
Robin Ole Heinemann [Tue, 18 May 2021 18:43:16 +0000 (20:43 +0200)]
rpc: fix parsing of negative signed parameters

2 years agotest.test_hdl_ast.OperatorTestCase: remove duplicate test_bool
Robin Ole Heinemann [Tue, 18 May 2021 19:18:51 +0000 (21:18 +0200)]
test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool

2 years agotests: rename tests with duplicate names
Robin Ole Heinemann [Tue, 18 May 2021 19:18:14 +0000 (21:18 +0200)]
tests: rename tests with duplicate names

2 years agotests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix
Robin Ole Heinemann [Tue, 18 May 2021 19:15:02 +0000 (21:15 +0200)]
tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix