git.libre-soc.org Git - gem5.git/log

arch-power: Add support for G500 platform

This adds the G500 platform for the power architecture that
is useful for connecting components like a serial console.

Change-Id: I9ab3b169ecefaa3fcd03850d4620e94a611fc12f
Signed-off-by: Pratik Rajesh Sampat <prasampa@in.ibm.com>

arch-power: Added support for SMT

This adds support for SMT (simultaneous multi-threading).
  * Enable multithreading for power architecture.
  * Make number of threads 2.
  * Added support for post and clear interrupt.
  * Added interrupt array support for external interrupts so
    that it will check any pending interrupt request in every
    tick.
  * Initialize PIR for second thread.
  * Initialize PC state for second thread so that it
    will loop until first thread try to wake up secondary
    threads.
  * Initialize register r3 for second thread.

Change-Id: I5825e62a94b50aaa213eb64335973129addf2e4c
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added Doorbell interrupt Handler

Added doorbell interrupt handler of type :

* Directed Hypervisor Doorbell Interrupt.
* Directed Privileged Doorbell Interrupt.

Change-Id: I2b2d8c07a0bbe353bf7a8279f5a02f1fe3acba87
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added dummy register

Added dummy register to avoid clearing of required register data.

Change-Id: Ic65f2c01d59c6ba7f84b13fa15ea6af85f2e8d86
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added function to set HSSR1 register

Change-Id: Ie7f44b4f901d22bf877b5c066a9f9042effb793c
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added PIR register

* Added PIR(Processor Identification Register).
* Added mfpir instruction to get content of register PIR.

Change-Id: I16b82684e7c9a5e5172f0395dd0a021791757425
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added support for Doorbell instructions

* Added support for doorbell instructions
  * msgclr
  * msgsnd
  * msgsync
  * msgclrp

Change-Id: Iec985b8fa2efec313672d88ec87f03ce121d66b5
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added support for Trap instructons

* Added trap instructons.
* Added trap interrupt handler.
* Raise trap interrupt whenever condition satisfied for corresponding trap instruction.
* Added bit need to set for that type of interrupt.

Change-Id: I46de00558139e0726c056fd71f819d63cb8045df
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added support for Atomic Instructions

Add support for Load and Reserve and Store Conditional Instructions:

* Load Byte And Reserve Indexed.
* Store Byte Conditional Indexed.
* Load Halfword And Reserve Indexed.
* Store Halfword Conditional Indexed.
* Load Word And Reserve Indexed.
* Store Word Conditional Indexed.
* Load Doubleword And Reserve Indexed.
* Store Doubleword Conditional Indexed.

Change-Id: I1dac94928e7a1bb6f458a4ecea0fca3247b26d37
Signed-off-by: Kajoljain379 <kajoljain797@gmail.com>

arch-power: Updated branch instruction

Change-Id: I242e8d5f0f3a5b12baa968967dd31f4e1260fa49
Signed-off-by: Kajoljain379 <kajoljain797@gmail.com>

arch-power: Added dcbz instruction

* Added dcbz cache instruction which used by kernel to clear multiple
words at a time.

Change-Id: I7cfd7c93cac2d4419db987e7cf8fef8b4c71f805
Signed-off-by: Kajoljain379 <kajoljain797@gmail.com>

arch-power: Added cache instruction

* Added dcbf cache instruction.
* Right now we are not supporting cache, its just nop
instruction.

Change-Id: I0d3010e17e636fba44716b9368f8b919295c4764
Signed-off-by: Kajoljain379 <kajoljain797@gmail.com>

arch-power: Added functionality to update Reference and Change bit

* Update the "Reference" and the "Change" bits on
the page-table entry whenever a page is accessed.

Change-Id: Iced7c10019e1ebe618f9723a65c6812d992bf27e
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Updated Data & Instruction Storage Interrupt

Added more checks for DATA and INSTRUCTION Storage Interrupt.

Change-Id: I1e386ac007ebd59cc5447a6226360965748073f5
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added proper formats for DPRINTFS

* Added proper format for DPRINTFS.

Change-Id: I32ce3158de5b98d1b842ea6feabf77130b8d75ec
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Modify Interrupt handler for DSI and ISI

* Modify Interrupt handler for Data storage (DSI) and Instruction
Storage Interrupt (ISI).
* Added function to check mode of instruction.
* Added function to prepare registers for DSI.
* Added function to prepare registers for ISI.

Change-Id: I62ee5116c2acdbad225f7dc7fe72bb95d9462dc4
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Add helper functions in radixwalk

* Added function to generate Mask with given bit set.
* Added a function to generate Mask with a sequence of clear bits.

Change-Id: I7cf0b0915ffd327a98537a89f7b3f60314ea6098
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Add function to Write in physical memory

* Add a helper to write to the physical memory.
* This will be used in the subsequent patches to update the
"Reference" and the "Change" bits on the page-table entry
whenever a page is accessed.

Change-Id: I89c732be5884341ae0d33801a63578dbd2e08815
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Updated Store instructions

Change-Id: I3eb0f5adbcce13cf586755fa62c7ca1d7aa80089
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Add DARN instruction

* Added DARN instruction.
* Right now not returning random number, Just Setting value to -1.
* Need to FIX that instruction.

Change-Id: I9b6fd7557232c16fda144f4a424bfffb62de33cc
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added more Special Purpose Register

* Added more special purpose registers.
* Added corresponding move functions.

Change-Id: I05a6fe75ef9303a0c7071b0260a084b199a8bfbb
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Add support for timebase updates

* Added support to update INTREG_TB on checkInterrupt
* Initialize TB register
* Add support for decrementer interrupt to check for ee bit to
handle nested interrupt.

Change-Id: I2e1f37871879bb9370eba17ddb5d23562665b138
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added Data and Instruction Interrupt Handler

Added data and instruction storage interrupr handler and
modify radixwalk.cc to check permissions and privileges of
both data and instrustion.

Change-Id: I5d3a820862cde7bd298f0b715777f069fb1e39d1
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added Radix Tree Page Table Entry

Change-Id: Ifde9fac352f8019247e8f5f7936c081a3b85d3ac
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added Illegal type Program interrupt support

Added suppot for illegal or unknown instruction type program
interrupt.
* Check if instruction is unknown or invalid and incase its unknown
raise Illegal type program interrupt.
* Added Illegal instruction interrupt handler.

Change-Id: Ib203cfc3542f47b9e0141a2a3f170dc6becf8a90
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added support for Program Interrupt

Added supoort for program interrupt for Privileged type instruction.

* Added flag IsPrivileged to check wheather instruction is
privileged or not.
* Define bit number to be set in MSR for corresponding interrupt.
* Added Program interrupt handler with privileged type interrupt handler.
* Add IsPrivileged flag in all privileged instructions
* Add checker for PR bit inorder to verify mode for privilege instructions
and raise interrupt if needed.

Change-Id: I2aeb1a603568a6f80cd074bf67d4a528ebb6a5bd
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

arch-power: Added Logical Partitioning Control Register(LPCR) Register

Change-Id: Id9bf672007cc7dfdabc3a073d79715d74e1975ed
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added SystemCall Interrupt handler

Added system call interrupt handler.
Added handler calling in decoder file.

Change-Id: I80b99257fe4b96a1a286f17afcec28bb8a849b83
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Modify Decrementer interrupt

Modify decrementer interrupt handler.

Change-Id: Ibafd535e7cb5faeb3d4f6c479893bb72f01f944c
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added enumeration for Interrupt PC state

Added enum to get address of required interrupt service routine.

Change-Id: I1c5e0c149b870c0a7b60e5935fb7b701b3bf3084
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Initialize PC State

Initialize PC state to 0x100.

Change-Id: Id130d161e40d287dfb1a1f97d5e1d58dfa0f2303
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>

arch-power: Added function to modify MSR and SRR1 register

* Added general function to modify MSR and SRR1 register.
* Added macros to get mask for
* Set particular bit.
* Unset Bit.

Change-Id: I17b82f6ef7f7d8915f9c1320f99fc6f3f9ecaf74
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

power: Add support for Radix Translation

Power ISA v3.0 introduces the Radix MMU in addition to the Hash MMU.

This patch adds support in gem5 for handling the Radix based address
translations when MSR[IR,DR] bits are set.

It also adds an example of a radix_walk.

Change-Id: I193f8d44f36b429997f7ffcb788a50544ba65a8c

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>

power: Add support for real-mode addressing (translation is off)

This patch adds support for executing programs which don't have the
translation support (MSR[IR, DR] = 0). With this change, we should be
able to run 64 little endian elf binaries executing previleged
instructions with translation off.

Change-Id: Iaa64a37676874cee1ed1a0591b51b5e842774b45
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>

power: Add support for handling the Decrementer Interrupt

This patch allows the programming of the decrementer device, which
will count down to zero. As of now, the decrement happens after every
instruction. When the decrementer value hits 0, the CPU is delivered a
decrementer interrupt.

[ego@linux.vnet.ibm.com: Fixed Conflicts in src/arch/power/interrupts.hh]

Change-Id: I3a863a8e2bca434d5a8139df662429d3e83a8542

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>

arch-power: Define more special purpose registers, mtspr,mfspr instructions

This patch defines more special purpose registers taking their count
to 49.

This also defines the mtspr and mfspr instructions to move the
contents to and from the these special purpose registers.

[ego@linux.vnet.ibm.com: Fixed conflicts in
src/arch/power/isa/decoder.isa,
src/arch/power/isa/operands.isa,
src/arch/power/registers.hh]

[kajoljain797@gmail.com: Fixed rfid, hrfid, mtmsr, mtmsrd instructions]

NOTE: Perhaps can be folded into the previous patch which introduces
CR, MSR, PTCR, etc.

Change-Id: I4dd6ba8c710c4c522fadc685b60fb039dfd0a743

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

power: Added support for CR, XER, FPSR, MSR, PTCR Registers

Define Condition Register (CR), XER, FPSR, MSR, PTCR Registers
as miscelleneous registers.

In particular, annotate the bits of MSR and PTCR for future use.

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: I6f1490b1490e16f9095075f5cd0056894fbf6608

Power: Add a minimal system configuration

[ego@linux.vnet.ibm.com: Fixeed conflicts in example/fs.py]

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: Idf6dad2ea3a7eef7bb3475c5abb2108690e59942

arch-power: Update hello test program

This updates the hello test program binary to an equivalent
64-bit little endian executable. Since this binary is built
with a recent toolchain, the kernel version provided by the
uname system call is ramped up to be able to meet the minimum
version required by glibc. This binary also uses the readlink
system call and the Move From Time Base (mftb) instruction.
So, placeholder code is added for these.

Change-Id: I645b344e8582f938711b75488bd25899c374cca3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix stack layout for 64-bit execution

This fixes the call stack layout by changing the size of the
auxiliary vector entries, each of which contain two 64-bit
values. Also, all base addresses for stack contents are now
considered to be 64 bits in order to prevent underflows during
program execution.

Users can now run statically-linked 64-bit ELF ABI v2 compliant
PowerPC LSB ELF executables in syscall emulation mode.

Change-Id: I256399d9344b1b101385e32ad8978325aec9844e
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add branch target address register instructions

This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it:
  * Move To Target Address Register (mttar)
  * Move From Target Address Register (mftar)
  * Branch Conditional to Branch Target Address Register (bctar[l])

Change-Id: I5130a22040e30a05e963b1cc8d38abbed9a49edb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix branch instructions

This fixes the following branch instructions in order to
support 64-bit addressing:
  * Branch (b[l][a])
  * Branch Conditional (bc[l][a])
  * Branch Conditional to Link Register (bclr[l])
  * Branch Conditional to Count Register (bcctr[l])

This also fixes disassembly generation for all of the above.

Change-Id: I7cad4e1b3b2945ab06c4ffc8c79842f1453c85ec
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword rotate instructions

This adds the following rotate instructions:
  * Rotate Left Doubleword Immediate then Clear Left (rldicl[.])
  * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
  * Rotate Left Doubleword Immediate then Clear (rldic[.])
  * Rotate Left Doubleword then Clear Left (rldcl[.])
  * Rotate Left Doubleword then Clear Right (rldcr[.])
  * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])

Change-Id: I27520314e738e5bed92bf07c1150943c9f83e881
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fields for MD and MDS form instructions

This introduces the extended opcode fields and the fields
mb and me for MD and MDS form instructions.

Change-Id: I2c3366794ed42f5d31ba1d69e360c0ac67c74e06
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point word rotate instructions

This fixes the following rotate instructions:
  * Rotate Left Word Immediate then And with Mask (rlwinm[.])
  * Rotate Left Word then And with Mask (rlwnm[.])
  * Rotate Left Word Immediate then Mask Insert (rlwimi[.])

For 64-bit execution, these instructions should perform rotate
operations on a 64-bit value formed by concatenating two copies
of the lower order 32 bits of the value in the source register.

This also fixes disassembly generation for all of the above.

Change-Id: Iccd8c6ad10a26d66dcecd64c8f1f8118ec8c1278
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword shift instructions

This adds the following shift instructions:
  * Shift Left Doubleword (sld[.])
  * Shift Right Doubleword (srd[.])
  * Shift Right Algebraic Doubleword (srad[.])
  * Shift Right Algebraic Doubleword Immediate (sradi[.])
  * Extend-Sign Word and Shift Left Immediate (extswsli[.])

Change-Id: Icd1f3efda715c5b8a7c7bc648ba29a8749e74695
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fields for XS form instructions

This introduces the extended opcode field and the field
sh for XS form instructions.

Change-Id: I8f7cb3a2fda33b5b0076ffe12ffebeb5ec1c33a6
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point word shift instructions

This fixes the following shift instructions:
  * Shift Left Word (slw[.])
  * Shift Right Word (srw[.])
  * Shift Right Algebraic Word (sraw[.])
  * Shift Right Algebraic Word Immediate (srawi[.])

For 64-bit execution, these instructions should perform
shift operations on only the lower order 32 bits of the
source register instead of all 64 bits.

This also fixes disassembly generation for all of the above.

Change-Id: I18871486d74969244d474eaf0f9d810f06faf50a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point logical bit permute instructions

This adds the following logical instructions:
* Bit Permute Doubleword (bpermd[.])

Change-Id: I1af329cd28871c00ebb0574e38a53bcd6a3b794c
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point logical parity instructions

This adds the following logical instructions:
* Parity Word (prtyw)
* Parity Doubleword (prtyd)

Change-Id: Icb1737435dfabf9ac7b14ce1fcdf1c232289bf24
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point logical population count instructions

This adds the following logical instructions:
  * Population Count Bytes (popcntb)
  * Population Count Words (popcntw)
  * Population Count Doubleword (popcntd)

Change-Id: I946d1f8b270b4c75849cdfb7e413974ae8748494
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point logical count zeros instructions

This adds the following logical instructions:
  * Count Trailing Zeros Word (cnttzw[.])
  * Count Leading Zeros Doubleword (cntlzd[.])
  * Count Trailing Zeros Doubleword (cnttzd[.])

Change-Id: I4bcf090178d9241f230509ba55e8e58f5e7794ac
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point logical extend sign instructions

This adds the following logical instructions:
* Extend Sign Word (extsw[.])

Change-Id: I610e84c2361b99b00ceef2170ede5b6dee8ec21b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point logical instructions

This fixes the following logical instructions:
  * Extend Sign Byte (extsb[.])
  * Extend Sign Halfword (extsh[.])
  * Count Leading Zeros Word (cntlzw[.])
  * Compare Bytes (cmpb)

This also fixes disassembly generation for all of the above.

Change-Id: I98873edf24db606d8de481aa18bcb809ad38d296
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point compare instructions

This adds the following compare instructions:
* Compare Ranged Byte (cmprb)
* Compare Equal Byte (cmpeqb)

Change-Id: I44765b3a9a8f0a3d81ecd6984efce3fd01ba4b24
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point compare instructions

This fixes the following compare instructions:
  * Compare (cmp)
  * Compare Logical (cmpl)
  * Compare Immediate (cmpi)
  * Compare Logical Immediate (cmpli)

Instead of always doing a 32-bit comparison, these instructions
now use the length field to determine the type of comparison to
be done. The comparison can either be based on the lower order
32 bits or on all 64 bits of the values.

This also fixes disassembly generation for all of the above.

Change-Id: I6a9f783efa9ef2f2ef3c16eada61074d6f798a20
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword arithmetic modulo instructions

This adds the following arithmetic instructions:
* Modulo Signed Doubleword (modsd)
* Modulo Unsigned Doubleword (modud)

Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword arithmetic divide extended instructions

This adds the following arithmetic instructions:
* Divide Doubleword Extended (divde[o][.])
* Divide Doubleword Extended Unsigned (divdeu[o][.])

Change-Id: I535605fa6d32153054d259bcb14b952a26a1372a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword arithmetic divide instructions

This adds the following arithmetic instructions:
* Divide Doubleword (divd[o][.])
* Divide Doubleword Unsigned (divdu[o][.])

Change-Id: Iedfa46ee482201a25dbc195ac5cb7f5f5e83c29b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword multipy-add instructions

This adds the following arithmetic instructions:
  * Multiply-Add Low Doubleword (maddld)
  * Multiply-Add High Doubleword (maddhd)
  * Multiply-Add High Doubleword Unsigned (maddhdu)

Change-Id: I09ecca9f3eb0abaf6b5a82a6d33d7f3e54b9837b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fields for VA form instructions

This introduces the extended opcode field and the operand
field RC for VA form instructions.

Change-Id: I60d1bff6e7c7dd41e6fbe28a5f012b6fd66e7bc3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword multiply instructions

This adds the following arithmetic instructions:
  * Multiply Low Doubleword (mulld[o][.])
  * Multiply High Doubleword (mulhd[.])
  * Multiply High Doubleword Unsigned (mulhdu[.])

Change-Id: I505d94dc8e9711c575c94f75e10f7e05e1d05fdf
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point arithmetic add instructions

This adds the following arithmetic instructions:
* Add PC Immediate Shifted (addpcis)

Change-Id: Id9de59427cbf8578fd75cbb7c98fb767d885d89a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fields for DX form instructions

This introduces the extended opcode field and the fields
d0, d1 and d2 for DX form instructions.

Change-Id: Iac52bca39993e4a5f299f33d356e36037c516130
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point word arithmetic modulo instructions

This adds the following arithmetic instructions:
* Modulo Signed Word (modsw)
* Modulo Unsigned Word (moduw)

Change-Id: I5590e569afb71dd429c473bd18c65457e2c49286
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point word arithmetic divide extended instructions

This adds the following arithmetic instructions:
* Divide Word Extended (divwe[o][.])
* Divide Word Extended Unsigned (divweu[o][.])

Change-Id: I1b8321de569d1be466e9d84ca5047b0c4682a0e3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point arithmetic multiply and divide instructions

This fixes the following arithmetic instructions:
  * Multiply Low Immediate (mulli)
  * Multiply Low Word (mullw[o][.])
  * Multiply High Word (mulhw[.])
  * Multiply High Word Unsigned (mulhwu[.])
  * Divide Word (divw[o][.])
  * Divide Word Unsigned (divwu[o][.])

This also fixes disassembly generation for all of the above.

Change-Id: I46fd3751b86a7436a962f8b93f26d8343f215fed
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point arithmetic add and subtract instructions

This fixes the following arithmetic instructions:
  * Add Immediate (addi)
  * Add Immediate Shifted (addis)
  * Add (add[o][.])
  * Subtract From (subf[o][.])
  * Add Immediate Carrying (addic)
  * Add Immediate Carrying and Record (addic.)
  * Subtract From Immediate Carrying (subfic)
  * Add Carrying (addc[o][.])
  * Subtract From Carrying (subfc[o][.])
  * Add Extended (adde[o][.])
  * Subtract From Extended (subfe[o][.])
  * Add to Zero Extended (addze[o][.])
  * Subtract From Zero Extended (subfze[o][.])
  * Negate (neg[o][.])

This also fixes disassembly generation for all of the above.

Change-Id: I431020a3f8b8610d6e18d1450848a50f477912cb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point store conditional instructions

This adds the following store instructions:
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Doubleword Conditional Indexed (stdcx.)

Change-Id: I065113e817e2ae419a6f3231e645bacd95460607
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point load and reserve instructions

This adds the following load instructions:
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Doubleword And Reserve Indexed (ldarx)

Change-Id: Iac3cf0e16e2b5da8b772be81850419e21f26bdab
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point byte-reversed load and store instructions

This adds the following load and store instructions:
  * Load Halfword Byte-Reverse Indexed (lhbrx)
  * Load Word Byte-Reverse Indexed (lwbrx)
  * Load Doubleword Byte-Reverse Indexed (ldbrx)
  * Store Halfword Byte-Reverse Indexed (sthbrx)
  * Store Word Byte-Reverse Indexed (stwbrx)
  * Store Doubleword Byte-Reverse Indexed (stdbrx)

Change-Id: I9f211bb4e3007ca09002a9ba4e5afb4b2e67cddd
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Add fixed-point doubleword load and store instructions

This adds the following load and store instructions:
  * Load Doubleword (ld)
  * Load Doubleword Indexed (ldx)
  * Load Doubleword with Update (ldu)
  * Load Doubleword with Update Indexed (ldux)
  * Store Doubleword (std)
  * Store Doubleword Indexed (stdx)
  * Store Doubleword with Update (stdu)
  * Store Doubleword with Update Indexed (stdux)

Change-Id: I57a95003b6c6cfc09cc40f9ac03b32a8dfd7b26d
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Fix fixed-point load and store instructions

This fixes the following load and store instructions as a result
of the change in register widths:
  * Load Word and Zero (lwz)
  * Load Word and Zero Indexed (lwzx)
  * Load Word and Zero with Update (lwzu)
  * Load Word and Zero with Update Indexed (lwzux)
  * Load Word Algebraic (lwa)
  * Load Word And Reserve Indexed (lwarx)
  * Store Word (stw)
  * Store Word Indexed (stwx)
  * Store Word with Update (stwu)
  * Store Word with Update Indexed (stwux)
  * Store Word Conditional Indexed (stwcx.)

This also fixes disassembly generation for all of the above.

Change-Id: I1a25cdb5ffe86145b7ffcf2c2bd7b27048a415d2
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Introduce proper opcode fields

This introduces separate extended opcode fields for DS, X, XFL,
XFX, XL and XO form instructions and renames the primary opcode
field from OPCODE to PO as listed in the Power ISA manual.

Scenarios where multiple instructions of different forms share
the same primary opcode have also been addressed by using the
correct extended opcode fields for decoding.

Change-Id: I4a01820f6a6326ef79330221b717952c6b9cbba3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Reorder instruction decoding logic

This reorders the decoding logic based on the category of
instructions. The ordering applied here is roughly in line
with the Power ISA manual which is as follows:
  * Branch facility instructions
      * Branch instructions
      * Condition Register instructions
      * System Call instructions
  * Fixed-point facility instructions
      * Load instructions
      * Store instructions
      * Arithmetic instructions
      * Compare instructions
      * Logical instructions
      * Rotate and Shift instructions
      * Move To/From System Register instructions
  * Floating-point facility instructions
      * Load instructions
      * Store instructions
      * Arithmetic instructions
      * Move instructions
      * Rounding and Conversion instructions
      * Compare instructions
      * Status and Control Register instructions

Change-Id: Icfb57c5e442a959e502222222b84289d8e74ecbf
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Make ELF interpreter read 64-bit LSB executables

This makes the ELF interpreter read 64-bit little endian (LSB)
PowerPC executables only. This drops support for the 32-bit big
endian (MSB) executables as the goal here is to enable a modern
64-bit execution environment for the Power ISA.

Change-Id: I0569f7e1d1e58ce874ec2d13291e7a758d56399f
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

arch-power: Switch to 64-bit registers and operands

This increases the width of the general-purpose registers and some
of the other important registers to 64 bits. This is a prerequisite
for enabling a 64-bit execution environment and allows the register
operands provided in instructions to also be recognized as 64-bit.

Change-Id: I442315163a5029bbfb9d4b16b5e6decd3ab2d61b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

misc: Updated the RELEASE-NOTES and version number

Updated the RELEASE-NOTES.md and version number for the v20.1.0.2
hotfix release.

Change-Id: Ibb6b62a36bd1f9084f7d8311ff1f94b8564dbe9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,stats: Fix incorrect stat names of ThreadStateStats

Previously, ThreadStateStats uses ThreadState::threadId() to
determine the name of the stats. However, in the ThreadState
constructor, ThreadStateStats is initialized before ThreadState
is intialized. As a result, the name of ThreadStateStats has
a wrong ThreadID.

This commit uses ThreadID instead of ThreadState to determine
the name of the stats.

This causes a name collision between ThreadStateStats and
ExecContextStats as both have the name of "thread_[tid]".
Ideally, those stats should be merged to the BaseSimpleCPU.
However, both ThreadStateStats and ExecContextStats have
a stat named numInsts. So, for now, ExecContextStats will
have a name of "exec_context.thread_[tid]", while ThreadStateStats
keeps its name.

Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37455
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix MemorySize division

The memory size is expected to be an integer.

Jira: https://gem5.atlassian.net/browse/GEM5-806

Change-Id: I44b2d423a3478d2598950779222151f09970cbd8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37255
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>

misc: Updated the RELEASE-NOTES and version number

Updated the RELEASE-NOTES.md and version number for the v20.1.0.1
hot-fix.

Change-Id: I51f7ba6f1178a2d8e80488ed2184b8735c2234a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37116
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Fix garnet network interface stats

Fixing a bug in garnet network interface where flit source delay is
computed using both tick and cycle.

Change-Id: If21a985f371a818611d13e9cd5ce344dbcf5fb2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36416
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37115
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jieming Yin <bjm419@gmail.com>

misc: Updated version to 20.1.0.0

Change-Id: Ic7a37581c58caa354eeecab051122116177d0721
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35456
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Removed -Werror for the gem5 20.1 release

While gem5 compiles on all our supported compilers, removing the -Werror
flag on the stable branch ensures that, as new compilers are released
with stricter warnings, gem5 remains compilable.

Change-Id: I9a356472dc4d729a3fef9f1455814c900103bd66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35455
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated CONTRIBUTING.md: 'master' -> 'stable'

The `master` branch is now the `stable` branch. This commit updates
CONTRIBUTING.md accordingly.

Change-Id: Ic5231eda336520e8a7260efac6474b4f0af08c37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35457
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add release notes for 20.1

Change-Id: I011ff987e222326dd7f0787c41043578b52b236a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35375
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Adding missing argument of panic function

panic function call in panicFsOnlyPseudoInst (src/sim/pseudo_inst.cc) needs to be invoked with argument (name).

Jira Issue: https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-786?filter=allissues

Change-Id: Iecacab7b9e0383373b69e9b790fa822d173d29c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35040
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Disable range-loop-analysis warnings for pybind11

Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35296
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Updated TestLib and boot-tests for gzipped imgs

In efforts to reduce storage costs and download times, the images hosted
by us have been gzipped. The TestLib framework has therefore been
extended to decompress gzipped files after download.

The x86-boot-tests are, at present, the only tests which use the gem5
images. These tests have been updated to download the gzipped image.

Change-Id: I6b2dbe9472a604148834820db8ea70e91e94376f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,python: Add warning for when python3-config is not used

We cannot say for certain whether 'python-config' is python2 or python3,
but this patch will produce a warning if 'python3-config' is not used,
stating that support for python2 will be dropped in future releases of
gem5.

Change-Id: I114da359c8768071bf7dd7f2701aae85e3459678
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35256
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Removing gem5/hello_se/ref/simerr

This is not needed in any comparison we make. It was probably added in
error.

Change-Id: Ie771654f73d101d0ef90ca6e2864a7cb684b3919
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34996
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,python: Add python2-config to PYTHON_CONFIG

PYTHON_CONFIG can be python2-config as well as python2.7-config.

Change-Id: I482cb922fcf26b37f67f2aca392e04968ca144bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35255
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,python: Prioritize Python3 for PYTHON_CONFIG

Change-Id: I0ac4d90b93f2e0a9384216f759937f7b0aa23d41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34899
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Flush the simulation stdout/stderr buffers

Occasionally gem5's stdout/stderr, when run within the TestLib
framework, will be shuffled. This is resolved by flushing the
stdout/stderr buffer before and after simulation.

In addition to this, the verifier.py has been improved to remove
boilerplate gem5 code from the stdout comparison.

Change-Id: I04c8f9cee4475b8eab2f1ba9bb76bfa3cfcca6ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34995
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Instantiate a single HTM checkpoint at ISA::startup

Change-Id: I48cc71dce607233f025387379507bcd485943dde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35016
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Allow storing an invalid HTM checkpoint

Commits 02745afd and f9b4e32 introduced a mechanism for creating checkpoint
objects for hardware transactional memory (HTM) and Arm TME. Because the
checkpoint object also contains the local UID of a transaction, it is
needed before any architectural checkpointing takes places. This caused
segfaults when running HTM codes.

This commit allows ISAs to allocate a checkpoint once at the beginning
of simulation. In order to do that we need to remove the validity check
assertion; the cpt will become valid only after a first successfull
transaction start

Change-Id: I233d01805f8ab655131ed8cd6404950a2bf6fbc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Fix some reference use in range loops

This change fixes two cases of range loops, one where we can't use
lvalue reference, and one more where we have to use an lvalue
reference as we can't create a copy. In both cases clang would warn.

Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34776
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: When loading an image directly in memory, use the right CL size.

Some code was added fairly recently which would load a memory image
into a memory directly in order to make it easier to set up ROMs.
Unfortunately, that code accidentally used the image size instead of
the cache line size when setting up the port proxy which would actually
write the data. This happens to work when the image size is a power of
two since that's all the proxy checks for, but there's no guarantee
that every image will be sized that way.

This change instead looks into the system object, retrieves the cache
line size from it, and uses that to set up the port proxy.

Change-Id: I227ac475b855d9516e1feb881769e12ec4e7d598
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Set kvm_map in DRAMInterface in Ruby.py

The kvm_map parameter from AbstractMemory has been moved from MemCtrl
(formerly DRAMCtrl) to DRAMInterface. Assign it to DRAMInterface
instead.

Change-Id: I4508aefcf5eb859d9ffe05c81d85a1b84ee0a196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35095
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>