git.libre-soc.org Git - gem5.git/log

cpu, sim: Remove unused System::totalNumInst

This counter gets augmented for every executed instruction but it
is not used. It is also overlapping with the

BaseCPU::numSimulatedInsts

A client willing to know the number of simulated instruction should rely
on the interface above.

Change-Id: Ic5c805ac3b2e87bbacb365108d4060f53e044b4e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25305
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Let the pseudoInst dispatch function handle the return value.

When the result is returned to the caller from the pseudoInst dispatch
function, the default behavior is to not store that value using the
guestABI mechanism. In the x86 definition, I accidentally used this
version but then didn't store the result manually. The fix should simply
be to not return the result to the instruction definition and to let the
guestABI mechanism handle everything normally.

Change-Id: Ib69f266ad6314032622e5d8d69e9ff114c62657a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38195
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update ROCm to 1.6.4 in gcn Dockerfile, install HIP by .deb

Previously, we were using ROCm 1.6.2 as there were issues with some of
the machine learning applications that weren't present on 1.6.2.
However, after re-running them we've found that they, and all other
applications previously tested, run to completion.

Additionally, there have been patches to enable BLIT kernels which made
it so we no longer need to build HIP and MIOpen differently for APU and
DGPU code. This allows us to install HIP directly from the .deb packages
instead of from source. Installing from the .deb packages also avoid the
hipDeviceSynchronize() bug. Finally, this makes it so most GPU programs
can be run as-is without modifications to remove hipMalloc/hipMemcpy
calls as was done previously.

Change-Id: Ic61b09ed200b19f759d891487cde874abd607537
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37675
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Use dict.get syntax for accessing buildEnv keys

37775 removed SmartDict, which is the type buildEnv used to be.
Because of that change, doing buildEnv[key] with a key not in the dict
returns KeyError instead of False. By using buildEnv(key, False), we are
able to return False when the key isn't in the dict.

Change-Id: I4aae29b95b082efb2b021f21d608f9cd1c196379
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38135
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Add exp_cnt tracking for buffer store instructions

exp_cnt (expInstsIssued in the code) is used in the waitcnt instruction
to track that data has been read out of VGPRs in previous global
memory instructions, making it safe to overwrite the VGPRs used in said
global memory instructions.

Previously, exp_cnt wasn't being tracked at all, which lead to the
waitcnt finishing immediately, leading to the memory instruction's VPGRs
getting overwritten by subsequent instructions, causing errors.

This patch makes it so waitcnts waiting on exp_cnt will wait for MUBUF
buffer store instructions to read their VGPRs before completing

Change-Id: Idd2b59511bc086cf316217da27b7a228272b0b0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37555
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Set frequency ranges in OSC device tree nodes.

The existing device tree generation method would use the default
frequency as both the min and max frequency when setting up the OSC
device tree nodes. This would sort of work, except it seems that if
the kernel needed to adjust a frequency, it would fail to do so since
it would assume the new frequency was out of range.

Since the existing property is used to set the initial frequency of
those clocks, and because the default, min and max frequencies are all
mostly independent variables (other than obvious ordering restrictions),
two new properties were added, min_freq and max_freq, which are only
there to fill in the frequency range property in the device tree. If
they aren't set, then the device tree generation method falls back to
the old way of using the default frequency as both min and max.

Change-Id: Ie907bd673f8bcb149e69e45c5b486863149b8a68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Convert POWER to use local reg index storage.

Change-Id: Ieea4ade247f89b23266a383b604c17e740d44e3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36882
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Port util to python3

This commit is the result of running 2to3 converter on the util
subdirectory

JIRA: https://gem5.atlassian.net/browse/GEM5-832

Change-Id: I4e7e2d2b1b99f7bcc5fe0f6dc5d25880323616eb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37797
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: make ProbeListener satisfy the rule of five with deleted

Since this class has a custom destructor ~ProbeListener(), it should
also generally have the 4 other methods defined, otherwise calling
those methods lead to subtle failures.

In this specific case, the ProbeManager *const manager; field stores a
pointer back to the ProbeListener object at:

ProbeListener::ProbeListener {
manager->addListener(name, *this);

which gets unregistered by the destructor:

ProbeListener::~ProbeListener()
manager->removeListener(name, *this);

and because the default copy does not re-register anything, it leads to
unregistration.

Therefore, a copy constructor would need the manager to support multiple
identical listeners, or at least refcount them, which would be overkill.

The two move operations would be more feasible, as we could make them
unregister the old ProbeListener address and then re-register the new one,
but that is not very efficient, so we just delete them as well.

A consequence of not implementing the move methods is that it is
impossible to store ProbeListener inside an std::vector. since objects
inside std::vector may need to be moved in memory when the vector resizes,
and therefore need to be movable. The alternative is to use an std::vector
of std::unique_ptr instead.

Change-Id: I8dc0157665391f86e2ca81d144bc6a42e9312d6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: add official names to all PMU events

Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37976
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add ID_MMFR4{,EL1} system registers

Change-Id: Id50ebd2ef2e69ecbd3b7f64a4e9eafe00e283806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34876
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a gerrit bot

This bot utilizes the Gerrit REST API to query for new changes
made to Gerrit within a certain amount of time and performs a set
of tests on the changes.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I9d5af31d952bc0cd791f1569e6aac7c270e687e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34737
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Merge "misc: Merge branch hotfix v20.1.0.2 branch into develop" into develop

arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode

Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add SECURE_RD/WR flags to miscRegInfo

The introduction of Secure EL2 in gem5 requires the introduction
of new miscReg flags as there are some EL2 registers which are
accessible from secure mode only

Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37615
Tested-by: kokoro <noreply+kokoro@google.com>

dev: -Wdeprecated-copy not available on all supported compilers

This option has been introduced in:
1) gcc/9.0 [1]
2) clang/10.0.0 [2]

[1]: https://gcc.gnu.org/gcc-9/changes.html
[2]: https://releases.llvm.org/10.0.0/tools/clang/docs/ReleaseNotes.html

Change-Id: Iee9de40ca462107ec78603ffe5bc0891d6904730
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37795
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister

This register is used since the Linux kernel 5.6 aarch64 boot.

This register indicates CPU capabilities in aarch32 mode, and it has the
same value as the aarch32 ID_ISAR6 miscregister, which is also added.

The capability values of those registers are analogous to those present in
aarch64 accessible ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1, which refer to
aarch64 capabilities however, and were already implemented before this
commit.

The arm architecture document clarifies that reads to this system register
location before it had been defined should return 0, but we were faulting
instead:

> Prior to the introduction of the features described by this register,
this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Added gem5.fast clang compilation to Kokoro

Compilation issues in Clang and in compiling gem5.fast are normally
only caught during gem5's weekly, intensive, compilation checks:
http://jenkins.gem5.org/job/Compiler-Checks. The purpose of this change
is to have smaller checks on every commit, reducing the chance of
uncompilable code being submitted.

Change-Id: Idd8c6795ff73e21b1814281c31fc7ae39f09dcc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37478
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

sim: ScopedCheckpointSection to public for mappingParamIn

In clang, the following error was given:

```
In file included from build/X86/sim/eventq.hh:51:
build/X86/sim/serialize.hh:533:19: error: 'ScopedCheckpointSection' is a protected member of 'Serializable'
    Serializable::ScopedCheckpointSection sec(os, sectionName);
                  ^
build/X86/sim/serialize.hh:175:11: note: declared protected here
    class ScopedCheckpointSection {
          ^
```

The use, at line 533, was introduced in this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/36135

This can be fixed by making ScopedCheckpointSection public.

Change-Id: Ib6ffba18d5e8c37980d4febb548f2405cb45ce8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37915
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache, stats: Stats update for snoop filter

Change-Id: I339bbc4268d5b9501421a2a6a76e5267422c87aa
Signed-off-by: Maryam Babaie <mbabaie@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36355
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Convert MIPS to use local register index storage.

Change-Id: Ib691f3dd666c0877fc53b2f50dbaaf7bb4a6905b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36880
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Convert SPARC to use local register index storage.

Once all ISAs are converted, the base StaticInst class will be able to
drop its local arrays, and will no longer need to know what the global
maximum number of source or destination registers is for a given
instruction.

Most of the convertion was very simple and just involved adding tags to
declare and install the register arrays in all the class definitions.
Since SPARC has a relatively simple ISA definition, there weren't many
places that needed to be updated.

The exception was the BlockMem template, which was declaring the microop
classes within the body of the macroop. That was ok when those
declarations didn't need anything other than the name of their parent,
but now they also need to know how big to declare their arrays based on
their actual implementation.

To facilitate that, and to significantly streamline the definition of
the macroop class, the microop class definitions were moved to their own
template, and only the declaration was left in the parent class.

Change-Id: I09e6b1d1041c6a0aeaee63ce5f9a18cf482b6203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36879
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Convert X86 to use local reg index storage.

Change-Id: I42bd3e08ebcffe25e2f366be82702b3c04225e92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36883
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use the common pseudoInst dispatch function.

Instead of manually calling each of the PseudoInst implementations, this
function will automatically pick up new instructions and greatly
simplifies the ARM ISA files.

Change-Id: I6cb94b3d115f50d681ca855f80f9d7d3df6bc470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27791
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: serialize miscregs as a map

This will prevent checkpoints from breaking on every miscreg addition.

Before this commit, miscregs were stored as an array:

[system.cpu.isa]
miscRegs=965 0 0 0 0 0 0 0 0 0 0 0 17895697 ...

and after this commit they are stored as a map:

[system.cpu.isa]

[system.cpu.isa.miscRegs]
cpsr=965
spsr=0
spsr_fiq=0
spsr_irq=0
spsr_svc=0
spsr_mon=0
spsr_abt=0
spsr_hyp=0
spsr_und=0
elr_hyp=0
fpsid=0
fpscr=0
mvfr1=17895697

JIRA: https://gem5.atlassian.net/browse/GEM5-661
Change-Id: I49999c7206bd9ac1cfb81297d45c8117ff8ae675
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36116
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING

The motivation for those new methods is to prevent checkpoints from
breaking when new map entries are added.

Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
JIRA: https://gem5.atlassian.net/browse/GEM5-661
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36135
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix cache hits being profiled as cache misses

There are some instances where a cache hit is profiled as a cache
miss. This commit addresses this error.

Change-Id: I7dafa806ef3f1e3717650dc25f8657a0ea741dd1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37835
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Remove SortedDict from python utilities

The SortedDict isn't actually used. A developer willing to
use a sorted dictionary should resort to the collections.OrderedDict
instead

Change-Id: Ia2cc664eb01e59b197218ccf40ff9c680a410fb2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37796
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons, python: Remove SmartDict from python utilities

The SmartDict, used by buildEnv, has been added long time ago for
the following reasons: (checking its documentation)

---
The SmartDict class fixes a couple of issues with using the content
of os.environ or similar dicts of strings as Python variables:

1) Undefined variables should return False rather than raising KeyError.

2) String values of 'False', '0', etc., should evaluate to False
(not just the empty string).
---

These are valid reasons, but I believe they should be addressed in
a more standardized way by using a common dictionary.

1) We should simply rely on dict.get

if buildEnv.get('KEY', False/None):

2) We should discourage the use of stringified False or 0.
If we are using a dictionary, can't we just pass those values as
booleans?
The SmartDict is basically converting every value into a
string ("Variable") at every access (__getitem__)
The Variable is a string + some "basic" conversion methods
What is the problem of passing every dict value as a string?

The problem is the ambiguity on the boolean conversion.

If a variable is modelling a boolean, we can return true if
the value is 'yes', 'true'... and false if the value is
'no', 'false' etc. We should raise an exception if it is
something different, like a typo (e.g.) 'Fasle'.
But if the variable is not modelling a boolean, we don't know
how to handle that. How should we convert 'mystring' ?

If we decide to treat 'mystring' as True (which is basically
what a str.__bool__ would return) we will break typoes detection,
as 'Fasle' will now be converted to True, rather than raising
an exception.

Change-Id: I960fbfb1ec0f703e1e372dd752ee75f00632acac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37775
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Relax commit message checker to allow fixups

Change-Id: I094de0a9cb65af0ba0a8700d77cd51c6537d7beb
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37598
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

util: Use MAINTAINERS.yaml for valid tags in git hook

There is a mismatch between the tags in MAINTAINERS.yaml and the
valid_tags in the git hook. This means if a user consults the
MAINTAINERS.yaml file to find the appropriate tag, there is a chance of
the commit being rejected due to this mismatch. Now that the maintainers
file is in yaml format, use the util/maint library to parse the valid
tag options. Additional meta tags are added (WIP, RFC) and tags that
were previously valid but not in the MAINTAINERS.yaml file.

Change-Id: I3de8f0b6f8507aa1afd2118bc4373ac0610cce40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37220
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby,misc: Fix a parameter name in a DeprecatedParam message

Change-Id: Ie84a29e779187effea372c6289688f32a1db075d
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36635
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Fix toBool converter

It was using an undefined variable (result) which was mistakenly left
there after its latest refactor

Change-Id: I50bb9b1e7793045556a29306faea5f455b29819d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37755
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,stats: Update stats style for power_model and thermal_domain

Change-Id: Ie50553c301ff5790b51057dc117568374f0cbe36
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36515
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem,stats: Update stats style for mem/probes and mem/qos

Change-Id: I47a094eb8fc56ef998ec3c971dab68ba39b092e3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36476
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem,stats: Update stats style for FALRU

Change-Id: I67a202eb974a31851fbbce0f15b5377ba726bc1c
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36475
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,stats: Update stats style for CopyEngine and IdeDisk

Change-Id: Ib757b00864bc144b20adef974e3443ddba2945f0
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36436
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,stats: Update stats style of src/dev/net

Change-Id: I06c41a0506415c7a4f2608668b90d328c2789e61
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36435
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm,stats: Update stats style of src/dev/arm

Change-Id: I722e88801bb8ca0f0d75b5a1bf271fa4d4eded17
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36415
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,stats: Update stats style for base.hh and base.cc

Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36297
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-simple,stats: Update stats style

Change-Id: I1e9c7c464f1f7b4b354e9a47c7d974c6806b45da
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36295
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style for mem_dep_unit.hh

Change-Id: I9bd8e9bc331f5d57c1b6320a87b14e9b94465148
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36215
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style for cpu.hh and cpu.cc

Change-Id: If4ddaf6a9a84ea71fa19f5ca6d2e5294ec9a0b23
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style of inst_queue & inst_queue_impl

Change-Id: I95c2e194e757437fb8c3b3f530bce363e24f9a8e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36176
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3,stats: Update stats style for iew and iew_impl

Change-Id: Ie213aeb402fee5f015f10c9c03e5b9c02ba1f3fe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36095
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-minor,stats: Update stats style of MinorCPU

Change-Id: Id14e6816cc82603459bf68461ae40bf2b63080eb
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36075
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Replace xrange with range to be python3 compliant

Change-Id: I69ef5d744e2642af95383fbda920464178380757
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37716
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Use BaseMMU in the CortexR52 wrapper

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37715
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Make tlm/gem5 packet conversion flexible

We used to have a hard-coded packet2payload and payload2packet in the
tlm_bridge implementation. However, as the conversion is operated on
generic tlm payload, we're not able to handle information stored in any
user defined SystemC extensions.

In this CL, we add a pair of function to register extra conversion steps
between tlm payload and gem5 packet. This decouples the exact conversion
logic and enables SystemC users to register any necessary steps for
their extensions.

Change-Id: I70b3405395fed0f757f0fb7e19136f47d84ac115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37075
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add some format strings to the parser for reg indexes.

There are two new strings, reg_idx_arr_decl which declares the source
and dest register index arrays, and set_reg_idx_arr which installs them
in the base class.

The set_reg_idx_arr code needs to implicitly figure out what type to use
based on the type of the "this" pointer. The name of the containing
class is not *necessarily* the same as class_name, since the generated
code can use that name, something based on that name, or whatever else
it wants. No other format string (other than class_name itself) uses the
class name internally, so we can't count on that working in existing ISA
definitions.

Change-Id: Id995a46896e71a2fcf3103c34a1e1e67e24f88f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36878
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Add an StaticInst accessor for setting register index storage.

Change-Id: I66adccd8851f035b5d61ace9153ae7acc57403ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36877
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-minor: this is a bug fix for MinorCPU for thread cloning.

Inside the code of cloneFunc(…)  //syscall_emul.hh

    cp->initState();  //line 1483
    p->clone(tc, ctc, cp, flags);  //line 1484
    …
    ctc->clearArchRegs(); //line 1503

    OS::archClone(flags, p, cp, tc, ctc, newStack, tlsPtr); //line 1505
    …

At line 1483, initState() is called and the activateContext() of the
corresponding MinorCPU is eventually called. The actual architecture
clone happens at line 1505 where PC of the new thread could have a
correct value.

In the existing implementation of MinorCPU::activateContext(ThreadID
thread_id), the below line 275 is called
    pipeline->wakeupFetch(thread_id);
to start fetching instruction with current value of PC, which is 0x0,
leading to panic “Page table fault when accessing virtual address 0”.

This is because the OS::archClone() is not yet called. So, the below bug
fix handles the wakeup fetch for a thread for two scenarios:
   ...
    if (!threads[thread_id]->getUseForClone())
    { //the thread is not cloned
        pipeline->wakeupFetch(thread_id);
    } else {//the thread from clone
        if (fetchEventWrapper != NULL)
            delete fetchEventWrapper;
        fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
          {pipeline->wakeupFetch(thread_id);}, "wakeupFetch");
        schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
    }
    ...
If a thread is not cloned, pipeline->wakeupFetch() is called
immediately.
For the cloned thread, the above bug fix delays the execution of
    pipeline->wakeupFetch()
after the OS::archClone is done. ThreadContext::getUseForClone() return
true if a thread is cloned.

A member variable fetchEventWrapper is added to MinorCPU class for
delayed fetch event.

A member variable useForClone and its corresponding get/set methods are
added to ThreadContext class. This approach allows future reuse of this
useForClone variable by other CPU models if needed and also avoid lots
of changes resulted by modifying parameters of activateContext () and
activate() which are defined as override.

Inside the syscall cloneFunc, the useForClone member of a ThreadContext
object is set via its set method right before Process's initState() is
called, shown as below.
    ctc->setUseForClone(true);
    cp->initState();
    p->clone(tc, ctc, cp, flags);

A few previously failed RISC-V ASM tests have been open in tests.py file
after the bug fix works.

JIRA issue: https://gem5.atlassian.net/browse/GEM5-374

Change-Id: Ibffe46522e2617443d29f49df180692c54830f14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37315
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix object scope in the CPUID code.

The original version of the code takes a pointer from a temporary object
which gets destroyed before the pointer is used.

Change-Id: I16af4eefdf202f769a672e230330d8e0bfce3bb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37695
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3,misc: Added missing overrides to gpu_thread.hh

Compiling GCN3 with clang will result in errors within this change.

Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37538
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>

cpu: Access src and dest reg indexes using a pointer to member.

This will eventually let subclasses provide their own appropriately
sized storage for these indexes. By using a pointer to member instead of
a regular pointer, we ensure that even if the StaticInst is copied/moved
somewhere, it will still find its indexes correctly, without any
additional performance overhead or maintenance.

Unfortunately C++ has decided that arrays with known bounds are not
convertible/compatible with arrays with unknown bounds. I've found at
least two standards proposals in various stages of acceptance which say
that that's dumb and they should change that (because it's dumb and they
should change that), but in the mean time we can get everything to
compile by using the reinterpret_cast hammer. While this is
*technically* undefined behavior, it's basically not and should be
pretty safe.

Change-Id: Id747b0cf68d1a0b4809ebb66a32472187110d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36876
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-gcn3, misc: Added missing override to protocol_tester.hh

Clang will return a missing-override error when compiling X86_GCN4
without this change.

Change-Id: Ib5fd9ba5c27ddc15561198bfc90d27b7599a7923
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37537
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-sparc,misc: Added M5_VAR_USED to SparcProcess var

Compiling sparc/gem5.fast fails without specifying this variable is
used.

Change-Id: I86aa5c6495de111421458c2b62200ddb2a89076e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache,misc: Added missing override to operator

Clang compilation was failing in error due to this missing override.

Change-Id: I92f1774cd2f1f5ef90ab1d72d038f6c65cba70ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37535
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Delete the unused DLAB member in the 8250 UART.

This value is never actually used. The value is computed from the LCR
each time it's needed instead.

Change-Id: I6dc5580eb03174f32b8a381cd2974f742b8eb472
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36817
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Convert the IDE controller to use the RegisterBank types.

Also get rid of the "ideConfig" register which does not actually show up
in the spec corresponding to this device's PCI IDs.

Change-Id: Id5d109403f49d956c696371b4d93d26150cc96dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36816
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Explicitly sign-extend simm16

In some instructions, simm16 needs to be sign extended. Previous code
simply casted the simm16 to a 32-bit or 64-bit datatype, however this
didn't actually sign-extend the value.

This patch explicitly calls sext<16> on simm16 whenever it's supposed
to be sign-extended.

Change-Id: I32f02e51fbab220d1a73dc7e68c7410937db21c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37495
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix deadlock in VIPERCoalescer

Certain instructions (some atomics and buffer_wbinvl1_vol) deadlock
in the coalescer, where sendTimingReq fails, fails a retry, and then
never retries again.

This fix sets m_cache_inv_pkt to null before calling
completeHitCallback(), as that allows the failed packets to be retried
again.

Change-Id: I4a51c741360f385f8b4c3f2a31a9410f18e095d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37477
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Implement flat_load_sbyte instruction

Change-Id: I3aa7547a393b9ecb4b3d4d107394c54d690a0ac2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37476
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Implement s_setreg_imm32_b32 instruction

Change-Id: I5383243403156dc17d4997106085a62fb0483fec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37475
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implementation ARMv8.1 RDMA

Adding RDMA implementation for ARMv8.1
+ isa/formats/*: Adding decoding of Aarch64 and aarch32 instructions
+ isa/insts/neon.isa\neon64.isa: Adding function instructions

Change-Id: I430e8880723f373ffffa50079a87fd4ecc634d86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Prevent undefined behavior in not interleaved `AddrRange`s.

If an `AddrRange` is not interleaved, return the input address in
`removeIntlvBits` and `addIntlvBits` to prevent undefined behavior. It
allows to use these methods in all cases without having to check
manually whether the range is interleaved.

Change-Id: Ic6ac8c4e52b09417bc41aa9380a24319c34e0b35
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37617
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

fastmodel: Wrap the PL330 DMA controller fast model.

Change-Id: I0290e52ede4dca1252ca224abcc85c2c8086ea3c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37216
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Merge branch hotfix v20.1.0.2 branch into develop

This merge commit also reverts the version info back to
'DEVELOP-FOR-V20.2' for the develop branch.

Change-Id: If6fd326cc23edf2aeaa67353d4d3fed573e9ddd6

misc: Updated the RELEASE-NOTES and version number

Updated the RELEASE-NOTES.md and version number for the v20.1.0.2
hotfix release.

Change-Id: Ibb6b62a36bd1f9084f7d8311ff1f94b8564dbe9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-hsa,gpu-compute: Agent Packet handler implemented.

HSA packet processor will now accept and process agent packets.

Type field in packet is command type.
For now:
AgentCmd::Nop = 0
AgentCmd::Steal = 1

Steal command steals the completion signal for a running kernel.
This enables a benchmark to use hsa primitives to send an agent
packet to steal the signal, then wait on that signal.

Minimal working example to be added in gem5-resources.

Change-Id: I37f8a4b7ea1780b471559aecbf4af1050353b0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37015
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: move serialize and unserialize definition to cpp file

Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,cpu,mem: Use templatized SatCounter

Change the deprecated SatCounter instances to the new type-size-
aware SatCounters.

Jira: https://gem5.atlassian.net/browse/GEM5-813

Change-Id: Ie943c553dd8a8c24c80e737783708b033ce001da
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

base: Templatize SatCounter

Allow SatCounter to have larger unsigned types to accomodate
larger counters.

The template decision was taken because some predictors will
generate huge arrays of small counters, so smaller types will
lessen their overhead; however, isolated counters may require
any counter size.

Jira: https://gem5.atlassian.net/browse/GEM5-813

Change-Id: I5475a565ea7b97d1dfc176fa9d7cf827560fbe39
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37135
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,stats: Fix incorrect stat names of ThreadStateStats

Previously, ThreadStateStats uses ThreadState::threadId() to
determine the name of the stats. However, in the ThreadState
constructor, ThreadStateStats is initialized before ThreadState
is intialized. As a result, the name of ThreadStateStats has
a wrong ThreadID.

This commit uses ThreadID instead of ThreadState to determine
the name of the stats.

This causes a name collision between ThreadStateStats and
ExecContextStats as both have the name of "thread_[tid]".
Ideally, those stats should be merged to the BaseSimpleCPU.
However, both ThreadStateStats and ExecContextStats have
a stat named numInsts. So, for now, ExecContextStats will
have a name of "exec_context.thread_[tid]", while ThreadStateStats
keeps its name.

Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37455
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add support for GRPC protobuf files.

These files are used to generate stubs for calling across GRPC
protocols, an RPC mechanism which is based around the protocol buffer
system.

The support for these files is heavily based on and calls into the
existing protobuf file support, but with the extra step which generates
the additional .grpc.pb.cc and .grpc.pb.h files.

Change-Id: I89022928c08aa9f7ed024b7380ddcc54ca75b55e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37277
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Convert ProtoBuf to use a scons Builder and Scanner.

There are several benefits to using a Builder. First, the action we're
executing is shared between all uses of the Builder. The number of
times this particular builder is called is small, but it should still
be a little more efficient.

Second, we can use SCons's emitter mechanism to generate the .pb.cc and
.pb.h target files in a little more general way.

Also, this change adds a Scanner for .proto files which will scan them
for imports and let SCons manage those implicit dependencies properly.
The scanner is a bit simplistic as described in a comment in the
source, but should work pretty well in practice with reasonably
formatted files, and in particular some files I'm working with that
include imports.

Change-Id: Iaf2498e61133d6f713d6ccaf199422b882c5894f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37276
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Consolidate the ProtoBuf code.

The ProtoBuf support in src/SConscript was split into two parts, one
where the ProtoBuf sources were declared, and the other where scons was
told how to buld the .cc and .hh files and the .cc was added to the
build.

As far as I can tell, there was no real reason to have things split up
like that, at least not currently. This change moves everything into
the ProtoBuf class definition, and this should behave the same as
before but be a little easier to understand and maintain.

Change-Id: I02320f50ece53d90c14b5062bd6b1167210f46c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37275
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Fix how directories are handled for protobuf files.

There were two issues with how paths were handled for these files.

1. The code in the ProtoBuf class would drop the subdirectory part of
the path name when generating the name of the .cc and .h files the
protoc compiler would output. Since protoc wouldn't generate files
where scons expected, it would fail when it tried to build the .cc.

2. protoc will use the --proto_path and --cpp_out settings to figure
out what path to use for generated files. It will remove the
--proto_path prefix it found the .proto file with from the files path,
and then add the rest to the --cpp_out prefix.

The input files should come from the build directory using symlinks
set up by scons, and the output files should end up alongside them.
That means the --proto_path setting should be the build directory, and
so should --cpp_out. That's fortunately simpler than what was there
before, since it doesn't depend on what the source or targets are.

Change-Id: I69692d2fe3813011982f0c1c9824589a132f93ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37218
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Remove "inline" from a method in one of the prefetchers.

The function was defined in a .cc file but marked as inline. gcc seems
to often figure out what it should do, but in clang it doesn't export
the function (since it's marked as inline), and during linking external
references, which don't have a local copy since it's not defined in the
.hh file, will fail.

This failure looks particularly odd because the funciton is virtual,
and so the failure is reported as being unable to compose the vtable
in places where the object is constructed, relatively obscure code
which is generated by the build system and obscured by templates from
an external code base (pybind11).

Change-Id: Ib51aefbf9005e4ca8dfebef32c5def472175f115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37436
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Override print function of sector and super blocks

Pass management of printing sector and super block's contents to them.

Change-Id: Ided8d404450a0fa39127ac7d2d6578d95691f509
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36582
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use the compression factor to co-allocate

The compression factor of a block is measured according to the maximum
achievable compression ratio.

For example, if up to 4 blocks can co-allocate in a superblock, and
a cache line has 512 bits, the possible compression factors are 1
(uncompressed, <=512 bits), 2 (compressed, <=256 bits), 4 (compressed,
<=128 bits).

This is an approach similar to the one described in "Yet Another
Compressed Cache", by Sardashti et al.

Change-Id: I52ef36989f3eeef6fc8890132a57f995ef9c5258
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36581
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Set compression bit with its size

When setting the size of a compressed block, its compressibility
needs to be recalculated based on that, so move such functionality
to be done after the block has been inserted, within setSizeBits.

As a side effect, insertBlock does not need to be overridden
anymore.

Change-Id: I608f876cd2110ac5e394ffad5b29941ba458ba91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36580
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add data expansion and compaction checking functions

Data expansion and compaction are determined according to the compaction
method being used. Therefore, do the verification on the blocks instead
of the cache.

Change-Id: I652418a5f4c6d5b946a9925d6287a995f262f02a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36579
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Allow moving data contractions

Data contractions happen when a block passes from a less compressed
(e.g., uncompressed) to a more compressed (e.g., compressed) state.

Some compaction methods enforce that a block can only be allocated
in a location matches an exact compression factor, thus on data
contractions such blocks must be moved to another location, or
they must be padded to fake a bigger size.

For compaction methods that do not have that limitation, performance
can be improved if the contracted block is moved to co-allocate with
another existing entry, since it frees up an entry.

Change-Id: I302bc561b897f9d3ce1426331fe4b5c2df76f4b5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36578
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use RP for data expansion victimization

When searching for victims of a data expansion a simple approach to
make room for the expanded block is to evict every co-allocatable
block. This, however, ignores replacement policies and tends to be
inefficient. Besides, some cache compaction policies do not allow
blocks that changed their compression ratio to be allocated in the
same location (e.g., Skewed Compressed Caches), so they must be
moved elsewhere.

The replacement policy approach asks the replacement policy which
block(s) would be the best to evict in order to make room for the
expanded block. The other approach, on the other hand, simply evicts
all co-allocated entries. In the case the replacement policy selects
the superblock of the block being expanded, we must make sure the
latter is not evicted/moved by mistake.

This patch also allows the user to select which approach they would
like to use.

Change-Id: Iae57cf26dac7218c51ff0169a5cfcf3d6f8ea28a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36577
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add function to move blocks in the tags

Add a function to allow moving a block's metadata from a source
entry to an invalid destination entry.

Change-Id: I7c8adbcd1133c907f1eea7f69dca983215bc3960
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36576
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add move assign and delete move constr of blk

Some cache techniques may need to move a block's metadata information
into another block. This must have some limitations to avoid mistakes:
- The destination entry must be invalid, otherwise the replacement
  policy steps would be skipped.
- The source entry must be valid, otherwise there would be no point
  in moving their metadata contents.
- The entries locations (set, way, offset...) must not be moved, since
  they are fixed. The same principle is applied to the location specific
  variables, such as the replacement pointer

Why it would be used:
For example, when using compression, and a block goes from uncompressed
to compressed state due to an overwrite, after the tag lookup
(sequential access) it can be decided whether to store the new data in
the old location, or, since we might have already found the block's co-
allocatable blocks, move it to co-allocate.

Other examples of techniques that could use this functionality are
Skewed Compressed Caches, and ZCaches.

Change-Id: I96e4f8cc8c992c4b01f315251d1a75d51c28692c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36575
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated MAINTAINERS.yaml

Change-Id: Ibda441858a22c9e8bb22e132c165e7724aaf7539
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37356
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm,misc: Added missing override to scmi_platform functions

The missing overrides on the "raiseInterrupt" and "clearInterrupt"
resulted in compilation failures when using Clang.

Change-Id: Ic77e8587cd622f8f0cb819c3230893a1b169a2a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37355
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a library to parse MAINTAINERS.yaml

Add a very simple library to parse MAINTAINERS.yaml. There are
currently no tools that use the library, but it can be tested using
`python3 -m "maint.lib.maintainers"` from within the util directory.

Change-Id: Id2edff94451f27e0b601994d198d0647325e4b35
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37036
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix MemorySize division

The memory size is expected to be an integer.

Jira: https://gem5.atlassian.net/browse/GEM5-806

Change-Id: I44b2d423a3478d2598950779222151f09970cbd8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37255
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>

arch-power: Implement mcrxr

Implement the mcrxr instruction (Move to Condition Register from XER
X-form) as defined on p.132 of the green-cloth book:
The contents of XER<0:3> are copied into the Condition Register field
designated by BF. XER<0:3> are set to zero.

Change-Id: I82ae3d98e1eaf9182e90c0c86afe0f13d4a052e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37295
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Make the NonCachingSimpleCPU use a back door for fetch.

If the memory system can provide a back door to memory, store that, and
use it for subsequent accesses to the range it covers. For now, this
covers only fetch. That's because fetch will generally happen more than
loads and stores, and because it's relatively simple to implement since
we can ignore atomic operations, etc.

Some limitted benchmarking suggests that this speeds up x86 linux boot
by about 20%, although my modifications to the config to remove caching
(which blocks the back door mechanism) also made gem5 crash, so it's
hard to say for sure if that's a valid result. The crash happened in the
same way before and after, so it's probably at least relatively
representative.

While this gives a pretty substantial performance boost, it will prevent
statistics from being collected at the memory, or on intermediate objects
in the interconnect like the bus. That is to be expected with this
memory mode, however.

Change-Id: I73f73017e454300fd4d61f58462eb4ec719b8d85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36979
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update python version for GCN3

The Python version installed in the Dockerfile for GCN3 by apt-get is
too old to build gem5. This bumps the version to the most recent Python
to avoid needing to update this file too much.

Python 3.9 is install via PPA since it is not available in the official
Ubuntu 16.04 repository. Likewise, pip is installed from "source" as it
is not available for Python 3.9 in from neither the PPA nor Ubuntu.

Change-Id: Ia919f31cf9c9063e1df091cea15590526715739b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37219
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix `AddrRange::addIntlvBits(Addr)` and new test.

The methods `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` should be the inverse of one another,
but the latter did not insert the blanks for filling the removed bits in
the correct positions.  Since the masks are ordered increasingly by the
position of the least significant bit of each mask, the lowest bit that
has to be inserted at each iteration is always `intlv_bit`, not needing
to be shifted to the left or right.  The bits that need to be copied
from the input address are `intlv_bit-1..0` at each iteration.

The test `AddrRangeTest.AddRemoveInterleavBitsAcrossRange` has been
updated have masks below bit 12, making the old code not pass the test.
A new `AddrRangeTest.AddRemoveInterleavBitsAcrossContiguousRange` test
has been added to include a case in which the previous code fails.  The
corrected code passes both tests.

This function is not used anywhere other than the tests and the class
`ChannelAddr`.  However, it is needed to efficiently implement
interleaved caches in the classic mode.

Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Add realview64-kvm.py test to quick regressions

By using the valid_host parameter we can make sure the test is
run on a aarch64 host only

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3cdb35967e85377f26adf73ad147cb2479162ca1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31219
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

tests: Add realview64-kvm.py testing platform

Change-Id: If9952563413b4c7462a3ddf46c40358023d5bc60
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31218
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update guest binaries used by regressions

The new tarball (aarch-system-20200611.tar.bz2) contains the
m5_exit_addr.squashfs.arm64 disk image to be used by KVM regressions

This disk image is based on a memory mapped m5 exit

Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37177
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>