yosys.git
5 years agoAdd more comments
Eddie Hung [Fri, 9 Aug 2019 16:48:17 +0000 (09:48 -0700)]
Add more comments

5 years agoAdd a few comments to document $alu and $lcu
Eddie Hung [Thu, 8 Aug 2019 17:05:28 +0000 (10:05 -0700)]
Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1248 from YosysHQ/eddie/abc9_speedup
Eddie Hung [Wed, 7 Aug 2019 19:25:26 +0000 (12:25 -0700)]
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup

abc9: speedup by using using "clean" more efficiently

5 years agoAdd comment
Eddie Hung [Tue, 6 Aug 2019 20:20:32 +0000 (13:20 -0700)]
Add comment

5 years agoRevert "Add TODO"
Eddie Hung [Tue, 6 Aug 2019 20:19:21 +0000 (13:19 -0700)]
Revert "Add TODO"

This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.

5 years agoAdd TODO
Eddie Hung [Fri, 2 Aug 2019 05:30:10 +0000 (22:30 -0700)]
Add TODO

5 years agoCompute box_lookup just once
Eddie Hung [Fri, 2 Aug 2019 05:21:56 +0000 (22:21 -0700)]
Compute box_lookup just once

5 years agoRun "clean" on mapped_mod in its own design
Eddie Hung [Fri, 2 Aug 2019 05:21:30 +0000 (22:21 -0700)]
Run "clean" on mapped_mod in its own design

5 years agoRun "clean -purge" on holes_module in its own design
Eddie Hung [Fri, 2 Aug 2019 05:21:14 +0000 (22:21 -0700)]
Run "clean -purge" on holes_module in its own design

5 years agoMerge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
David Shah [Wed, 7 Aug 2019 14:35:29 +0000 (15:35 +0100)]
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes

ecp5: Make cells_sim.v consistent with nextpnr

5 years agoecp5: Make cells_sim.v consistent with nextpnr
David Shah [Wed, 7 Aug 2019 13:19:31 +0000 (14:19 +0100)]
ecp5: Make cells_sim.v consistent with nextpnr

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1213 from YosysHQ/eddie/wreduce_add
Clifford Wolf [Wed, 7 Aug 2019 12:27:35 +0000 (14:27 +0200)]
Merge pull request #1213 from YosysHQ/eddie/wreduce_add

wreduce/opt_expr: improve width reduction for $add and $sub cells

5 years agoMerge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Clifford Wolf [Wed, 7 Aug 2019 10:31:32 +0000 (12:31 +0200)]
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor

 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.

5 years agoMerge pull request #1249 from mmicko/anlogic_fix
Clifford Wolf [Wed, 7 Aug 2019 10:30:52 +0000 (12:30 +0200)]
Merge pull request #1249 from mmicko/anlogic_fix

anlogic : Fix alu mapping

5 years agoMerge pull request #1252 from YosysHQ/clifford/fix1231
Clifford Wolf [Wed, 7 Aug 2019 10:14:54 +0000 (12:14 +0200)]
Merge pull request #1252 from YosysHQ/clifford/fix1231

Fix handling of functions/tasks without top-level begin-end block

5 years agoMerge pull request #1253 from YosysHQ/clifford/check
Clifford Wolf [Wed, 7 Aug 2019 10:14:41 +0000 (12:14 +0200)]
Merge pull request #1253 from YosysHQ/clifford/check

Be less aggressive with running design->check()

5 years agoMerge pull request #1257 from YosysHQ/clifford/cellcosts
Clifford Wolf [Wed, 7 Aug 2019 10:13:50 +0000 (12:13 +0200)]
Merge pull request #1257 from YosysHQ/clifford/cellcosts

Redesign of cell cost API

5 years agoUpdate CHANGELOG
David Shah [Wed, 7 Aug 2019 09:56:32 +0000 (10:56 +0100)]
Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1241 from YosysHQ/clifford/jsonfix
David Shah [Wed, 7 Aug 2019 09:40:38 +0000 (10:40 +0100)]
Merge pull request #1241 from YosysHQ/clifford/jsonfix

Improved JSON attr/param encoding

5 years agoTweak default gate costs, cleanup "stat -tech cmos"
Clifford Wolf [Wed, 7 Aug 2019 08:25:51 +0000 (10:25 +0200)]
Tweak default gate costs, cleanup "stat -tech cmos"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRedesign of cell cost API
Clifford Wolf [Tue, 6 Aug 2019 23:12:14 +0000 (01:12 +0200)]
Redesign of cell cost API

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd signed opt_expr tests
Eddie Hung [Tue, 6 Aug 2019 22:40:30 +0000 (15:40 -0700)]
Add signed opt_expr tests

5 years agoAdd signed test
Eddie Hung [Tue, 6 Aug 2019 22:38:43 +0000 (15:38 -0700)]
Add signed test

5 years agoMove LSB-trimming functionality from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:25:50 +0000 (15:25 -0700)]
Move LSB-trimming functionality from wreduce to opt_expr

5 years agoAdd SigSpec::extract_end() convenience function
Eddie Hung [Tue, 6 Aug 2019 22:25:11 +0000 (15:25 -0700)]
Add SigSpec::extract_end() convenience function

5 years agoRestore original SigSpec::extract()
Eddie Hung [Tue, 6 Aug 2019 22:24:55 +0000 (15:24 -0700)]
Restore original SigSpec::extract()

5 years agoMove LSB tests from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:24:49 +0000 (15:24 -0700)]
Move LSB tests from wreduce to opt_expr

5 years agoMerge remote-tracking branch 'origin/master' into eddie/wreduce_add
Eddie Hung [Tue, 6 Aug 2019 21:50:00 +0000 (14:50 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add

5 years agoMerge pull request #1232 from YosysHQ/dave/write_gzip
David Shah [Tue, 6 Aug 2019 18:05:35 +0000 (19:05 +0100)]
Merge pull request #1232 from YosysHQ/dave/write_gzip

Add support for writing gzip-compressed files

5 years agoBe less aggressive with running design->check()
Clifford Wolf [Tue, 6 Aug 2019 17:21:37 +0000 (19:21 +0200)]
Be less aggressive with running design->check()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd test for writing gzip-compressed files
David Shah [Wed, 31 Jul 2019 12:58:27 +0000 (13:58 +0100)]
Add test for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd support for writing gzip-compressed files
David Shah [Mon, 29 Jul 2019 08:28:31 +0000 (09:28 +0100)]
Add support for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoFix handling of functions/tasks without top-level begin-end block, fixes #1231
Clifford Wolf [Tue, 6 Aug 2019 16:06:14 +0000 (18:06 +0200)]
Fix handling of functions/tasks without top-level begin-end block, fixes #1231

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1251 from YosysHQ/clifford/nmux
Clifford Wolf [Tue, 6 Aug 2019 13:18:18 +0000 (15:18 +0200)]
Merge pull request #1251 from YosysHQ/clifford/nmux

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

5 years agoAdd $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Clifford Wolf [Tue, 6 Aug 2019 02:47:55 +0000 (04:47 +0200)]
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoanlogic : Fix alu mapping
Miodrag Milanovic [Sat, 3 Aug 2019 12:47:33 +0000 (14:47 +0200)]
anlogic : Fix alu mapping

5 years agoMerge pull request #1242 from jfng/fix-proc_prune-partial
whitequark [Sat, 3 Aug 2019 07:08:41 +0000 (07:08 +0000)]
Merge pull request #1242 from jfng/fix-proc_prune-partial

proc_prune: Promote partially redundant assignments.

5 years agoMerge pull request #1238 from mmicko/vsbuild_fix
Clifford Wolf [Fri, 2 Aug 2019 15:07:39 +0000 (17:07 +0200)]
Merge pull request #1238 from mmicko/vsbuild_fix

Visual Studio build fix

5 years agoMerge pull request #1239 from mmicko/mingw_fix
Clifford Wolf [Fri, 2 Aug 2019 14:37:57 +0000 (16:37 +0200)]
Merge pull request #1239 from mmicko/mingw_fix

Fix formatting for msys2 mingw build

5 years agoMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
Eddie Hung [Thu, 1 Aug 2019 16:38:55 +0000 (09:38 -0700)]
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map

xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER

5 years agoFix linking issue for new mxe and pthread
Miodrag Milanovic [Wed, 31 Jul 2019 16:02:27 +0000 (18:02 +0200)]
Fix linking issue for new mxe and pthread

5 years agoFix yosys linking for mxe
Miodrag Milanovic [Wed, 31 Jul 2019 15:31:07 +0000 (17:31 +0200)]
Fix yosys linking for mxe

5 years agoNew mxe hacks needed to support 2ca237e
Miodrag Milanovic [Wed, 31 Jul 2019 15:30:48 +0000 (17:30 +0200)]
New mxe hacks needed to support 2ca237e

5 years agoFix formatting for msys2 mingw build using GetSize
Miodrag Milanovic [Wed, 31 Jul 2019 09:49:48 +0000 (11:49 +0200)]
Fix formatting for msys2 mingw build using GetSize

5 years agoproc_prune: Promote partially redundant assignments.
Jean-François Nguyen [Wed, 31 Jul 2019 12:26:09 +0000 (14:26 +0200)]
proc_prune: Promote partially redundant assignments.

5 years agoUpdate JSON front-end to process new attr/param encoding
Clifford Wolf [Thu, 1 Aug 2019 10:48:22 +0000 (12:48 +0200)]
Update JSON front-end to process new attr/param encoding

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImplement improved JSON attr/param encoding
Clifford Wolf [Thu, 1 Aug 2019 10:34:52 +0000 (12:34 +0200)]
Implement improved JSON attr/param encoding

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoSupport explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semanti...
Jim Lawson [Wed, 31 Jul 2019 16:27:38 +0000 (09:27 -0700)]
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.

5 years agoMerge pull request #1233 from YosysHQ/clifford/defer
Clifford Wolf [Wed, 31 Jul 2019 11:30:52 +0000 (13:30 +0200)]
Merge pull request #1233 from YosysHQ/clifford/defer

Call "read_verilog" with -defer from "read"

5 years agoVisual Studio build fix
Miodrag Milanovic [Wed, 31 Jul 2019 07:10:24 +0000 (09:10 +0200)]
Visual Studio build fix

5 years agoMerge remote-tracking branch 'upstream/master'
Jim Lawson [Tue, 30 Jul 2019 23:04:27 +0000 (16:04 -0700)]
Merge remote-tracking branch 'upstream/master'

5 years agoRST -> RSTBRST for RAMB8BWER
Eddie Hung [Mon, 29 Jul 2019 23:05:44 +0000 (16:05 -0700)]
RST -> RSTBRST for RAMB8BWER

5 years agoMerge pull request #1228 from YosysHQ/dave/yy_buf_size
Eddie Hung [Mon, 29 Jul 2019 16:16:09 +0000 (09:16 -0700)]
Merge pull request #1228 from YosysHQ/dave/yy_buf_size

verilog_lexer: Increase YY_BUF_SIZE to 65536

5 years agoMerge pull request #1234 from mmicko/fix_gzip_no_exist
David Shah [Mon, 29 Jul 2019 14:50:20 +0000 (15:50 +0100)]
Merge pull request #1234 from mmicko/fix_gzip_no_exist

Fix case when file does not exist

5 years agoFix case when file does not exist
Miodrag Milanovic [Mon, 29 Jul 2019 10:29:13 +0000 (12:29 +0200)]
Fix case when file does not exist

5 years agoUpdate README to use "read" instead of "read_verilog"
Clifford Wolf [Mon, 29 Jul 2019 08:40:30 +0000 (10:40 +0200)]
Update README to use "read" instead of "read_verilog"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCall "read_verilog" with -defer from "read"
Clifford Wolf [Mon, 29 Jul 2019 08:29:36 +0000 (10:29 +0200)]
Call "read_verilog" with -defer from "read"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1226 from YosysHQ/dave/gzip
David Shah [Sat, 27 Jul 2019 06:40:38 +0000 (07:40 +0100)]
Merge pull request #1226 from YosysHQ/dave/gzip

Add support for gzip'd input files

5 years agoUpdate CHANGELOG
David Shah [Fri, 26 Jul 2019 14:53:21 +0000 (15:53 +0100)]
Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
5 years agoverilog_lexer: Increase YY_BUF_SIZE to 65536
David Shah [Fri, 26 Jul 2019 12:35:39 +0000 (13:35 +0100)]
verilog_lexer: Increase YY_BUF_SIZE to 65536

Signed-off-by: David Shah <dave@ds0.me>
5 years agoFix frontend auto-detection for gzipped input
David Shah [Fri, 26 Jul 2019 09:29:05 +0000 (10:29 +0100)]
Fix frontend auto-detection for gzipped input

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd support for reading gzip'd input files
David Shah [Fri, 26 Jul 2019 09:23:58 +0000 (10:23 +0100)]
Add support for reading gzip'd input files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Thu, 25 Jul 2019 17:49:26 +0000 (10:49 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoBump abc to fix &mfs bug
Eddie Hung [Thu, 25 Jul 2019 17:44:20 +0000 (10:44 -0700)]
Bump abc to fix &mfs bug

5 years agoMerge branch 'ZirconiumX-synth_intel_m9k'
Clifford Wolf [Thu, 25 Jul 2019 15:23:48 +0000 (17:23 +0200)]
Merge branch 'ZirconiumX-synth_intel_m9k'

5 years agoMerge pull request #1218 from ZirconiumX/synth_intel_iopads
Clifford Wolf [Thu, 25 Jul 2019 15:19:54 +0000 (17:19 +0200)]
Merge pull request #1218 from ZirconiumX/synth_intel_iopads

intel: Make -noiopads the default

5 years agoMerge pull request #1219 from jakobwenzel/objIterator
Clifford Wolf [Thu, 25 Jul 2019 15:19:11 +0000 (17:19 +0200)]
Merge pull request #1219 from jakobwenzel/objIterator

made ObjectIterator comply with Iterator Interface

5 years agoMerge pull request #1224 from YosysHQ/xilinx_fix_ff
Eddie Hung [Thu, 25 Jul 2019 13:44:17 +0000 (06:44 -0700)]
Merge pull request #1224 from YosysHQ/xilinx_fix_ff

xilinx: Fix missing cell name underscore in cells_map.v

5 years agoreplaced std::iterator with using statements
Jakob Wenzel [Thu, 25 Jul 2019 07:51:09 +0000 (09:51 +0200)]
replaced std::iterator with using statements

5 years agoxilinx: Fix missing cell name underscore in cells_map.v
David Shah [Thu, 25 Jul 2019 07:19:07 +0000 (08:19 +0100)]
xilinx: Fix missing cell name underscore in cells_map.v

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1222 from koriakin/s6-example
Eddie Hung [Wed, 24 Jul 2019 17:51:03 +0000 (10:51 -0700)]
Merge pull request #1222 from koriakin/s6-example

Add a simple example for Spartan 6

5 years agoMerge remote-tracking branch 'upstream/master'
Jim Lawson [Wed, 24 Jul 2019 17:20:46 +0000 (10:20 -0700)]
Merge remote-tracking branch 'upstream/master'

5 years agoAdd a simple example for Spartan 6
Marcin Kościelnicki [Wed, 24 Jul 2019 16:41:39 +0000 (18:41 +0200)]
Add a simple example for Spartan 6

5 years agomade ObjectIterator extend std::iterator
Jakob Wenzel [Wed, 24 Jul 2019 11:33:07 +0000 (13:33 +0200)]
made ObjectIterator extend std::iterator

this makes it possible to use std algorithms on them

5 years agointel: Make -noiopads the default
Dan Ravensloft [Wed, 24 Jul 2019 09:38:15 +0000 (10:38 +0100)]
intel: Make -noiopads the default

5 years agointel: Map M9K BRAM only on families that have it
Dan Ravensloft [Mon, 22 Jul 2019 11:15:22 +0000 (12:15 +0100)]
intel: Map M9K BRAM only on families that have it

This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.

5 years agoMerge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp
Eddie Hung [Tue, 23 Jul 2019 16:56:58 +0000 (09:56 -0700)]
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp

ice40: Fix SB_MAC16 sim model for signed modes

5 years agoMerge pull request #1214 from jakobwenzel/astmod_clone
Eddie Hung [Mon, 22 Jul 2019 14:42:53 +0000 (07:42 -0700)]
Merge pull request #1214 from jakobwenzel/astmod_clone

initialize noblackbox and nowb in AstModule::clone

5 years agoinitialize noblackbox and nowb in AstModule::clone
Jakob Wenzel [Mon, 22 Jul 2019 08:37:40 +0000 (10:37 +0200)]
initialize noblackbox and nowb in AstModule::clone

5 years agoAdd "stat -tech cmos"
Clifford Wolf [Sat, 20 Jul 2019 13:06:28 +0000 (15:06 +0200)]
Add "stat -tech cmos"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoTry and fix again
Eddie Hung [Fri, 19 Jul 2019 21:40:57 +0000 (14:40 -0700)]
Try and fix again

5 years agoAdd another test
Eddie Hung [Fri, 19 Jul 2019 21:02:46 +0000 (14:02 -0700)]
Add another test

5 years agoDo not access beyond bounds
Eddie Hung [Fri, 19 Jul 2019 20:58:50 +0000 (13:58 -0700)]
Do not access beyond bounds

5 years agoAdd an SigSpec::at(offset, defval) convenience method
Eddie Hung [Fri, 19 Jul 2019 20:54:57 +0000 (13:54 -0700)]
Add an SigSpec::at(offset, defval) convenience method

5 years agoWrap A and B in sigmap
Eddie Hung [Fri, 19 Jul 2019 20:23:07 +0000 (13:23 -0700)]
Wrap A and B in sigmap

5 years agoRemove "top" from message
Eddie Hung [Fri, 19 Jul 2019 20:20:45 +0000 (13:20 -0700)]
Remove "top" from message

5 years agoAlso optimise MSB of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:48 +0000 (13:11 -0700)]
Also optimise MSB of $sub

5 years agoAdd one more test with trimming Y_WIDTH of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:30 +0000 (13:11 -0700)]
Add one more test with trimming Y_WIDTH of $sub

5 years agoBe more explicit
Eddie Hung [Fri, 19 Jul 2019 19:53:18 +0000 (12:53 -0700)]
Be more explicit

5 years agowreduce for $sub
Eddie Hung [Fri, 19 Jul 2019 19:50:21 +0000 (12:50 -0700)]
wreduce for $sub

5 years agoAdd tests for sub too
Eddie Hung [Fri, 19 Jul 2019 19:50:11 +0000 (12:50 -0700)]
Add tests for sub too

5 years agoAdd test
Eddie Hung [Fri, 19 Jul 2019 19:43:02 +0000 (12:43 -0700)]
Add test

5 years agoSigSpec::extract to take negative lengths
Eddie Hung [Fri, 19 Jul 2019 19:34:04 +0000 (12:34 -0700)]
SigSpec::extract to take negative lengths

5 years agoice40: Fix test_dsp_model.sh
David Shah [Fri, 19 Jul 2019 16:33:57 +0000 (17:33 +0100)]
ice40: Fix test_dsp_model.sh

Signed-off-by: David Shah <dave@ds0.me>
5 years agoice40/cells_sim.v: Fix sign of J and K partial products
David Shah [Fri, 19 Jul 2019 16:33:41 +0000 (17:33 +0100)]
ice40/cells_sim.v: Fix sign of J and K partial products

Signed-off-by: David Shah <dave@ds0.me>
5 years agoice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
David Shah [Fri, 19 Jul 2019 16:13:34 +0000 (17:13 +0100)]
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd tests for all combinations of A and B signedness for comb mul
Eddie Hung [Fri, 19 Jul 2019 15:52:49 +0000 (08:52 -0700)]
Add tests for all combinations of A and B signedness for comb mul

5 years agoDon't copy ref if exists already
Eddie Hung [Fri, 19 Jul 2019 15:45:35 +0000 (08:45 -0700)]
Don't copy ref if exists already

5 years agoMerge pull request #1208 from ZirconiumX/intel_cleanups
David Shah [Thu, 18 Jul 2019 18:04:28 +0000 (19:04 +0100)]
Merge pull request #1208 from ZirconiumX/intel_cleanups

Assorted synth_intel cleanups from @bwidawsk

5 years agosynth_intel: Use stringf
Dan Ravensloft [Thu, 18 Jul 2019 17:41:34 +0000 (18:41 +0100)]
synth_intel: Use stringf