Tim Newsome [Mon, 9 May 2016 21:43:12 +0000 (14:43 -0700)]
Remove already-implemented TODO.
Tim Newsome [Mon, 9 May 2016 21:38:06 +0000 (14:38 -0700)]
Move debug rom link map to the right place.
Turns out this doesn't actually matter, but it's better to be correct.
Tim Newsome [Mon, 9 May 2016 20:48:20 +0000 (13:48 -0700)]
Remove obsolete TODO.
Tim Newsome [Mon, 9 May 2016 20:47:44 +0000 (13:47 -0700)]
Implement ebreak[mhsu].
Tim Newsome [Mon, 9 May 2016 20:08:41 +0000 (13:08 -0700)]
Remove dependency on include file in my homedir.
Tim Newsome [Mon, 9 May 2016 16:41:01 +0000 (09:41 -0700)]
Force gdb to not print entry values.
All of a sudden gdb decided to start printing them, which messed up the
breakpoint test. It would only print them in the test, not if I manually
ran the same commands. I'm sure it's my fault somehow, but this should
keep things consistent in the future.
Tim Newsome [Sat, 7 May 2016 18:15:59 +0000 (11:15 -0700)]
mprv test now breaks like it's supposed to.
Tim Newsome [Fri, 6 May 2016 23:54:33 +0000 (16:54 -0700)]
Deal with escapes that gdb sends in binary data.
Tim Newsome [Fri, 6 May 2016 19:14:22 +0000 (12:14 -0700)]
Make -H halt the core right out of reset.
Added a test, too.
Tim Newsome [Fri, 6 May 2016 00:40:02 +0000 (17:40 -0700)]
Halt when gdb user hits ^C.
Tim Newsome [Thu, 5 May 2016 21:53:56 +0000 (14:53 -0700)]
Make sure to fence.i after setting/clearing a swbp
This doesn't change anything since Debug ROM already executes a fence.i,
but it will be more correct if that is no longer necessary.
Tim Newsome [Thu, 5 May 2016 20:45:14 +0000 (13:45 -0700)]
Implemented register writes.
All existing tests pass!
Tim Newsome [Thu, 5 May 2016 18:21:07 +0000 (11:21 -0700)]
Fix reading CSRs.
Tim Newsome [Thu, 5 May 2016 01:51:26 +0000 (18:51 -0700)]
Single step appears to work.
Tim Newsome [Wed, 4 May 2016 20:14:46 +0000 (13:14 -0700)]
Software breakpoints sort of work.
Tim Newsome [Wed, 4 May 2016 16:45:56 +0000 (09:45 -0700)]
Use fence.i in Debug ROM.
This replaces a hack that just disabled all of the icache.
Tim Newsome [Wed, 4 May 2016 16:40:20 +0000 (09:40 -0700)]
Fix off-by-two in general read registers.
Now the exit test passes!
Tim Newsome [Wed, 4 May 2016 01:53:16 +0000 (18:53 -0700)]
Walk page tables to translate addresses.
Tim Newsome [Tue, 3 May 2016 20:46:57 +0000 (13:46 -0700)]
Turn operation into a queue,
in preparation for address translation.
Tim Newsome [Tue, 3 May 2016 19:24:25 +0000 (12:24 -0700)]
Remove unused code.
Add some debug printfs, which I'll be wanting for at least a little
while.
Tim Newsome [Tue, 3 May 2016 17:55:00 +0000 (10:55 -0700)]
Save/restore mstatus, too.
Also read DCSR, which will be useful to figure out why we halted.
Tim Newsome [Tue, 3 May 2016 17:54:08 +0000 (10:54 -0700)]
Ignore more files.
Tim Newsome [Tue, 3 May 2016 17:43:27 +0000 (10:43 -0700)]
Properly read s0/s1.
Tim Newsome [Tue, 3 May 2016 01:07:51 +0000 (18:07 -0700)]
Add dret.
Tim Newsome [Mon, 2 May 2016 22:04:03 +0000 (15:04 -0700)]
Implement memory writes.
Tim Newsome [Sun, 1 May 2016 20:18:03 +0000 (13:18 -0700)]
Implement single memory read access.
Prevent unaligned accesses in memory read.
Also change how exceptions in Debug Mode are signaled.
Tim Newsome [Sun, 1 May 2016 16:53:23 +0000 (09:53 -0700)]
Properly save/restore dpc, mcause, mbadaddr.
Also clear dcsr.cause when leaving Debug Mode so future traps go where
they should.
Tim Newsome [Sat, 30 Apr 2016 22:24:38 +0000 (15:24 -0700)]
Exceptions in Debug Mode, stay in Debug Mode.
Now things don't blow up when reading a non-existent CSR.
Tim Newsome [Sun, 1 May 2016 19:26:29 +0000 (12:26 -0700)]
Remove debug printfs.
Tim Newsome [Sun, 1 May 2016 19:05:48 +0000 (12:05 -0700)]
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Tim Newsome [Fri, 29 Apr 2016 20:38:59 +0000 (13:38 -0700)]
Read FP registers, and general CSRs*
*) Only works if you read CSRs that actually exist.
Tim Newsome [Fri, 29 Apr 2016 18:17:58 +0000 (11:17 -0700)]
Continue works well enough for DebugTest.test_exit
Tim Newsome [Thu, 28 Apr 2016 20:15:46 +0000 (13:15 -0700)]
Fix race using fence.
Tim Newsome [Wed, 27 Apr 2016 20:52:54 +0000 (13:52 -0700)]
Refactor how we track in-progress operations.
I think the functionality is unchanged.
Tim Newsome [Tue, 26 Apr 2016 21:32:08 +0000 (14:32 -0700)]
gdb can attach and read the PC:
(gdb) target remote localhost:1234
Remote debugging using localhost:1234
0x0000000000010178 in fib (n=0) at waste.c:1
1 unsigned int fib(unsigned int n) {
(gdb)
Tim Newsome [Tue, 26 Apr 2016 19:12:57 +0000 (12:12 -0700)]
processor_t unfriends gdbserver_t.
Tim Newsome [Tue, 26 Apr 2016 17:22:02 +0000 (10:22 -0700)]
Correctly read PC on halt.
Tim Newsome [Tue, 26 Apr 2016 15:29:17 +0000 (08:29 -0700)]
Fix store to clear debug interrupt.
Tim Newsome [Sun, 24 Apr 2016 15:54:19 +0000 (08:54 -0700)]
Add debug_module bus device.
This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
Tim Newsome [Sat, 23 Apr 2016 18:09:07 +0000 (11:09 -0700)]
ROM -> RAM -> ROM, waiting for debug int.
Tim Newsome [Sat, 23 Apr 2016 17:40:23 +0000 (10:40 -0700)]
Make sure to translate Debug RAM addresses also.
Tim Newsome [Sat, 23 Apr 2016 17:25:57 +0000 (10:25 -0700)]
Jump to the correct (temporary) Debug RAM address.
Tim Newsome [Sat, 23 Apr 2016 17:18:05 +0000 (10:18 -0700)]
Clean up how Debug ROM is included.
I'm not thrilled about including a static copy in so many cc files, and
making the compiler throw it out. But without really grokking the
Makefile this is the best it's going to be.
Tim Newsome [Sat, 23 Apr 2016 03:11:29 +0000 (20:11 -0700)]
Can jump to and execute Debug ROM.
Connect with gdb, and the core will jump to Debug ROM and start
executing it. Then it crashes when it jumps to 0x400 because Debug RAM
isn't implemented (and doesn't live there anyway, for now).
Tim Newsome [Fri, 22 Apr 2016 22:11:26 +0000 (15:11 -0700)]
Check in compiled debug ROM.
Not everybody will have a cross-compiled toolchain set up when they
build spike.
Tim Newsome [Fri, 22 Apr 2016 22:10:23 +0000 (15:10 -0700)]
When gdb connects, jump to Debug ROM and segfault.
Tim Newsome [Fri, 22 Apr 2016 22:08:35 +0000 (15:08 -0700)]
Add debug rom code.
Tim Newsome [Fri, 22 Apr 2016 19:09:59 +0000 (12:09 -0700)]
Gutting direct-access gdb.
Tim Newsome [Thu, 21 Apr 2016 22:53:46 +0000 (15:53 -0700)]
Add writing to DCSR, DPC, DSCRATCH.
Make those 3 CSRs writable.
Tim Newsome [Wed, 30 Mar 2016 17:43:45 +0000 (10:43 -0700)]
Actually run the ebreak test.
Tim Newsome [Thu, 24 Mar 2016 00:42:17 +0000 (17:42 -0700)]
Only halt on ebreak if a debugger is attached.
Tim Newsome [Wed, 23 Mar 2016 23:14:50 +0000 (16:14 -0700)]
Test ebreak without gdb.
Currently this test fails.
Tim Newsome [Sat, 19 Mar 2016 20:39:41 +0000 (13:39 -0700)]
Document attaching with gdb.
Tim Newsome [Sat, 19 Mar 2016 20:33:58 +0000 (13:33 -0700)]
Add --gdb-port
It's necessary to be able to run multiple spikes at once on the same
box.
Tim Newsome [Thu, 17 Mar 2016 19:51:58 +0000 (12:51 -0700)]
Do a better job checking CSR functionality.
Tim Newsome [Wed, 16 Mar 2016 18:07:50 +0000 (11:07 -0700)]
Rename gdbserver-smoke.py to gdbserver.py.
It's not really a smoketest anymore.
Tim Newsome [Wed, 16 Mar 2016 18:02:52 +0000 (11:02 -0700)]
Test 'info registers all' as well as 'info all-registers'
Tim Newsome [Tue, 15 Mar 2016 23:15:53 +0000 (16:15 -0700)]
Minor cleanup.
Tim Newsome [Tue, 15 Mar 2016 20:50:17 +0000 (13:50 -0700)]
Update regnum handling to match gdb CSR changes.
Tim Newsome [Mon, 14 Mar 2016 20:39:47 +0000 (13:39 -0700)]
Forgot to add this source.
Tim Newsome [Mon, 14 Mar 2016 20:29:53 +0000 (13:29 -0700)]
Treat warnings as errors.
The code compiles cleanly right now. Let's keep it that way.
Tim Newsome [Mon, 14 Mar 2016 18:54:29 +0000 (11:54 -0700)]
Implement register writes.
Tim Newsome [Sun, 13 Mar 2016 23:23:59 +0000 (16:23 -0700)]
Properly clean up spike.
Tim Newsome [Sun, 13 Mar 2016 22:39:08 +0000 (15:39 -0700)]
Implement reading of CSRs.
Tim Newsome [Sun, 13 Mar 2016 20:13:15 +0000 (13:13 -0700)]
Add some tests that pass and test something.
Tim Newsome [Sun, 13 Mar 2016 01:50:32 +0000 (17:50 -0800)]
Flush icache when using swbps and report to gdb.
Tim Newsome [Fri, 11 Mar 2016 02:14:31 +0000 (18:14 -0800)]
Add very basic 'make check'.
The existing stuff all assumes you're writing your tests in C++.
Tim Newsome [Fri, 11 Mar 2016 01:57:23 +0000 (17:57 -0800)]
Make 'make check' not hang forever.
Tim Newsome [Thu, 10 Mar 2016 20:29:29 +0000 (12:29 -0800)]
Software breakpoints seem to work.
Tim Newsome [Thu, 10 Mar 2016 18:04:04 +0000 (10:04 -0800)]
Rewrite GPL'd code from OpenOCD.
Tim Newsome [Thu, 10 Mar 2016 02:48:20 +0000 (18:48 -0800)]
Looks like single step works.
Tim Newsome [Thu, 10 Mar 2016 01:16:26 +0000 (17:16 -0800)]
Add -H to start halted.
Tim Newsome [Wed, 9 Mar 2016 18:31:51 +0000 (10:31 -0800)]
Implement binary memory write.
Also set the simulation running again when gdb disconnects.
Tim Newsome [Wed, 9 Mar 2016 05:56:31 +0000 (21:56 -0800)]
Now you can halt/continue from gdb.
Tim Newsome [Wed, 9 Mar 2016 05:13:55 +0000 (21:13 -0800)]
Register read looks sane now.
Tim Newsome [Mon, 7 Mar 2016 23:44:20 +0000 (15:44 -0800)]
gdb can now read spike memory.
The endianness is wrong, but I think it might be that gdb doesn't have
it right. Need to investigate what architecture gdb thinks it's
debugging.
Tim Newsome [Mon, 7 Mar 2016 04:59:26 +0000 (20:59 -0800)]
Hack to the point where gdb reads a register.
Tim Newsome [Sun, 6 Mar 2016 01:35:06 +0000 (17:35 -0800)]
Listen on a socket for gdb to connect to.
So far it just listens, and gdb times out because it's not getting any
messages back.
Receive packets and verify their checksum.
Andrew Waterman [Sun, 22 May 2016 09:35:33 +0000 (02:35 -0700)]
Allow delegation of device interrupts
Garret Kelly [Sat, 21 May 2016 22:41:28 +0000 (18:41 -0400)]
htif: catch proper store exception (#44)
The sim's debug_mmu will generate a trap_load_access_fault if the load
fails, not a trap_store_access_fault. This doesn't materially affect
exection, but results in a nicer log message.
Andy Wright [Sat, 21 May 2016 20:39:21 +0000 (16:39 -0400)]
Some bugfixes for CSR reading and setting FS for fflags updates (#43)
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0
* Dirty fp state when setting new fp exceptions
* Set FS to dirty for all non-zero fflags writes.
Tim Newsome [Thu, 19 May 2016 23:34:21 +0000 (16:34 -0700)]
Merge pull request #42 from csail-csg/master
Removed devicetree.h from riscv.mk.in since it no longer exists
acw1251 [Thu, 19 May 2016 20:17:57 +0000 (16:17 -0400)]
Removed devicetree.h from riscv.mk.in since it no longer exists
acw1251 [Mon, 16 May 2016 19:39:37 +0000 (15:39 -0400)]
Added missing header files to riscv.mk.in
Merges #40
Andrew Waterman [Mon, 2 May 2016 23:28:51 +0000 (16:28 -0700)]
Add back IPI support
Andrew Waterman [Mon, 2 May 2016 22:11:25 +0000 (15:11 -0700)]
Remove MIPI; mip.MSIP bit is read-only
Andrew Waterman [Mon, 2 May 2016 21:13:52 +0000 (14:13 -0700)]
Remove tohost/fromhost registers
Andrew Waterman [Sun, 1 May 2016 03:43:00 +0000 (20:43 -0700)]
Initialize mtvec to DEFAULT_MTVEC
Andrew Waterman [Sun, 1 May 2016 00:48:07 +0000 (17:48 -0700)]
Remove SCRs; add padding after config string
Andrew Waterman [Fri, 29 Apr 2016 20:48:56 +0000 (13:48 -0700)]
Move much closer to new platform-M memory map
Reset vector is at 0x1000; below that is reserved for debug
Memory is at 0x80000000
Andrew Waterman [Thu, 28 Apr 2016 22:17:28 +0000 (15:17 -0700)]
Add --dump-config-string flag
Andrew Waterman [Thu, 28 Apr 2016 22:01:09 +0000 (15:01 -0700)]
Remove MTIME[CMP]; add RTC device
Andrew Waterman [Wed, 20 Apr 2016 00:31:54 +0000 (17:31 -0700)]
Split ERET into URET, SRET, HRET, MRET
Andrew Waterman [Wed, 6 Apr 2016 17:20:24 +0000 (10:20 -0700)]
Remove non-standard uarch CSRs
Andrew Waterman [Sun, 3 Apr 2016 00:32:23 +0000 (17:32 -0700)]
Allow configuration of default ISA with --with-isa
Andrew Waterman [Thu, 17 Mar 2016 06:43:33 +0000 (23:43 -0700)]
Update definition of base field in misa register
Andrew Waterman [Fri, 4 Mar 2016 01:01:48 +0000 (17:01 -0800)]
Fix up interrupt delegation
Andrew Waterman [Tue, 1 Mar 2016 23:03:00 +0000 (15:03 -0800)]
Add counter-enable registers
Andrew Waterman [Tue, 1 Mar 2016 23:01:29 +0000 (15:01 -0800)]
Use RV config string rather than FDT
Andrew Waterman [Mon, 29 Feb 2016 07:51:53 +0000 (23:51 -0800)]
WIP on priv spec v1.9