nmigen.git
2 years agovendor.xilinx_*: deprecate legacy Xilinx platform aliases.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
vendor.xilinx_*: deprecate legacy Xilinx platform aliases.

2 years agoRun tests on Python 3.10.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
Run tests on Python 3.10.

2 years agoSimplify CI workflow.
whitequark [Fri, 8 Oct 2021 17:48:00 +0000 (17:48 +0000)]
Simplify CI workflow.

2 years agovendor.intel: add Mistral toolchain support.
Olivier Galibert [Thu, 14 Oct 2021 16:02:22 +0000 (18:02 +0200)]
vendor.intel: add Mistral toolchain support.

2 years agohdl.ast: improve interaction of ValueCastable with custom __getattr__.
whitequark [Sun, 3 Oct 2021 20:28:07 +0000 (20:28 +0000)]
hdl.ast: improve interaction of ValueCastable with custom __getattr__.

Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.

2 years agomention benefits of nmigen over MyHDL, ability to use full python OO
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 16:11:29 +0000 (16:11 +0000)]
mention benefits of nmigen over MyHDL, ability to use full python OO

2 years agomention MyHDL for compare/contrast to nmigen
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 16:09:35 +0000 (16:09 +0000)]
mention MyHDL for compare/contrast to nmigen

2 years agorestore nmigen logos, update wording on git format-patch
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 16:06:22 +0000 (16:06 +0000)]
restore nmigen logos, update wording on git format-patch

2 years agomore README whitespace
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:59:30 +0000 (15:59 +0000)]
more README whitespace

2 years agomention that git format-patch for contributions is perfectly fine
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:58:54 +0000 (15:58 +0000)]
mention that git format-patch for contributions is perfectly fine

2 years agowhitespace update on README.md
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:57:16 +0000 (15:57 +0000)]
whitespace update on README.md

2 years agoMerge branch 'update_to_2021oct08' into 'master'
luke leighton [Fri, 31 Dec 2021 15:54:49 +0000 (15:54 +0000)]
Merge branch 'update_to_2021oct08' into 'master'

sim._pyrtl: optimize uses of reflexive operators.

See merge request nmigen/nmigen!1

2 years agoMerge branch 'master' into 'update_to_2021oct08'
luke leighton [Fri, 31 Dec 2021 15:54:32 +0000 (15:54 +0000)]
Merge branch 'master' into 'update_to_2021oct08'

# Conflicts:
#   LICENSE.txt
#   README.md
#   nmigen/test/utils.py
#   nmigen/vendor/xilinx_7series.py
#   setup.py

2 years agocorrect IRC link
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:49:06 +0000 (15:49 +0000)]
correct IRC link

2 years agoreplace github with gitlab
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:45:23 +0000 (15:45 +0000)]
replace github with gitlab

2 years agoadd reference to nmigen Trademark
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:40:50 +0000 (15:40 +0000)]
add reference to nmigen Trademark

2 years agohdl.ast: simplify Mux implementation.
whitequark [Sat, 2 Oct 2021 14:18:02 +0000 (14:18 +0000)]
hdl.ast: simplify Mux implementation.

2 years agohdl.ast: add tests for casting bare integers in {Cat,Repl}.
whitequark [Sat, 2 Oct 2021 13:18:11 +0000 (13:18 +0000)]
hdl.ast: add tests for casting bare integers in {Cat,Repl}.

2 years agohdl.ast: remove quadratic time complexity in Statement.cast().
Anton Blanchard [Mon, 27 Sep 2021 01:00:56 +0000 (11:00 +1000)]
hdl.ast: remove quadratic time complexity in Statement.cast().

Using `sum(lst, [])` to flatten a list of lists has quadratic time
complexity. Use `chain.from_iterable()` instead. While not strictly
necessary to improve performance, convert to `map()`.

A test case writing out verilog for a 512k entry FIFO is 120x faster
with this applied.

2 years agovendor.xilinx: avoid using `/` for hierarchy in ISE constraint files.
H-S-S-11 [Sat, 25 Sep 2021 10:41:23 +0000 (11:41 +0100)]
vendor.xilinx: avoid using `/` for hierarchy in ISE constraint files.

2 years agoUnify Xilinx platforms into a single class, support more devices
Marcelina Kościelnicka [Wed, 16 Dec 2020 15:35:57 +0000 (16:35 +0100)]
Unify Xilinx platforms into a single class, support more devices

This merges existing code, and also adds support for:

- Virtex, Virtex E (also known as Spartan 2, Spartan 2E)
- Virtex 2, Virtex 2 Pro
- Spartan 3, Spartan 3E (in addition to existing Spartan 3A, Spartan 3A
  DSP support)
- Virtex 4
- Virtex 5
- Virtex 6
- ISE synthesis for Series 7

Fixes #552.

2 years ago_toolchain: Properly set compiler/linker executables on Gentoo
Adam Jeliński [Tue, 21 Sep 2021 08:33:26 +0000 (10:33 +0200)]
_toolchain: Properly set compiler/linker executables on Gentoo

The `test_toolchain_cxx.py` tests on Gentoo definitely use compiler and
linker set with `_so_cxx`-suffixed executables. Tests use a proper
executable instead of `c++` after this change.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
2 years agovendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical
Robin Ole Heinemann [Mon, 16 Aug 2021 21:31:57 +0000 (23:31 +0200)]
vendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical

Signed-off-by: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>
2 years ago_toolchain: substitute '+' with 'X' in tool_env_var().
Jean-François Nguyen [Fri, 16 Jul 2021 17:16:56 +0000 (19:16 +0200)]
_toolchain: substitute '+' with 'X' in tool_env_var().

2 years agoREADME: update IRC channel.
whitequark [Thu, 20 May 2021 03:07:51 +0000 (03:07 +0000)]
README: update IRC channel.

2 years agorpc: fix parsing of negative signed parameters
Robin Ole Heinemann [Tue, 18 May 2021 18:43:16 +0000 (20:43 +0200)]
rpc: fix parsing of negative signed parameters

2 years agotest.test_hdl_ast.OperatorTestCase: remove duplicate test_bool
Robin Ole Heinemann [Tue, 18 May 2021 19:18:51 +0000 (21:18 +0200)]
test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool

2 years agotests: rename tests with duplicate names
Robin Ole Heinemann [Tue, 18 May 2021 19:18:14 +0000 (21:18 +0200)]
tests: rename tests with duplicate names

2 years agotests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix
Robin Ole Heinemann [Tue, 18 May 2021 19:15:02 +0000 (21:15 +0200)]
tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix

2 years ago*: remove unused variables
Robin Ole Heinemann [Tue, 18 May 2021 19:10:47 +0000 (21:10 +0200)]
*: remove unused variables

2 years ago*: remove unused imports
Robin Ole Heinemann [Tue, 18 May 2021 18:39:57 +0000 (20:39 +0200)]
*: remove unused imports

2 years agotests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements
Thomas Watson [Tue, 11 May 2021 02:02:29 +0000 (21:02 -0500)]
tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements

2 years agohdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements
Thomas Watson [Tue, 11 May 2021 01:59:34 +0000 (20:59 -0500)]
hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements

2 years agovendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts.
Adam Greig [Mon, 12 Apr 2021 09:48:20 +0000 (10:48 +0100)]
vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts.

Fixes #604.

2 years agoCI: fix sri-csl/formal-methods PPA series.
whitequark [Thu, 18 Mar 2021 23:56:52 +0000 (23:56 +0000)]
CI: fix sri-csl/formal-methods PPA series.

GHA's Ubuntu has been upgraded to Focal.

2 years agohdl.ast: handle int subclasses as slice start/stop values.
whitequark [Thu, 18 Mar 2021 23:52:23 +0000 (23:52 +0000)]
hdl.ast: handle int subclasses as slice start/stop values.

Fixes #601.

2 years agocompat.genlib.roundrobin: fix missing imports
dx-mon [Thu, 4 Feb 2021 03:10:44 +0000 (03:10 +0000)]
compat.genlib.roundrobin: fix missing imports

2 years agovendor.xilinx_7series: fix tool names for symbiflow.
nickoe [Sun, 31 Jan 2021 18:08:44 +0000 (19:08 +0100)]
vendor.xilinx_7series: fix tool names for symbiflow.

Prefix "tools" with symbiflow_ as is done for the QuickLogic Symbiflow
toolchain. Installing symbiflow gives me the tools with the preifx, so I
guess this is the correct way to move forward.

2 years agovendor.lattice_ecp5: correctly generate OE signaling when xdr=0
Katherine Temkin [Mon, 25 Jan 2021 15:41:45 +0000 (08:41 -0700)]
vendor.lattice_ecp5: correctly generate OE signaling when xdr=0

This fixes a logic bug introduced in
6ce2b21e196a0f93b82748ed046098331d20b3bf.

2 years agovendor.lattice_ecp5: replicate OE signal for each output bit.
Adam Greig [Sat, 23 Jan 2021 18:06:52 +0000 (18:06 +0000)]
vendor.lattice_ecp5: replicate OE signal for each output bit.

nextpnr can only pack OE FFs into IOLOGIC when there's one OFS1P3DX per
output, rather than one shared instance.

2 years agodocs: Update up_counter to avoid deprecation warning
Joel Stanley [Fri, 15 Jan 2021 02:58:21 +0000 (13:28 +1030)]
docs: Update up_counter to avoid deprecation warning

nmigen/docs/_code/up_counter.py:44: DeprecationWarning: instead of nmigen.back.pysim.*, use nmigen.sim.*
  from nmigen.back.pysim import Simulator

2 years agovendor.lattice_ecp5: remove outdated comment in ECP5 platform.
Adam Greig [Thu, 14 Jan 2021 11:34:03 +0000 (11:34 +0000)]
vendor.lattice_ecp5: remove outdated comment in ECP5 platform.

Starting with nextpnr c6401413a, nextpnr does pack *FS1P3DX
into IOLOGIC cells.

2 years agolib.fifo.AsyncFIFOBuffered: fix output register accounting
Robin Ole Heinemann [Sat, 2 Jan 2021 23:17:48 +0000 (00:17 +0100)]
lib.fifo.AsyncFIFOBuffered: fix output register accounting

2 years agolib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency
Robin Ole Heinemann [Sat, 2 Jan 2021 23:14:26 +0000 (00:14 +0100)]
lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency

2 years agolib.fifo: use proper clock domains in AsyncFIFO tests
Robin Ole Heinemann [Sat, 2 Jan 2021 23:13:46 +0000 (00:13 +0100)]
lib.fifo: use proper clock domains in AsyncFIFO tests

2 years agolib.fifo.AsyncFIFOBuffered: use FFSynchronizer instead of AsyncFFsynchronizer
Robin Ole Heinemann [Sat, 2 Jan 2021 23:12:31 +0000 (00:12 +0100)]
lib.fifo.AsyncFIFOBuffered: use FFSynchronizer instead of AsyncFFsynchronizer

AsyncFFsynchronizer only synchronizes one edge

2 years agoRevert "vendor.xilinx_7series: byte swap generated bitstream"
whitequark [Sat, 12 Dec 2020 22:08:57 +0000 (22:08 +0000)]
Revert "vendor.xilinx_7series: byte swap generated bitstream"

This reverts commit 14a5c42a8bd425a4882ba566b26e11bd6d1e1721.

2 years agohdl.ast: formatting. NFC.
whitequark [Sat, 12 Dec 2020 14:11:40 +0000 (14:11 +0000)]
hdl.ast: formatting. NFC.

2 years agohdl.ast: normalize case values to two's complement, not signed binary.
whitequark [Sat, 12 Dec 2020 12:42:12 +0000 (12:42 +0000)]
hdl.ast: normalize case values to two's complement, not signed binary.

This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.

2 years agoback.rtlil: give private items an appropriate name. NFCI.
whitequark [Sat, 12 Dec 2020 12:18:59 +0000 (12:18 +0000)]
back.rtlil: give private items an appropriate name. NFCI.

2 years agobuild.plat: make `verbose` work like all other overrides.
whitequark [Tue, 24 Nov 2020 23:07:09 +0000 (23:07 +0000)]
build.plat: make `verbose` work like all other overrides.

Fixes #497.

2 years agovendor.intel: implement `add_settings` (QSF) and `add_constraints` (SDC) overrides.
whitequark [Tue, 24 Nov 2020 20:35:58 +0000 (20:35 +0000)]
vendor.intel: implement `add_settings` (QSF) and `add_constraints` (SDC) overrides.

2 years agovendor.xilinx_spartan_3_6: fix typo.
whitequark [Sun, 22 Nov 2020 00:16:02 +0000 (00:16 +0000)]
vendor.xilinx_spartan_3_6: fix typo.

This was introduced in commit 2f8669ca.

Fixes #549.

2 years agohdl.ast: remove dead code. NFC.
whitequark [Sat, 21 Nov 2020 17:29:55 +0000 (17:29 +0000)]
hdl.ast: remove dead code. NFC.

See #548.

2 years agonmigen.hdl.rec: restore Record.shape().
awygle [Tue, 17 Nov 2020 19:36:58 +0000 (11:36 -0800)]
nmigen.hdl.rec: restore Record.shape().

This method was lost in commit abbebf8e.

2 years agosim._pyrtl: mask Mux selection operand.
Marcelina Kościelnicka [Sat, 14 Nov 2020 15:22:34 +0000 (16:22 +0100)]
sim._pyrtl: mask Mux selection operand.

Otherwise it behaves funny when it's eg. the result of operator ~.

2 years agovendor.quicklogic: enable SoC clock configuration
Jan Kowalewski [Fri, 13 Nov 2020 12:58:11 +0000 (13:58 +0100)]
vendor.quicklogic: enable SoC clock configuration

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2 years agovendor.quicklogic: write OpenOCD scripts as part of build process.
whitequark [Fri, 13 Nov 2020 05:44:16 +0000 (05:44 +0000)]
vendor.quicklogic: write OpenOCD scripts as part of build process.

The OpenOCD scripts for EOS-S3 are roughly equivalent to SVF files
for a more traditional FPGA, which we also produce, for some common
"default" configuration, as a part of the build process.

2 years agobuild.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.
whitequark [Tue, 10 Nov 2020 05:30:21 +0000 (05:30 +0000)]
build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.

This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.

2 years agohdl.rec: proxy operators correctly.
awygle [Mon, 9 Nov 2020 20:20:25 +0000 (12:20 -0800)]
hdl.rec: proxy operators correctly.

Commit abbebf8e used __getattr__ to proxy Value methods called on
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.

2 years agovendor.intel: add support for Cyclone V internal oscillator
Konrad Beckmann [Fri, 6 Nov 2020 11:35:18 +0000 (12:35 +0100)]
vendor.intel: add support for Cyclone V internal oscillator

When using the default clock "cyclonev_oscillator" on Cyclone V devices,
the internal oscillator will be used.

2 years agohdl.ast: deprecate UserValue in favor of ValueCastable.
whitequark [Fri, 6 Nov 2020 02:21:53 +0000 (02:21 +0000)]
hdl.ast: deprecate UserValue in favor of ValueCastable.

Closes #527.

2 years agosim.pysim: avoid redundant VCD updates.
whitequark [Fri, 6 Nov 2020 02:05:35 +0000 (02:05 +0000)]
sim.pysim: avoid redundant VCD updates.

This commit properly addresses a bug introduced in 2efeb05c and then
temporarily fixed in 58f1d4bc.

Fixes #429.

2 years agoexamples: clean up oudated code.
whitequark [Fri, 6 Nov 2020 01:52:00 +0000 (01:52 +0000)]
examples: clean up oudated code.

2 years agoFix commit 8313d6e7.
whitequark [Fri, 6 Nov 2020 01:54:25 +0000 (01:54 +0000)]
Fix commit 8313d6e7.

2 years agocli: update deprecated import.
whitequark [Fri, 6 Nov 2020 01:39:04 +0000 (01:39 +0000)]
cli: update deprecated import.

2 years agoCI: add CPython 3.9 to test matrix.
whitequark [Fri, 6 Nov 2020 01:41:35 +0000 (01:41 +0000)]
CI: add CPython 3.9 to test matrix.

2 years agoCI: run testsuite with -Werror.
whitequark [Fri, 6 Nov 2020 01:38:03 +0000 (01:38 +0000)]
CI: run testsuite with -Werror.

2 years agovendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.
whitequark [Fri, 6 Nov 2020 01:31:14 +0000 (01:31 +0000)]
vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.

These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:

  Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.

2 years agohdl.rec: migrate Record from UserValue to ValueCastable.
awygle [Fri, 6 Nov 2020 01:10:39 +0000 (17:10 -0800)]
hdl.rec: migrate Record from UserValue to ValueCastable.

Closes #528.

2 years agohdl.ast: implement ValueCastable.
awygle [Fri, 6 Nov 2020 00:20:54 +0000 (16:20 -0800)]
hdl.ast: implement ValueCastable.

Closes RFC issue #355.

2 years agovendor.quicklogic: part→package
whitequark [Thu, 5 Nov 2020 07:36:13 +0000 (07:36 +0000)]
vendor.quicklogic: part→package

2 years agovendor.xilinx_7series: byte swap generated bitstream
Norbert Braun [Mon, 2 Nov 2020 21:00:17 +0000 (22:00 +0100)]
vendor.xilinx_7series: byte swap generated bitstream

The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that
are byte swapped with respect to what the Vivado command
`write_bitstream -bin_file` produces. Thus, use the `write_cfgmem` command with
appropriate options to generate the bitstream (.bin file).

Fixes #519.

2 years agolib.fifo: fix {r,w}_level in AsyncFIFOBuffered
Jaro Habiger [Tue, 18 Aug 2020 11:11:30 +0000 (13:11 +0200)]
lib.fifo: fix {r,w}_level in AsyncFIFOBuffered

2 years agolib.fifo: fix level on fifo full
Jaro Habiger [Tue, 3 Nov 2020 09:10:07 +0000 (10:10 +0100)]
lib.fifo: fix level on fifo full

2 years agovendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC instance.
David Lattimore [Mon, 2 Nov 2020 06:19:47 +0000 (17:19 +1100)]
vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC instance.

Fixes #520.

2 years agovendor.quicklogic: utilize internal SoC clock in EOS-S3
Jan Kowalewski [Wed, 21 Oct 2020 12:24:41 +0000 (14:24 +0200)]
vendor.quicklogic: utilize internal SoC clock in EOS-S3

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2 years agovendor.quicklogic: fix toolchain nomenclature
Jan Kowalewski [Tue, 20 Oct 2020 10:46:58 +0000 (12:46 +0200)]
vendor.quicklogic: fix toolchain nomenclature

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2 years agolib.fifo.AsyncFFSynchronizer: check input and output signal width
Robin Ole Heinemann [Tue, 27 Oct 2020 23:41:01 +0000 (00:41 +0100)]
lib.fifo.AsyncFFSynchronizer: check input and output signal width

2 years agobuild.dsl: clean up inversion logic.
whitequark [Mon, 26 Oct 2020 19:50:21 +0000 (19:50 +0000)]
build.dsl: clean up inversion logic.

  * Add invert= argument to DiffPairs() constructor, like in Pins().
  * Make PinsN() and DiffPairsN() pass invert= to the corresponding
    construtor instead of mutating.

2 years agoback.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.
whitequark [Sun, 25 Oct 2020 01:59:46 +0000 (01:59 +0000)]
back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.

To track upstream changes.

2 years agoCI: disable codecov project status.
whitequark [Sun, 25 Oct 2020 00:13:39 +0000 (00:13 +0000)]
CI: disable codecov project status.

Every PR should be covered by tests, and codecov patch statuses are
extremely useful. However, codecov project statuses mostly create
noise because project-wide coverage in nMigen is currently primarily
informational.

2 years agolib.fifo.AsyncFIFO: fix incorrect latency of r_level.
anuejn [Sat, 24 Oct 2020 14:58:23 +0000 (16:58 +0200)]
lib.fifo.AsyncFIFO: fix incorrect latency of r_level.

Co-authored-by: Andrew Wygle <awygle@gmail.com>
2 years agotests: make spec directory name unique per test method.
anuejn [Thu, 22 Oct 2020 21:38:44 +0000 (23:38 +0200)]
tests: make spec directory name unique per test method.

2 years agosim._pyrtl: sign extend RHS of assignment.
whitequark [Thu, 22 Oct 2020 16:08:38 +0000 (16:08 +0000)]
sim._pyrtl: sign extend RHS of assignment.

Fixes #502.

2 years agohdl.dsl: error on Elif immediately nested in an If.
whitequark [Thu, 22 Oct 2020 13:23:06 +0000 (13:23 +0000)]
hdl.dsl: error on Elif immediately nested in an If.

I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:

    with m.If(...):
        with m.Elif(...):
            ...

Fixes #500.

2 years agovendor.quicklogic: fix syntax
Jan Kowalewski [Mon, 19 Oct 2020 10:09:50 +0000 (12:09 +0200)]
vendor.quicklogic: fix syntax

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2 years agosetup.py: Exclude "tests" package
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:14:37 +0000 (15:14 +0000)]
setup.py: Exclude "tests" package

67b957d moved the tests from nmigen/test/ to tests/, and removed the
exclude= parameter from find_packages() in setup.py. However, even if
the new location is not inside the module tree, it is still found by
find_packages(), resulting in a stray "tests" module on the system.

2 years agohdl.ir: Update error message for Instance arguments
Xiretza [Fri, 16 Oct 2020 16:36:56 +0000 (18:36 +0200)]
hdl.ir: Update error message for Instance arguments

48d4ee4 added the option to specify attributes using Instance arguments,
but the error message wasn't updated accordingly.

2 years agoREADME: Quicklogic EOS S3 is now supported.
whitequark [Thu, 15 Oct 2020 18:10:39 +0000 (18:10 +0000)]
README: Quicklogic EOS S3 is now supported.

2 years agoCI: fix code coverage collection.
whitequark [Thu, 15 Oct 2020 18:09:04 +0000 (18:09 +0000)]
CI: fix code coverage collection.

This has been broken since commit d71e19e2 (2020-07-22).

2 years agovendor.quicklogic: new platform.
Jan Kowalewski [Thu, 15 Oct 2020 18:02:25 +0000 (20:02 +0200)]
vendor.quicklogic: new platform.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
Co-authored-by: Kamil Rakoczy <krakoczy@antmicro.com>
2 years agotests: keep comments up to date. NFC.
whitequark [Thu, 15 Oct 2020 17:02:50 +0000 (17:02 +0000)]
tests: keep comments up to date. NFC.

2 years agobuild.plat: avoid type confusion in _check_feature.
whitequark [Thu, 15 Oct 2020 08:54:48 +0000 (08:54 +0000)]
build.plat: avoid type confusion in _check_feature.

Before this commit, `_check_feature(valid_xdrs=0)` would mean that
XDR buffers are not supported. Only `_check_feature(valid_xdrs=())`
was intended to be an indicator of that.

2 years agohdl.mem: document ReadPort and WritePort.
Jean-François Nguyen [Tue, 15 Sep 2020 00:20:35 +0000 (02:20 +0200)]
hdl.mem: document ReadPort and WritePort.

Fixes #496.

2 years agovendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.
William D. Jones [Sat, 29 Aug 2020 19:34:57 +0000 (15:34 -0400)]
vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.

2 years agoback.verilog: use `proc -nomux` if it is available.
whitequark [Thu, 27 Aug 2020 13:03:15 +0000 (13:03 +0000)]
back.verilog: use `proc -nomux` if it is available.

Yosys offers no stability guarantees for individual `proc_*` passes,
though so far it worked out fine. This commit changes the Verilog
backend to use `proc -nomux` instead, which is guaranteed to have
backwards-compatible behavior.

Fixes #479.

2 years agosim: split into base, core, and engines.
whitequark [Thu, 27 Aug 2020 10:17:02 +0000 (10:17 +0000)]
sim: split into base, core, and engines.

Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.

2 years agosim.pysim: in write_vcd(), close files if an exception is raised.
whitequark [Thu, 27 Aug 2020 08:33:48 +0000 (08:33 +0000)]
sim.pysim: in write_vcd(), close files if an exception is raised.

This also avoids leaving the waveform writer list in an inconsistent
state after an exception.

2 years agosim._pyclock: new type of process.
whitequark [Thu, 27 Aug 2020 07:54:27 +0000 (07:54 +0000)]
sim._pyclock: new type of process.

The overhead of coroutine processes is fairly high. A clock driver
implemented through a coroutine process is mostly overhead. This was
partially addressed in commit 2398b792 by microoptimizing yielding.

This commit eliminates the coroutine process overhead completely by
introducing dedicated clock processes. It also simplifies the logic
to a simple toggle.

This change improves runtime by about 12% on Minerva SRAM SoC.