David Shah [Tue, 25 Feb 2020 14:14:45 +0000 (14:14 +0000)]
deminout: Don't demote inouts with unused bits
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Sat, 22 Feb 2020 19:29:22 +0000 (11:29 -0800)]
Merge pull request #1715 from boqwxp/master
Closes #1714. Fix make failure when NDEBUG=1.
Alberto Gonzalez [Sat, 22 Feb 2020 06:29:11 +0000 (06:29 +0000)]
Closes #1714. Fix make failure when NDEBUG=1.
Eddie Hung [Fri, 21 Feb 2020 17:15:17 +0000 (09:15 -0800)]
Merge pull request #1703 from YosysHQ/eddie/specify_improve
Improve specify parser
Claire Wolf [Thu, 20 Feb 2020 17:17:25 +0000 (18:17 +0100)]
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
Enum support
Eddie Hung [Wed, 19 Feb 2020 19:09:37 +0000 (11:09 -0800)]
verilog: add support for more delays than just rise/fall
Eddie Hung [Wed, 19 Feb 2020 18:45:10 +0000 (10:45 -0800)]
clean: ignore specify-s inside cells when determining whether to keep
Jeff Wang [Mon, 17 Feb 2020 09:40:18 +0000 (04:40 -0500)]
update documentation for enums and typedefs
Jeff Wang [Mon, 17 Feb 2020 09:40:02 +0000 (04:40 -0500)]
remove unnecessary blank line
Jeff Wang [Mon, 3 Feb 2020 06:12:24 +0000 (01:12 -0500)]
add attributes for enumerated values in ilang
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
Jeff Wang [Mon, 3 Feb 2020 06:08:16 +0000 (01:08 -0500)]
separate out enum_item/param implementation when they should be different
Marcin Kościelnicki [Sat, 15 Feb 2020 13:32:35 +0000 (14:32 +0100)]
tests/aiger: Add missing .gitignore
Tim 'mithro' Ansell [Sat, 7 Jul 2018 00:04:16 +0000 (17:04 -0700)]
show: Add -nobg argument.
Makes yosys wait for the viewer command to finish before continuing.
Miodrag Milanović [Sat, 15 Feb 2020 10:15:35 +0000 (11:15 +0100)]
Merge pull request #1706 from YosysHQ/mmicko/remove_executable_flag
Remove executable flag from files
Miodrag Milanovic [Sat, 15 Feb 2020 09:36:44 +0000 (10:36 +0100)]
Remove executable flag from files
Miodrag Milanović [Sat, 15 Feb 2020 08:44:32 +0000 (09:44 +0100)]
Add comment for macOS dependency install
Eddie Hung [Sat, 15 Feb 2020 00:08:04 +0000 (16:08 -0800)]
Revert "abc9: fix abc9_arrival for flops"
This reverts commit
f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.
Miodrag Milanović [Fri, 14 Feb 2020 11:06:37 +0000 (12:06 +0100)]
Merge pull request #1701 from nakengelhardt/rpc-test
make rpc frontend unix socket test less fragile
Eddie Hung [Fri, 14 Feb 2020 01:58:43 +0000 (17:58 -0800)]
verilog: ignore ranges too without -specify
Eddie Hung [Fri, 14 Feb 2020 01:32:54 +0000 (17:32 -0800)]
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
Eddie Hung [Fri, 14 Feb 2020 01:32:14 +0000 (17:32 -0800)]
Merge pull request #1699 from YosysHQ/eddie/fix_iopad_init
iopadmap: move \init attributes from outpad output to its input
Eddie Hung [Thu, 13 Feb 2020 23:14:58 +0000 (15:14 -0800)]
Fine tune #1699 tests
Eddie Hung [Thu, 13 Feb 2020 22:57:06 +0000 (14:57 -0800)]
iopadmap: fixes as suggested by @mwkmwkmwk
Eddie Hung [Thu, 13 Feb 2020 21:27:15 +0000 (13:27 -0800)]
verilog: improve specify support when not in -specify mode
Eddie Hung [Thu, 13 Feb 2020 21:06:13 +0000 (13:06 -0800)]
verilog: ignore '&&&' when not in -specify mode
Eddie Hung [Thu, 13 Feb 2020 16:59:08 +0000 (08:59 -0800)]
specify: system timing checks to accept min:typ:max triple
Eddie Hung [Wed, 12 Feb 2020 20:16:01 +0000 (12:16 -0800)]
verilog: fix $specify3 check
Eddie Hung [Thu, 13 Feb 2020 20:36:50 +0000 (12:36 -0800)]
write_xaiger: default value for abc9_init
Eddie Hung [Thu, 13 Feb 2020 00:04:19 +0000 (16:04 -0800)]
abc9: fix abc9_arrival for flops
Eddie Hung [Wed, 12 Feb 2020 23:33:02 +0000 (15:33 -0800)]
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
Eddie Hung [Thu, 13 Feb 2020 20:05:14 +0000 (12:05 -0800)]
iopadmap: move \init attributes from outpad output to its input
N. Engelhardt [Thu, 13 Feb 2020 19:52:22 +0000 (20:52 +0100)]
make rpc frontend unix socket test less fragile
Claire Wolf [Thu, 13 Feb 2020 17:30:22 +0000 (18:30 +0100)]
Merge pull request #1694 from rqou/json_compat_fix
json: Change compat mode to directly emit ints <= 32 bits
N. Engelhardt [Thu, 13 Feb 2020 11:01:27 +0000 (12:01 +0100)]
Merge pull request #1679 from thasti/delay-parsing
Fix crash on wire declaration with delay
Eddie Hung [Mon, 10 Feb 2020 18:17:23 +0000 (10:17 -0800)]
abc9: cleanup
Eddie Hung [Mon, 10 Feb 2020 16:31:01 +0000 (08:31 -0800)]
Merge pull request #1670 from rodrigomelo9/master
$readmem[hb] file inclusion is now relative to the Verilog file
N. Engelhardt [Mon, 10 Feb 2020 11:38:28 +0000 (12:38 +0100)]
Merge pull request #1669 from thasti/pyosys-attrs
Make RTLIL attributes accessible via pyosys
whitequark [Sun, 9 Feb 2020 20:29:16 +0000 (20:29 +0000)]
Merge pull request #1695 from whitequark/manual-explain-wire-upto-offset
manual: explain RTLIL::Wire::{upto,offset}
whitequark [Sun, 9 Feb 2020 14:54:07 +0000 (14:54 +0000)]
manual: explain RTLIL::Wire::{upto,offset}.
R. Ou [Sun, 9 Feb 2020 09:01:18 +0000 (01:01 -0800)]
json: Change compat mode to directly emit ints <= 32 bits
This increases compatibility with certain older parsers in some cases
that worked before commit
15fae357 but do not work with the current
compat-int mode
Eddie Hung [Fri, 7 Feb 2020 20:45:07 +0000 (12:45 -0800)]
Remove unnecessary comma
Eddie Hung [Fri, 7 Feb 2020 20:32:08 +0000 (12:32 -0800)]
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
Fix shiftx2mux, fix yosys-tests
Eddie Hung [Fri, 7 Feb 2020 19:02:48 +0000 (11:02 -0800)]
techmap: fix shiftx2mux decomposition
Eddie Hung [Fri, 7 Feb 2020 16:27:45 +0000 (08:27 -0800)]
Fix misc.abc9.abc9_abc9_luts
Marcin Kościelnicki [Mon, 3 Feb 2020 17:37:28 +0000 (18:37 +0100)]
xilinx: Add support for LUT RAM on LUT4-based devices.
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
Marcin Kościelnicki [Mon, 3 Feb 2020 15:19:24 +0000 (16:19 +0100)]
xilinx: Initial support for LUT4 devices.
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
Eddie Hung [Fri, 7 Feb 2020 04:59:21 +0000 (20:59 -0800)]
Merge pull request #1685 from dh73/gowin
Removing cells_sim from GoWin bram techmap
whitequark [Fri, 7 Feb 2020 02:54:04 +0000 (02:54 +0000)]
Merge pull request #1683 from whitequark/write_verilog-memattrs
write_verilog: dump $mem cell attributes
Marcin Kościelnicki [Tue, 4 Feb 2020 14:35:47 +0000 (15:35 +0100)]
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Marcin Kościelnicki [Mon, 3 Feb 2020 17:50:33 +0000 (18:50 +0100)]
xilinx: Add support for Spartan 3A DSP block RAMs.
Part of #1550
Eddie Hung [Thu, 6 Feb 2020 21:51:23 +0000 (13:51 -0800)]
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
Fix/cleanup +/xilinx/arith_map.v
Diego H [Thu, 6 Feb 2020 20:38:29 +0000 (14:38 -0600)]
Removing cells_sim.v from bram techmap pass
Eddie Hung [Thu, 6 Feb 2020 19:25:07 +0000 (11:25 -0800)]
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
Eddie Hung [Tue, 21 Jan 2020 16:42:37 +0000 (08:42 -0800)]
Fix/cleanup +/xilinx/arith_map.v
Marcin Kościelnicki [Sat, 1 Feb 2020 14:27:27 +0000 (15:27 +0100)]
edif: more resilience to mismatched port connection sizes.
Fixes #1653.
whitequark [Thu, 6 Feb 2020 16:22:22 +0000 (16:22 +0000)]
write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
Rodrigo Alejandro Melo [Thu, 6 Feb 2020 13:45:40 +0000 (10:45 -0300)]
Added 'set -e' into tests/memfile/run-test.sh
Also added two checks for situations where the execution must fail.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Rodrigo Alejandro Melo [Thu, 6 Feb 2020 13:10:29 +0000 (10:10 -0300)]
Modified $readmem[hb] to use '\' or '/' according the OS
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Eddie Hung [Thu, 6 Feb 2020 04:21:40 +0000 (20:21 -0800)]
Merge pull request #1682 from YosysHQ/eddie/opt_after_techmap
synth_*: call 'opt -fast' after 'techmap'
Eddie Hung [Thu, 6 Feb 2020 02:39:01 +0000 (18:39 -0800)]
synth_*: call 'opt -fast' after 'techmap'
Eddie Hung [Thu, 6 Feb 2020 00:41:09 +0000 (16:41 -0800)]
shiftx2mux: fix select out of bounds
Eddie Hung [Wed, 5 Feb 2020 22:56:26 +0000 (14:56 -0800)]
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
Eddie Hung [Wed, 5 Feb 2020 22:55:57 +0000 (14:55 -0800)]
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
techmap LSB-first for compatible $shift/$shiftx cells
Eddie Hung [Wed, 5 Feb 2020 22:46:48 +0000 (14:46 -0800)]
abc9_ops: -reintegrate to use derived_type for box_ports
Eddie Hung [Wed, 5 Feb 2020 18:47:31 +0000 (10:47 -0800)]
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Eddie Hung [Wed, 5 Feb 2020 18:31:18 +0000 (19:31 +0100)]
Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
Eddie Hung [Wed, 5 Feb 2020 17:59:40 +0000 (18:59 +0100)]
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
Stefan Biereigel [Mon, 3 Feb 2020 20:29:54 +0000 (21:29 +0100)]
add testcase for #1614
Stefan Biereigel [Mon, 3 Feb 2020 20:29:40 +0000 (21:29 +0100)]
correct wire declaration grammar for #1614
Stefan Biereigel [Mon, 3 Feb 2020 19:54:32 +0000 (20:54 +0100)]
remove namespace mention from inheritance information
Stefan Biereigel [Mon, 3 Feb 2020 19:21:02 +0000 (20:21 +0100)]
expose polymorphism through python wrappers
Rodrigo A. Melo [Mon, 3 Feb 2020 14:07:51 +0000 (11:07 -0300)]
Merge branch 'master' into master
Marcelina Kościelnicka [Mon, 3 Feb 2020 13:57:17 +0000 (14:57 +0100)]
Add opt_lut_ins pass. (#1673)
Rodrigo Alejandro Melo [Mon, 3 Feb 2020 13:56:11 +0000 (10:56 -0300)]
Merge branch 'master' of https://github.com/YosysHQ/yosys
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Rodrigo Alejandro Melo [Mon, 3 Feb 2020 13:30:33 +0000 (10:30 -0300)]
Replaced strlen by GetSize into simplify.cc
As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
David Shah [Sun, 2 Feb 2020 18:12:28 +0000 (18:12 +0000)]
Merge pull request #1516 from YosysHQ/dave/dotstar
sv: Add support for wildcard port connections (.*)
David Shah [Fri, 22 Nov 2019 15:32:46 +0000 (15:32 +0000)]
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 15:07:55 +0000 (15:07 +0000)]
sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 12:57:51 +0000 (12:57 +0000)]
sv: More tests for wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 09:21:35 +0000 (09:21 +0000)]
hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 09:16:37 +0000 (09:16 +0000)]
sv: Add tests for wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 09:04:54 +0000 (09:04 +0000)]
hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 08:24:01 +0000 (08:24 +0000)]
sv: Add lexing and parsing of .* (wildcard port conns)
Signed-off-by: David Shah <dave@ds0.me>
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 15:33:34 +0000 (12:33 -0300)]
Removed 'synth' into tests/memfile/run-test.sh
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 15:18:34 +0000 (12:18 -0300)]
Added content1.dat into tests/memfile
Modified run-test.sh to use it.
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
David Shah [Sun, 2 Feb 2020 14:53:46 +0000 (14:53 +0000)]
Merge pull request #1647 from YosysHQ/dave/sprintf
ast: Add support for $sformatf system function
David Shah [Sun, 2 Feb 2020 14:53:32 +0000 (14:53 +0000)]
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
Marcin Kościelnicki [Sun, 2 Feb 2020 10:26:00 +0000 (11:26 +0100)]
xilinx: use RAM32M/RAM64M for memories with two read ports
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 01:48:03 +0000 (22:48 -0300)]
Removed a line jump into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 01:44:06 +0000 (22:44 -0300)]
Added tests/memfile to 'make test' with an extra testcase
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 20:41:10 +0000 (17:41 -0300)]
Added a test for the Memory Content File inclusion using $readmemb
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 20:03:56 +0000 (17:03 -0300)]
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
David Shah [Mon, 27 Jan 2020 11:19:27 +0000 (11:19 +0000)]
xilinx_dsp: Add multonly scratchpad var to bypass
Signed-off-by: David Shah <dave@ds0.me>
Marcin Kościelnicki [Sat, 1 Feb 2020 09:21:19 +0000 (10:21 +0100)]
json: remove the 32-bit parameter special case
Before, the rules for encoding parameters in JSON were as follows:
- if the parameter is not a string:
- if it is exactly 32 bits long and there are no z or x bits, emit it
as an int
- otherwise, emit it as a string made of 0/1/x/z characters
- if the parameter is a string:
- if it contains only 0/1/x/z characters, append a space at the end
to distinguish it from a non-string
- otherwise, emit it directly
However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values. Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 01:10:51 +0000 (22:10 -0300)]
Modified the new search for files of $readmem[hb] to be backward compatible
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Fri, 31 Jan 2020 21:20:22 +0000 (18:20 -0300)]
$readmem[hb] file inclusion is now relative to the Verilog file
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Eddie Hung [Fri, 31 Jan 2020 09:34:13 +0000 (09:34 +0000)]
Merge pull request #1668 from gsomlo/gls-abc9-external
abc9: Fix regression breaking support for use of ABCEXTERNAL
Stefan Biereigel [Thu, 30 Jan 2020 20:26:37 +0000 (21:26 +0100)]
add inheritance for pywrap generators
Gabriel Somlo [Thu, 30 Jan 2020 20:12:43 +0000 (15:12 -0500)]
abc9: restore ability to use ABCEXTERNAL
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Claire Wolf [Thu, 30 Jan 2020 18:55:53 +0000 (19:55 +0100)]
Merge pull request #1667 from YosysHQ/clifford/verificnand
Add Verific support for OPER_REDUCE_NAND