mesa.git
10 years agoi965/fs: Rename c->sample_mask_reg to sample_mask_in_reg.
Kenneth Graunke [Wed, 14 May 2014 04:36:28 +0000 (21:36 -0700)]
i965/fs: Rename c->sample_mask_reg to sample_mask_in_reg.

This is actually for gl_SampleMaskIn, which is quite different than
gl_SampleMask.  Renaming should help avoid confusion.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
10 years agoi965/fs: Move c->last_scratch into fs_visitor.
Kenneth Graunke [Wed, 14 May 2014 04:00:35 +0000 (21:00 -0700)]
i965/fs: Move c->last_scratch into fs_visitor.

Nothing outside of fs_visitor uses it, so we may as well keep it
internal.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
10 years agoi965/fs: Move total_scratch calculation into fs_visitor::run().
Kenneth Graunke [Wed, 14 May 2014 03:51:32 +0000 (20:51 -0700)]
i965/fs: Move total_scratch calculation into fs_visitor::run().

With this one use gone, c->last_scratch is now only used inside
fs_visitor.  The rest of the driver uses prog_data->total_scratch.

We already compute similar prog_data fields in fs_visitor, so this
seems reasonable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
10 years agoi965/fs: Move perf_debug about register spilling to a more obvious spot.
Kenneth Graunke [Wed, 14 May 2014 03:41:27 +0000 (20:41 -0700)]
i965/fs: Move perf_debug about register spilling to a more obvious spot.

The if (!allocated_without_spills) block is an obvious spot for this
performance warning message.

In the Vec4 backend, scratch is also used for indirect access of
temporary arrays.  The FS backend doesn't implement that yet, but
if it did, this message would be inaccurate, since scratch access
wouldn't necessarily mean spilling.  Moving it preemptively fixes that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
10 years agoi965: Rename brw/gen8_dump_compile to brw/gen8_disassemble.
Kenneth Graunke [Thu, 15 May 2014 23:10:09 +0000 (16:10 -0700)]
i965: Rename brw/gen8_dump_compile to brw/gen8_disassemble.

"Disassemble" is an accurate description of what this function does.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoi965: Rename brw_disasm/gen8_disassemble to brw/gen8_disassemble_inst.
Kenneth Graunke [Thu, 15 May 2014 23:02:16 +0000 (16:02 -0700)]
i965: Rename brw_disasm/gen8_disassemble to brw/gen8_disassemble_inst.

We're going to use "disassemble" for the function that disassembles
the whole program.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoi965: Fix dump_prog_cache to handle compacted instructions.
Kenneth Graunke [Thu, 15 May 2014 22:58:07 +0000 (15:58 -0700)]
i965: Fix dump_prog_cache to handle compacted instructions.

dump_prog_cache has interpreted compacted instructions as full size
instructions, decoding garbage and complaining about invalid values.

We can just use brw_dump_compile to handle this correctly in less code.
The output format changes slightly, but it's still perfectly acceptable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoi965: Use brw_dump_compile for clip, SF, and old GS programs.
Kenneth Graunke [Thu, 15 May 2014 21:12:48 +0000 (14:12 -0700)]
i965: Use brw_dump_compile for clip, SF, and old GS programs.

Looping over the instructions and calling brw_disasm doesn't handle
compacted instructions.  In most cases, this hasn't been a problem since
we don't compact prior to Sandybridge.

However, Sandybridge's transform feedback GS program should already be
compacted, and so this ought to fix decoding of that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agonv50/ir: fix integer mul lowering for u32 x u32 -> high u32
Ilia Mirkin [Tue, 13 May 2014 15:23:33 +0000 (11:23 -0400)]
nv50/ir: fix integer mul lowering for u32 x u32 -> high u32

UNION appears to expect that all of its sources are conditionally
defined. Otherwise it inserts an unpredicated mov instruction which
overwrites the desired result. This fixes tests that use UMUL_HI, and
much less directly, unsigned integer division by a constant, which uses
this functionality in a peephole pass.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
10 years agonv50/ir: make sure that texprep/texquerylod's args get coalesced
Ilia Mirkin [Tue, 13 May 2014 05:31:20 +0000 (01:31 -0400)]
nv50/ir: make sure that texprep/texquerylod's args get coalesced

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
10 years agofreedreno/a3xx: use util_format_compose_swizzles()
Rob Clark [Sun, 18 May 2014 19:19:34 +0000 (15:19 -0400)]
freedreno/a3xx: use util_format_compose_swizzles()

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx/compiler: 1D textures
Rob Clark [Sat, 17 May 2014 17:49:52 +0000 (13:49 -0400)]
freedreno/a3xx/compiler: 1D textures

Gallium already gives us height==1 for these, so the texture state is
already setup correctly to emulate 1D textures as a Nx1 2D texture.  We
just need to supply the .y coord.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno: fix caps
Rob Clark [Sun, 18 May 2014 12:02:08 +0000 (08:02 -0400)]
freedreno: fix caps

In particular, we want mesa to emulate primitive restart for us.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno: fix index buffer offset
Rob Clark [Sat, 17 May 2014 17:50:10 +0000 (13:50 -0400)]
freedreno: fix index buffer offset

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx: add sRBG texture support
Rob Clark [Sat, 17 May 2014 00:29:44 +0000 (20:29 -0400)]
freedreno/a3xx: add sRBG texture support

That was easy.  Turns out it is just a matter of setting one bit.
Enable sampling from sRGB texture, and therefore enable GL 2.1 :-)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno: update generated headers
Rob Clark [Sat, 17 May 2014 00:07:36 +0000 (20:07 -0400)]
freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agogallivm: (trivial) fix compilation with llvm 3.1, 3.2
Roland Scheidegger [Sat, 17 May 2014 00:03:35 +0000 (02:03 +0200)]
gallivm: (trivial) fix compilation with llvm 3.1, 3.2

I actually checked the getModuleIdentifier() function exists with 3.1 but
missed that the file moved...
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=78803

10 years agogallivm: print out how long it takes to optimize shader IR.
Roland Scheidegger [Thu, 15 May 2014 23:01:07 +0000 (01:01 +0200)]
gallivm: print out how long it takes to optimize shader IR.

Enabled with GALLIVM_DEBUG=perf (which up to now was only used to print
warnings for unoptimized code).

While some unexpectedly long shader compile times for some shaders were fixed
with 8a9f5ecdb116d0449d63f7b94efbfa8b205d826f this should help recognize such
problems in the future. For now though only available in debug builds (which
are not always suitable for such analysis). And since this uses system time,
it might not be all that accurate (even llvmpipe's own rasterization threads
might be running at the same time, or just other tasks).
(llvmpipe also has LP_DEBUG=counters but this only gives an average per shader
and the the total time for all shaders.)
This prints information like this:
optimizing module fs17_variant0 took 1 msec
optimizing module setup_variant_0 took 0 msec
optimizing module draw_llvm_vs_variant0 took 9 msec
optimizing module draw_llvm_vs_variant0 took 12 msec
optimizing module fs17_variant1 took 2 msec

v2: rebase for recent gallivm compilation changes, and print time for whole
modules instead of functions (otherwise it would be very spammy since it would
include all trivial inline sse2 functions), using the shiny new module names,
prying them off LLVM using new helper (not available through C bindings).
Per function timings, while possibly giving more information (if there'd be
a problem only in for instance the partial not the whole function), don't seem
all that useful for now.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agogallivm: give more verbose names to modules
Roland Scheidegger [Thu, 15 May 2014 23:00:53 +0000 (01:00 +0200)]
gallivm: give more verbose names to modules

When we had just one module "gallivm" was an appropriate name. But now we have
modules containing all functions for a particular variant, so give it a
corresponding name (this is really just for helping debugging).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agomesa: fix double-freeing of dispatch tables inside glBegin/End.
Brian Paul [Thu, 15 May 2014 21:49:14 +0000 (15:49 -0600)]
mesa: fix double-freeing of dispatch tables inside glBegin/End.

We allocate dispatch tables for BeginEnd and OutsideBeginEnd.  But
when we destroy the context we were freeing the BeginEnd and Exec
tables.  If Exec==BeginEnd we did a double-free.  This would happen
if the context was destroyed while inside a glBegin/End pair.  Now
free the BeginEnd and OutsideBeginEnd pointers.

Cc: "10.1", "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
10 years agoi965: Use binary literals counter select.
Matt Turner [Tue, 4 Mar 2014 03:10:44 +0000 (19:10 -0800)]
i965: Use binary literals counter select.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoglsl_to_tgsi: Make sure the 'shader' member is always initialized
Michel Dänzer [Thu, 15 May 2014 03:23:16 +0000 (12:23 +0900)]
glsl_to_tgsi: Make sure the 'shader' member is always initialized

Fixes the valgrind report below and random crashes with piglit on radeonsi.

==30005== Conditional jump or move depends on uninitialised value(s)
==30005==    at 0xB13584E: st_translate_program (st_glsl_to_tgsi.cpp:5100)
==30005==    by 0xB14698B: st_translate_fragment_program (st_program.c:747)
==30005==    by 0xB14777D: st_get_fp_variant (st_program.c:824)
==30005==    by 0xB11219C: get_color_fp_variant (st_cb_drawpixels.c:1042)
==30005==    by 0xB1131AE: st_DrawPixels (st_cb_drawpixels.c:1154)
==30005==    by 0xAFF8806: _mesa_DrawPixels (drawpix.c:162)
==30005==    by 0x4EB86DB: stub_glDrawPixels (generated_dispatch.c:6640)
==30005==    by 0x4F1DF08: piglit_visualize_image (piglit-util-gl.c:1574)
==30005==    by 0x40691D: draw_image_to_window_system_fb(int, bool) (draw-buffers-common.cpp:733)
==30005==    by 0x406C8B: draw_reference_image(bool, bool) (draw-buffers-common.cpp:854)
==30005==    by 0x40722A: piglit_display (alpha-to-coverage-dual-src-blend.cpp:117)
==30005==    by 0x4EA7168: run_test (piglit_fbo_framework.c:52)

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: remove optimization workaround when not having sse 4.1
Roland Scheidegger [Thu, 15 May 2014 15:01:40 +0000 (17:01 +0200)]
gallivm: remove optimization workaround when not having sse 4.1

This workaround doesn't list any llvm version, but it was introduced
2010-06-10 (e277d5c1f6b2c5a6d202561e67d2b6821a69ecc4). It is unlikely
this bug is still present in llvm versions we support (3.1+).
There's no specific test listed, but I ran lp_test_arit (which uses
the mentioned functions) on llvm 3.1 and 3.3 with sse41 disabled and
this pass enabled without issues.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agogallivm: remove workaround for reversing optimization pass order.
Roland Scheidegger [Thu, 15 May 2014 14:26:00 +0000 (16:26 +0200)]
gallivm: remove workaround for reversing optimization pass order.

32bit code generation and llvm >= 2.7 used a different optimization pass
order - this code was initially introduced (2010-07-23) by
815e79e72c1f4aa849c0ee6103621685b678bc9d, apparently due to buggy code being
generated with then brand new llvm versions (which was llvm 2.7 plus pre 2.8
devel).
It seems very highly likely that whatever this bug was it has been fixed in
newer llvm versions, though there's no easy way to test this - the mentioned
piglit test has been removed years ago, and even if you'd build it I'm
sceptical the glsl compiler would still produce the required code to trigger
it.
I have no idea what a good order of passes is, but just remove the workaround
and use the same order everywhere.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agoi965/gen8: Make disassembly function match brw's signature.
Matt Turner [Fri, 9 May 2014 00:27:31 +0000 (17:27 -0700)]
i965/gen8: Make disassembly function match brw's signature.

gen8_dump_compile will be called indirectly by code common used by
generations before and after the gen8 instruction format change.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965: Pass brw_context and assembly separately to brw_dump_compile.
Matt Turner [Fri, 9 May 2014 23:15:30 +0000 (16:15 -0700)]
i965: Pass brw_context and assembly separately to brw_dump_compile.

brw_dump_compile will be called indirectly by code common used by
generations before and after the gen8 instruction format change.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965: Pull brw_compact_instructions() out of brw_get_program().
Matt Turner [Wed, 7 May 2014 18:53:22 +0000 (11:53 -0700)]
i965: Pull brw_compact_instructions() out of brw_get_program().

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/disasm: Align send instruction meta-information with dst.
Matt Turner [Thu, 8 May 2014 23:06:33 +0000 (16:06 -0700)]
i965/disasm: Align send instruction meta-information with dst.

Has been misaligned since we added instruction offset prefixes.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/disasm: Disassemble the compaction control bit.
Matt Turner [Thu, 1 May 2014 18:20:25 +0000 (11:20 -0700)]
i965/disasm: Disassemble the compaction control bit.

brw_disasm doesn't disassemble compacted instructions, so we uncompact
before disassembling them which would unset the compaction control bit.
Instead pass it as a separate argument.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/cfg: Embed exec_node in bblock_link.
Matt Turner [Mon, 12 May 2014 21:40:40 +0000 (14:40 -0700)]
i965/cfg: Embed exec_node in bblock_link.

In order to remove bblock_link's inheritance of exec_node. Also makes
linked list walk code much nicer.

Acked-by: Eric Anholt <eric@anholt.net>
10 years agoi965/cfg: Make brw_cfg.h closer to C-includable.
Matt Turner [Mon, 12 May 2014 16:54:15 +0000 (09:54 -0700)]
i965/cfg: Make brw_cfg.h closer to C-includable.

Only bblock_link's inheritance left.

Acked-by: Eric Anholt <eric@anholt.net>
10 years agoi965/cfg: Protect brw_cfg.h from multiple inclusion.
Matt Turner [Wed, 19 Feb 2014 22:47:57 +0000 (14:47 -0800)]
i965/cfg: Protect brw_cfg.h from multiple inclusion.

Acked-by: Eric Anholt <eric@anholt.net>
10 years agoglsl: Add C-callable fprint_ir function.
Matt Turner [Tue, 13 May 2014 01:16:22 +0000 (18:16 -0700)]
glsl: Add C-callable fprint_ir function.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/fb: Use meta path for stencil up/downsampling
Topi Pohjolainen [Mon, 12 May 2014 09:42:28 +0000 (12:42 +0300)]
i965/fb: Use meta path for stencil up/downsampling

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
10 years agoi965/meta: Stencil blit for miptree updownsampling
Topi Pohjolainen [Mon, 12 May 2014 09:35:40 +0000 (12:35 +0300)]
i965/meta: Stencil blit for miptree updownsampling

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/fb: Use meta path for stencil blits
Topi Pohjolainen [Sat, 19 Apr 2014 14:11:10 +0000 (17:11 +0300)]
i965/fb: Use meta path for stencil blits

This is effective only on gen8 for now as previous generations still
go through blorp.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/meta: Stencil blits
Topi Pohjolainen [Mon, 5 May 2014 19:18:46 +0000 (22:18 +0300)]
i965/meta: Stencil blits

v2: Create the intel renderbuffer with level hardcoded to zero instead
    of overriding it in the surface state configuration. Also moved the
    dimension adjustments for tiling, mip level, msaa into the render
    buffer creation. Finally prepares for another blit path needed for
    miptree updownsampling.
v3 (Ken): Dropped unnecessary memory context for "ralloc_asprintf()"

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
10 years agoi965: Extend brw_get_rb_for_first_slice() for specified level/layer
Topi Pohjolainen [Fri, 18 Apr 2014 23:02:42 +0000 (02:02 +0300)]
i965: Extend brw_get_rb_for_first_slice() for specified level/layer

v2: Configure stencil directly for final dimensions instead of
    adjusting bit by bit for tiling, mip level and msaa.
v3 (Ken): Used non-static constant for horizontal alignment

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/gen8: Surface state overriding for stencil
Topi Pohjolainen [Wed, 7 May 2014 09:16:28 +0000 (12:16 +0300)]
i965/gen8: Surface state overriding for stencil

v2: Allow hardware to offset accesses to individual layers. Also leave
    the mip-level overriding for the creator of the intel renderbuffer
    to handle. Merged with "i965/gen8: Allow stencil buffers to be
    configured as single sampled"

Ken: I left the "_mesa_problem()" still in place. I think it is clearer
     to remove it in a separate patch.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965/wm: Surface state overrides for configuring w-tiled as y-tiled
Topi Pohjolainen [Wed, 7 May 2014 07:49:50 +0000 (10:49 +0300)]
i965/wm: Surface state overrides for configuring w-tiled as y-tiled

v2: Use intel_mipmap_tree::total_width in order to get correct alignment
    automatically. Also use "mt->total_height / mt->physical_depth0" as
    surface height allowing hardware to offset to correct slice.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoi965 meta up/downsample: Fix renderbuffer _BaseFormat
Jordan Justen [Thu, 15 May 2014 06:06:47 +0000 (06:06 +0000)]
i965 meta up/downsample: Fix renderbuffer _BaseFormat

mt->format is of type mesa_format, and therefore can't be
used with _mesa_base_fbo_format which requires a GLenum input.

On gen8, this fixes various piglit fbo-depthstencil tests with
samples > 1.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
10 years agoi965: Delete current_insn() function.
Matt Turner [Mon, 5 May 2014 21:08:56 +0000 (14:08 -0700)]
i965: Delete current_insn() function.

10 years agoi965: Remove blorp unit tests.
Matt Turner [Wed, 14 May 2014 22:15:02 +0000 (15:15 -0700)]
i965: Remove blorp unit tests.

They've served their purpose (in transitioning blorp to using
fs_generator) and now they just necessitate large amounts of manual
labor to regenerate if the disassembler changes.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
10 years agoegl-static: include libradeonwinsys.la only once
Emil Velikov [Sat, 10 May 2014 14:59:03 +0000 (15:59 +0100)]
egl-static: include libradeonwinsys.la only once

With this and the previous patch, we no longer have multiple
definitions in the final egl_gallium.so.

v2: Drop duplicate libloader link.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chia-I Wu <olv@lunarg.com> (v1)
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> (v1)
10 years agogallium/radeon: link in libradeon.la at target level
Emil Velikov [Sat, 10 May 2014 13:35:08 +0000 (14:35 +0100)]
gallium/radeon: link in libradeon.la at target level

It makes more sense to link the core and common parts of the driver as the
target is build. Additionally this will help us drop duplicating symbols
for targets that static link mulitple pipe-drivers. Only egl-static needs
that currently with more to come.

To simplify things a bit add HAVE_GALLIUM_RADEON_COMMON variable.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
10 years agogallium/radeon: build only a single common library libradeon
Emil Velikov [Sat, 10 May 2014 13:25:08 +0000 (14:25 +0100)]
gallium/radeon: build only a single common library libradeon

Just fold libllvmradeon in libradeon.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
10 years agofreedreno/a3xx: fix write to bogus register
Rob Clark [Wed, 14 May 2014 16:46:42 +0000 (12:46 -0400)]
freedreno/a3xx: fix write to bogus register

The loops for updating the multiple packed fields in SP_VS_OUT[] and
SP_VS_VPC_DST[] will zero out one register beyond the last that on
required.  Which is normally not a problem (and is kinda convenient
when looking at cmdstream dumps) unless we have maximum (16) varyings.

Fix loop termination condition so that this does not happen.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx: account for special inputs/outputs
Rob Clark [Wed, 14 May 2014 15:39:44 +0000 (11:39 -0400)]
freedreno/a3xx: account for special inputs/outputs

We need to size input/output tables big enough for special inputs/
outputs (gl_Position, gl_FrontFacing, etc) which, while they don't
count towards the hw limit of 16 attributes or 16 varyings, we do
still need to track them all the same.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx: fix MAX_INPUTS shader cap
Rob Clark [Wed, 14 May 2014 15:15:26 +0000 (11:15 -0400)]
freedreno/a3xx: fix MAX_INPUTS shader cap

Hardware only supports 16.  Which fd3_shader_variant properly reflected,
but the pipe cap did not, leading to array overflow (and shaders that
could not possibly work).

Also a bunch of asserts to make problems like this easier to see.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx: add debug flag to expose glsl130
Rob Clark [Wed, 14 May 2014 15:06:21 +0000 (11:06 -0400)]
freedreno/a3xx: add debug flag to expose glsl130

We are starting to add integer support to the compiler, which does not
get exercised with glsl feature level 120 and without advertising
integer support.  But doing so breaks too many things right now.  So
for now use a debug flag to conditionally expose the functionality
while it is in development.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx/compiler: add KILL_IF
Ryan Houdek [Wed, 14 May 2014 02:58:03 +0000 (21:58 -0500)]
freedreno/a3xx/compiler: add KILL_IF

The KILL_IF opcode could potentially be merged in to the regular KILL
opcode function.  It was a pain to do so, so I've left is separated
for cleanliness.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/a3xx/compiler: start adding integer support
Ryan Houdek [Wed, 14 May 2014 02:44:41 +0000 (21:44 -0500)]
freedreno/a3xx/compiler: start adding integer support

Adds a large sum of TGSI opcodes to the a3xx compiler.

For integer opcodes we have 28 opcodes added.
Adds 4 floating point compare opcodes

If GLSL 1.30 is enabled, this allows the GLSL 1.30 piglits to have a
completion amount of 432/641.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agodraw: better llvm names for shaders for debugging.
Roland Scheidegger [Tue, 13 May 2014 01:43:11 +0000 (03:43 +0200)]
draw: better llvm names for shaders for debugging.

All shaders had the same name.
We could probably use some identifier per shader too, but for now only use
the variant number.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agollvmpipe: improve setup shader names (for debugging)
Roland Scheidegger [Tue, 13 May 2014 00:59:30 +0000 (02:59 +0200)]
llvmpipe: improve setup shader names (for debugging)

The setup shaders were composed of both a fs shader number and a variant
number. But since they aren't tied to a particular fragment shader, the
former was a fixed zero while the latter was also always zero because
it was never assigned. So, similar to what the fs code does, use a ever
increasing number to give it a more catchy name (unlike fragment shaders
though where this number is for each explicitly created shader, we just use
it for the implicitly created variants).
And while here, fix whitespace a bit.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agollvmpipe: kill off llvmpipe_variant_count
Roland Scheidegger [Tue, 13 May 2014 00:20:32 +0000 (02:20 +0200)]
llvmpipe: kill off llvmpipe_variant_count

Unused except it was increased for both fs and setup shader variants created.
Probably some leftover from ages ago.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agomesa/st: fix number of ubos being declared in a shader
Roland Scheidegger [Wed, 14 May 2014 19:06:23 +0000 (21:06 +0200)]
mesa/st: fix number of ubos being declared in a shader

Previously the code used the total number of ubos being declared in the
linked program (so the ubos of all shaders combined), use the number
from the particular shader instead.
This fixes an assertion failure with piglit arb_uniform_buffer_object-maxblocks
seen in llvmpipe since 8a9f5ecdb116d0449d63f7b94efbfa8b205d826f as it now emits
code for each declared buffer, not just the ones actually used.

CC: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
10 years agonvc0: enable support for maxwell boards
Ben Skeggs [Fri, 9 May 2014 05:56:08 +0000 (15:56 +1000)]
nvc0: enable support for maxwell boards

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: add maxwell (sm50) compiler backend
Ben Skeggs [Fri, 9 May 2014 05:56:05 +0000 (15:56 +1000)]
nvc0: add maxwell (sm50) compiler backend

The big missing part here is proper sched data calculations, but
hopefully the chosen placeholder will be sufficient for now.

Passes piglit as well as GK107 does.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: maxwell isa has no per-instruction join modifier
Ben Skeggs [Fri, 9 May 2014 05:56:03 +0000 (15:56 +1000)]
nvc0: maxwell isa has no per-instruction join modifier

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: replace immd 0 with $rLASTGPR for emit/restart opcodes
Ben Skeggs [Fri, 9 May 2014 05:56:01 +0000 (15:56 +1000)]
nvc0: replace immd 0 with $rLASTGPR for emit/restart opcodes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: move nvc0 lowering pass class definitions into header
Ben Skeggs [Fri, 9 May 2014 05:55:59 +0000 (15:55 +1000)]
nvc0: move nvc0 lowering pass class definitions into header

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: bump sched data member to 32-bits
Ben Skeggs [Fri, 9 May 2014 05:55:57 +0000 (15:55 +1000)]
nvc0: bump sched data member to 32-bits

SM50 backend requires 21 bits per instruction, not 8.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: use vertex arrays for eng3d blit
Ben Skeggs [Fri, 9 May 2014 05:55:55 +0000 (15:55 +1000)]
nvc0: use vertex arrays for eng3d blit

Maxwell doesn't have immediate-mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: restrict "constant vbo" logic to fermi/kepler classes
Ben Skeggs [Fri, 9 May 2014 05:55:53 +0000 (15:55 +1000)]
nvc0: restrict "constant vbo" logic to fermi/kepler classes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: replace some vb->stride checks with constant_vbo instead
Ben Skeggs [Fri, 9 May 2014 05:55:51 +0000 (15:55 +1000)]
nvc0: replace some vb->stride checks with constant_vbo instead

Maxwell no longer has the methods to set constant attributes, and we'll
want to be treating stride 0 vtxbufs the same as for stride > 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: add maxwell class
Ben Skeggs [Fri, 9 May 2014 05:55:49 +0000 (15:55 +1000)]
nvc0: add maxwell class

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: allow for easier modification of compiler library routines
Ben Skeggs [Fri, 9 May 2014 05:55:47 +0000 (15:55 +1000)]
nvc0: allow for easier modification of compiler library routines

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agonvc0: properly distribute macros in source form
Ben Skeggs [Fri, 9 May 2014 05:55:44 +0000 (15:55 +1000)]
nvc0: properly distribute macros in source form

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
10 years agodocs: Add a note about llvm-shared-libs and libxatracker
Emil Velikov [Mon, 5 May 2014 21:09:23 +0000 (22:09 +0100)]
docs: Add a note about llvm-shared-libs and libxatracker

Both changes landed in 10.2, and for people not following the
development cycle these will come as a surprise. Note that the
pipe_* interface is not stable.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>
10 years agoautomake: Honor GL_LIB for gallium libgl-xlib
Brad King [Tue, 6 May 2014 15:06:47 +0000 (11:06 -0400)]
automake: Honor GL_LIB for gallium libgl-xlib

Use "@GL_LIB@" in src/gallium/targets/libgl-xlib/Makefile.am to produce
the library name specified by the configure --with-gl-lib-name option.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
10 years agoconfigure: correctly set LD_NO_UNDEFINED
Emil Velikov [Tue, 13 May 2014 00:33:48 +0000 (01:33 +0100)]
configure: correctly set LD_NO_UNDEFINED

Commit 11623be934f85 was meant to have this hunk, which
I accidently dropped during git rebase.

Cc: 10.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Julien Cristau <jcristau@debian.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
10 years agogallivm: only fetch pointers to constant buffers once
Roland Scheidegger [Wed, 14 May 2014 13:43:53 +0000 (15:43 +0200)]
gallivm: only fetch pointers to constant buffers once

In 1d35f77228ad540a551a8e09e062b764a6e31f5e support for multiple constant
buffers was introduced. This meant we had another indirection, and we did
resolve the indirection for each constant buffer access. This looks very
reasonable since llvm can figure out if it's the same pointer, however it
turns out that this can cause llvm compilation time to go through the roof
and beyond (I've seen cases in excess of factor 100, e.g. from 50 ms to more
than 10 seconds (!)), with all the additional time spent in IR optimization
passes (and in the end all of it in DominatorTree::dominate()).
I've been unable to narrow it down a bit more (only some shaders seem affected,
seemingly without much correlation to overall shader complexity or constant
usage) but it is easily avoidable by doing the buffer lookups themeselves just
once (at constant buffer declaration time).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
10 years agogallivm: fix output stream flushing in error case for disassembly.
Roland Scheidegger [Wed, 14 May 2014 01:23:09 +0000 (03:23 +0200)]
gallivm: fix output stream flushing in error case for disassembly.

When there's an error, also need to flush the stream, otherwise an assertion
is hit (meaning you don't actually see the error neither).

10 years agoradeonsi: Fix anisotropic filtering state setup
Michel Dänzer [Wed, 14 May 2014 07:30:33 +0000 (16:30 +0900)]
radeonsi: Fix anisotropic filtering state setup

Bring it back in line with r600g. I broke this in the original radeonsi
bringup. :(

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78537

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
10 years agotgsi: support parsing texture offsets from text tgsi shaders
Ilia Mirkin [Thu, 8 May 2014 01:15:12 +0000 (21:15 -0400)]
tgsi: support parsing texture offsets from text tgsi shaders

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agomesa/st: provide native integers implementation of ir_unop_any
Ilia Mirkin [Thu, 8 May 2014 13:06:36 +0000 (09:06 -0400)]
mesa/st: provide native integers implementation of ir_unop_any

Previously, ir_unop_any was implemented via a dot-product call, which
uses floating point multiplication and addition. The multiplication was
completely pointless, and the addition can just as well be done with an
or. Since we know that the inputs are booleans, they must already be in
canonical 0/~0 format, and the final SNE can also be avoided.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallium/docs: clarify when query results are reset
Rob Clark [Tue, 13 May 2014 02:19:03 +0000 (22:19 -0400)]
gallium/docs: clarify when query results are reset

It wasn't completely clear from the docs, so I had to figure out by
looking at piglit results.  Hopefully this saves the next driver writer
implementing queries some time.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agogallivm: Remove lp_func_delete_body.
José Fonseca [Mon, 12 May 2014 15:12:32 +0000 (16:12 +0100)]
gallivm: Remove lp_func_delete_body.

Not necessary, now that we will free the whole module (hence all
function bodies) immediately after compiling.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: Remove gallivm_free_function.
José Fonseca [Mon, 12 May 2014 14:59:55 +0000 (15:59 +0100)]
gallivm: Remove gallivm_free_function.

Unused.  Deprecated by gallivm_free_ir().

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agollvmpipe: Delete unneeded LLVM stuff earlier.
José Fonseca [Mon, 12 May 2014 14:59:13 +0000 (15:59 +0100)]
llvmpipe: Delete unneeded LLVM stuff earlier.

Same as Frank's change to draw module but for llvmpipe module.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agodraw: Delete unneeded LLVM stuff earlier.
Frank Henigman [Tue, 1 Oct 2013 19:15:43 +0000 (15:15 -0400)]
draw: Delete unneeded LLVM stuff earlier.

Free up unneeded LLVM stuff immediately after generating vertex shader
code.  Saves about 500K per shader.

v2: Don't bother calling gallivm_free_function (Jose)

Signed-off-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: Separate freeing LLVM intermediate data from freeing final code.
Frank Henigman [Tue, 1 Oct 2013 19:15:42 +0000 (15:15 -0400)]
gallivm: Separate freeing LLVM intermediate data from freeing final code.

Split free_gallivm_state() into two steps.  First step is
gallivm_free_ir() which cleans up the LLVM scaffolding used to generate
code while preserving the code itself.  Second step is
gallivm_free_code() to free the memory occupied by the code.

v2: s/gallivm_teardown/gallivm_free_ir/ (Jose)

Signed-off-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: One code memory pool with deferred free.
Frank Henigman [Tue, 1 Oct 2013 19:15:41 +0000 (15:15 -0400)]
gallivm: One code memory pool with deferred free.

Provide a JITMemoryManager derivative which puts all generated code into
one memory pool instead of creating a new one each time code is generated.
This saves significant memory per shader as the pool size is 512K and
a small shader occupies just several K.

This memory manager also defers freeing generated code until you tell
it to do so, making it possible to destroy the LLVM engine while keeping
the code, thus enabling future memory savings.

v2: Fix compilation errors with LLVM 3.4 (Jose)

Signed-off-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: Run passes per module, not per function.
José Fonseca [Mon, 12 May 2014 13:29:04 +0000 (14:29 +0100)]
gallivm: Run passes per module, not per function.

This is how it is meant to be done nowadays.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: Use LLVM global context.
José Fonseca [Thu, 8 May 2014 14:21:49 +0000 (15:21 +0100)]
gallivm: Use LLVM global context.

I saw that LLVM internally uses its global context for some things, even
when we use our own.  Given ours is also global, might as well use
LLVM's.

However, sepearate contexts can still be enabled with a simple source
code modification, for when the need/benefit arises.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm: Stop using module providers.
José Fonseca [Mon, 12 May 2014 13:03:47 +0000 (14:03 +0100)]
gallivm: Stop using module providers.

Nowadays LLVMModuleProviderRef is just an alias for LLVMModuleRef, so
its use just causes unnecessary confusion.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agogallivm,draw,llvmpipe: Remove support for versions of LLVM prior to 3.1.
José Fonseca [Thu, 8 May 2014 12:25:28 +0000 (13:25 +0100)]
gallivm,draw,llvmpipe: Remove support for versions of LLVM prior to 3.1.

Older versions haven't been tested probably don't work anyway.  But more
importantly, code supporting it is hindering further work.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agoconfigure: Require LLVM 3.1.
José Fonseca [Mon, 12 May 2014 15:30:51 +0000 (16:30 +0100)]
configure: Require LLVM 3.1.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agoscons: Require LLVM 3.1
José Fonseca [Thu, 8 May 2014 12:32:07 +0000 (13:32 +0100)]
scons: Require LLVM 3.1

Support for prior versions will be removed in the following change.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
10 years agoi965: Reformat brw_set_src1 so it can be easily found with grep.
Matt Turner [Fri, 2 May 2014 21:49:24 +0000 (14:49 -0700)]
i965: Reformat brw_set_src1 so it can be easily found with grep.

10 years agoi965: fix size assert for gen7 in brw_init_compaction_tables()
Samuel Iglesias Gonsalvez [Thu, 8 May 2014 13:55:08 +0000 (15:55 +0200)]
i965: fix size assert for gen7 in brw_init_compaction_tables()

It should compare with it's own size.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
10 years agoi965: Relax accumulator dependency scheduling on Gen < 6
Iago Toral Quiroga [Wed, 7 May 2014 07:58:43 +0000 (09:58 +0200)]
i965: Relax accumulator dependency scheduling on Gen < 6

Many instructions implicitly update the accumulator on Gen < 6. The instruction
scheduling code just calls add_barrier_deps() for each accumulator access on
these platforms, but a large class of operations don't actually update the
accumulator -- mostly move and logical instructions. Teaching the scheduling
code about this would allow more flexibility to schedule instructions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77740
Reviewed-by: Matt Turner <mattst88@gmail.com>
10 years agoglsl: simplify the M_PI*f macros, fixes build on OpenBSD
Jonathan Gray [Wed, 14 May 2014 05:13:55 +0000 (15:13 +1000)]
glsl: simplify the M_PI*f macros, fixes build on OpenBSD

The M_PI*f macros used a preprocessor paste to append 'f'
to M_PI defines, which works if the values are only numbers
but breaks on OpenBSD where M_PI definitions have casts
and brackets to meet requirements of a future version of POSIX,

http://austingroupbugs.net/view.php?id=801
http://austingroupbugs.net/view.php?id=828

Simplify the M_PI*f macros by using casts directly in the defines
as suggested by Kenneth Graunke.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78665
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
10 years agodocs: Really add the 10.1.3 release nots this time
Carl Worth [Wed, 14 May 2014 00:30:17 +0000 (17:30 -0700)]
docs: Really add the 10.1.3 release nots this time

Commit a96c3bccf6791359d1159ebe9475e0ed5cf790ed intended to add these, but I
forgot to add the file.

10 years agofreedreno/a3xx: occlusion query support
Rob Clark [Sun, 11 May 2014 18:15:32 +0000 (14:15 -0400)]
freedreno/a3xx: occlusion query support

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno: add support for hw queries
Rob Clark [Sat, 10 May 2014 17:45:54 +0000 (13:45 -0400)]
freedreno: add support for hw queries

Real GPU queries need some infrastructure to track samples per tile and
accumulate the results.  But fortunately this can be shared across GPU
generation.

See:
https://github.com/freedreno/freedreno/wiki/Queries#hardware-queries

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agofreedreno/query: allow multiple query implementations
Rob Clark [Fri, 9 May 2014 21:33:19 +0000 (17:33 -0400)]
freedreno/query: allow multiple query implementations

Split out fd_query into an abstract base class, to allow multiple
implementations.  The current sw based queries are moved into
fd_sw_query.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
10 years agomesa: Dump ARB_vp/fp source and IR when MESA_GLSL=dump.
Kenneth Graunke [Mon, 12 May 2014 03:22:48 +0000 (20:22 -0700)]
mesa: Dump ARB_vp/fp source and IR when MESA_GLSL=dump.

As far as I can tell, Mesa hasn't had a convenient way to dump ARB_vp/fp
source until now.  Using MESA_GLSL=dump is convenient, since it means
you can use a single environment variable to dump a program's shaders,
no matter which language they're written in.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
10 years agoi965: Don't _swrast_BlitFramebuffer when doing CopyTexSubImage.
Kenneth Graunke [Mon, 12 May 2014 00:20:08 +0000 (17:20 -0700)]
i965: Don't _swrast_BlitFramebuffer when doing CopyTexSubImage.

The point of copytexsubimage_using_blit_framebuffer is to use a hardware
accelerated BlitFramebuffer path.  If that fails, we shouldn't do a
swrast blit---we should try our CTSI fallback code.

This is especially important for i965 and GLES, where we don't even
create a swrast context.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77705
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
10 years agoi965/gen8: Set depth extent field
Jordan Justen [Tue, 13 May 2014 18:06:59 +0000 (18:06 +0000)]
i965/gen8: Set depth extent field

The depth extent field is used to limit the allowed slice range that
can be rendered to.

With the previous setting, only slice 0 could be rendered.

This fixes piglit amd_vertex_shader_layer-layered-depth-texture-render.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>