python: Use six's with_metaclass instead of it's add_metaclass.

The decorator creates two versions of a class, adding it to the Params
dict multiple times which generates an annoying warning. Alternatively,
the with_metaclass mechanism sets up an alternative base class which
does not create the extra class and doesn't generate the warning.

It may be the case that this generates extra classes which just don't
lead to a warning? Or in other words, would we then have Params types
with weird, internal names generated by six? Hopefully not, but that may
be preferable to the annoying warnings, especially when running tests
which run gem5 many times.

Change-Id: I9395cde3fc95126c0a0c4db67fc5b0c6bf2dd9ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33276
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Clear out isa_traits.hh.

Remove unused constants, move the interrupt related constants to
arch/arm/interrupts.hh, move a paging related constant to
arch/arm/pagetable.hh, and get rid of unnecessary includes.

Change-Id: Ide219f7a8515e010c1dd029db2ef22d8f614d8a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33198
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Get rid of (some) unused VAddr types.

X86 actually defines and uses a VAddr bitunion, but the ARM, MIPS and
SPARC versions are just stubs and aren't used anywhere.

Change-Id: Iea8d0c8ab04ac1d95f49458f0fc41f291751da1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33202
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

util: Fix interworking for the thumb version of the m5 util.

Make sure the m5 op call sight is marked as thumb, and also use an
interworking branch to return from it.

Change-Id: I4f6ec6a0e9e7ff76fc8f256fec9ec410a9959189
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27748
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

util: Enable neon when building arm/thumb versions of the m5 util.

Apparently the presence of a hardware FPU is no longer implied by
-march=armv7-a (or armv7 I assume), and so adding -mfpu=neon is
necessary when using hardware floating point in gcc/g++.

Change-Id: I59c5b58933fae2e4e5a747b2af128b801acc812e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27747
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Add a unit test for the "inst" call type in the m5 util.

This test does two things. First, it makes sure that the "inst" call
type detects that it's being requested in the command line arguments
correctly.

Second, it detects whether it's running in gem5 or not, really just
detecting an environment variable which tells it whether it is. If it
is, then it attempts to run the "sum" op which it expects to succeed and
give the right answer.

If not, it expects to get a SIGILL signal from the OS when it tries to
execute the otherwise illegal instruction. It sets up a signal handler
to catch it, and in that handler saves off information about what
happened. It then uses siglongjmp to return to sanity (before the
signal) and to examine what happened to see if the right instruction was
attempted.

It looks like, depending on the architecture, Linux will either set
si_code to ILL_ILLOPC (illegal opcode) or ILL_ILLOPN (illegal operand).
The later doesn't seem right since the entire instruction is illegal,
not just some operand, but it is what it is and we need to handle
either.

The test then calls a small function, abi_verify, which takes the
siginfo_t and does any abi specific verification. That includes
extracting fields from the instruction if the instruction trigger the
signal, or checking for architecture specific constants, etc.

Also, to centralize setting the macro which lets a call type know that
it's the default, the call types are now also responsible for setting up
their own tweaks to the environment.

Change-Id: I8710e39e20bd9c03b1375a2dccefb27bd6fe0c10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27689
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

test,arch-riscv: Removed the RISCV Insttests

These tests verify RISCV instructions. This is already one by the
asmtests:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/tests/gem5/asmtest/tests.py

The asmtests do this better.

Furthermore, the insttests have some bugs associated with them, which
would require some engineering effort fix:
https://gem5.atlassian.net/browse/GEM5-729
https://gem5.atlassian.net/browse/GEM5-748
https://gem5.atlassian.net/browse/GEM5-749

This patch removes the RISCV insttests.

Change-Id: I9ee3c88d06778823f655ef9222071beb57c6c995
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33147
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Create Compressor namespace

Creation of the Compressor namespace. It encapsulates all the cache
compressors, and other classes used by them.

The following classes have been renamed:
BaseCacheCompressor -> Base
PerfectCompressor - Perfect
RepeatedQwordsCompressor -> RepeatedQwords
ZeroCompressor -> Zero

BaseDictionaryCompressor and DictionaryCompressor were not renamed
because the there is a high probability that users may want to
create a Dictionary class that encompasses the dictionary contained
by these compressors.

To apply this patch one must force recompilation (e.g., by deleting
it) of build/<arch>/params/BaseCache.hh (and any other files that
were previously using these compressors).

Change-Id: I78cb3b6fb8e3e50a52a04268e0e08dd664d81230
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33294
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Remove unused or misplaced values from isa_traits.hh.

Most of these values were unused, except the interrupt levels which were
moved to the interrupt controller, the only place they were used.
Unnecessary includes were also removed.

Change-Id: I783966413d51391663a9217ed672ec1f2b4719b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33197
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu,sim: Get rid of the microcode ROM stub code.

This code, including a switching header file, is no longer necessary
because ROM based microops are now handled by the decoder itself.

Change-Id: Ie3ea4a7371dec22993ede80e2acd1df7cd1ecf59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32899
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,arch: Delegate fetching ROM microops to the decoder.

In most cases, the microcode ROM doesn't actually do anything. The
structural existence of a microcode ROM doesn't make sense in the
general case, and in architectures that know they have one and need to
interact with it, they can cast their decoder into an arch specific type
and access the ROM that way.

Change-Id: I25b67bfe65df1fdb84eb5bc894cfcb83da1ce64b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32898
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Use default initializers to simplify the decoder constructor.

Change-Id: I76f1fe9a58a26f26c204cb0b9bab050a22d289c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Remove unnecessary includes from isa_traits.hh.

These includes are not used in this header file, and if they're needed
by other source it should include them directly.

Change-Id: I7d17d7c7fcc1020d85f1257059d2c2057b0c461d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33196
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Style fixes in the base Fault classes.

Change-Id: Iff8588aba929b3909ca1b5ec0e494acb8f838543
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33280
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

x86: Style fixes in x86's fault implementations.

Change-Id: I320877a7e753eae5ffba2421e6dfe23b52352664
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33279
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

x86: Replace "is not" with "!=" in fpop.isa.

Some variables were being compared against some constants with "is not",
which is not correct since it will compare for identity rather than
equivalence. There was a long standing build warning from this, but it
wasn't clear where the error was coming from since it was in python
interpreted from a string in the ISA description.

This change replaces "is not" in those two places with "!=".

Change-Id: I0c4d038af6e047ffd79f8171713e8e998e840e3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33283
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Replace some includes of arch/isa_traits.hh.

In sim/vma.hh, the include was indirectly getting the definition of
DPRINTF. It was replaced with an include of base/trace.hh which actually
provides that definition.

In the indirect branch predictor, it was being used to get the
definition of TheISA::PCState. This should come from arch/types.hh
instead.

Change-Id: I6de08f196499c85b54edde09d654902cc766c2eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Added .txt file extension to txt files

This is a small improvement. In our Jenkins, https://jenkins.gem5.org,
we archive the `compile-test-out` directory. Opening these `*.stderr`
and `*.stdout` files through the Jenkins interface was problematic. The
`.txt` extension makes these files easier to open.

Change-Id: I4026efec2118179eaed775c7560510cd16f349a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32154
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Added exit code to the compiler tests

This testing script should return a non-exit code when one of the
compilations fail.

Change-Id: Ie15bc5779372dd31d784eaffdee4b04abb9a1b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32097
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Removed GCC 4.8 from compilers tests

We are going to remove support of GCC 4
(https://gem5.atlassian.net/browse/GEM5-218) as part of the gem5 20.1
release.

Change-Id: Ie44b553d35f48118d24b96eba564a927fefdb985
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32096
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv, arch-x86: convert tlb to new style stats

Change-Id: Ie2754d861a658fde0acdda30cbcb91e02029e33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32835
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips, arch-power: removed unused stats

Change-Id: Ic44943eaefab027d6dc665e531f827202b353093
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32834
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86,cpu: Fix bpred by annotating branch instructions in x86

Original Creator: Adria Armejach.

Branch instructions needed to be annotated in x86 as direct/indirect and conditional/unconditional. These annotations where not present causing the branch predictor to misbehave, not using the BTB. In addition, logic to determine the real branch target at decode needed to be added as it was also missing.

Change-Id: I91e707452c1825b9bb4ae75c3f599da489ae5b9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29154
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Removed m5threads tests from .testignore

This commit fixes many problems which were resulting in these tests
not executing correctly. However, the m5thread tests are still failing
with an `fatal:syscall set_tid_address (#166) unimplemented` error,
recorded here: https://gem5.atlassian.net/browse/GEM5-747.

The tests have been removed from .testignore as part of our goal of
removing all tests from the .testignore file:
https://gem5.atlassian.net/browse/GEM5-361

Change-Id: I287d1e126963114a791d7f3aa563a037a89b2cb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32916
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added tests/gem5/resources to .gitignore

This is simply a directory used by testlib to store downloaded
resources. It should therefore be ignored.

Change-Id: Iede2234dc512b3bc8bdcccfaef0b14d56dee0a27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32915
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Removed the hello tests from .testignore

The "hello" tests that were previously ignored are all functioning
correctly, and are therefore being re-included in the test suite. The
MIPS and SPARC tests have been tagged a "long" as we do not compile
these ISAs are part of our "quick" tests.

Change-Id: I3aa079b81b938a12da6993213d158e53bc4ae514
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32914
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Delete the critical path annotation code.

This code was at least a little Alpha specific, and now that Alpha is
gone it can no longer be compiled. We could either fix it up to work
with other/all ISAs or delete it, and the consensus was to delete it. It
could potentially be revived in the future by retrieving it from version
control.

Change-Id: Ied073f2b9b166951ecba3442cd762eb19bc690b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32954
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Use getGuestByteOrder in the indirect memory prefetcher.

Use that instead of accessing TheISA::GuestByteOrder directly.

Change-Id: I6fbeb7501aceadb95739bb482215097af18da2fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32926
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Add float registers in copyRegs

The origin copyRegs() does not include float registers.
This patch fixes the problem.

Change-Id: If4ad04b1eda6035486197879ff3e04ff32dd87bb
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32934
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Eliminate the unused HasUnalignedMemAcc constant.

Change-Id: Iaf9346df57336216c09979fe1d931701c6b7ddf6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32923
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Eliminate an unused pair of constants from isa_traits.hh.

The one questionable use of CurThreadInfoImplemented (always false) and
CurThreadInfoReg (always -1) has been eliminated, making these constants
unnecessary.

Change-Id: Ibfe4f7be7ce5aaf9c5e896146e1b05b3ac752305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32922
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Make ThreadInfo::curThreadInfo virtual, protected.

Also remove it's Alpha centric implementation. All existing ISAs will
panic since they all define the guarding constant as false. Even if they
defined it as true, this function assumes that there is necessarily a misc
reg which can be read to find the current thread_info struct, and how
the contents of that register should be manipulated.

This code is already fairly fragile since it depends on things in the
Linux kernel having certain names and relationships with each other, but
that's a larger problem I don't want to fix right now.

Change-Id: Ic107793ebcd25ee25c4d3713c84c1d2b5209f1a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32921
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Replace getDoubleBits with floatToBits64.

The getDoubleBits function was used exactly once to find the bit
representation of a double floating point value, which is the same thing
the common floatToBits64 function does. Eliminate x86's one off version,
and use the common one instead.

Change-Id: Icb0cec5a55d81a6eacf1bb5a3c2b8f16c414d0d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32927
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Use the System object's getGuestByteOrder in AbstractMemory.

Change-Id: Ifcf3d8dcbee73555b23ec0a8c25572921fca13a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32925
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Remove the "inline" keyword in ThreadInfo.

Methods which are defined inline are already implicitly inline, making
that keyword redundant. It's also inconsistently used.

Change-Id: If6ec3e94d126ae52d9c2f0d3e8ca27f1ac600650
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32920
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix some style issues in the microcode ROM class.

Change-Id: I64fb5efbc9f63298c103816503f4718308032eb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32896
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Style fix in the decoder class.

Change-Id: If06a8771b5db0fb68e88b16dedfe60fc2ce306d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32894
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Get the byte order from sys and not TheISA::.

This is a small step which localizes the use of TheISA, hopefully making
it easier to eliminate in the future.

Change-Id: I13472ed69e12a3c753e2dea91b9c7ca813bfc0e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

kern: Stop using TheISA::GuestByteOrder in Linux::dumpDmesg.

This value is already read from the system object in that same function.
We should use that instead of getting the value ourselves.

Change-Id: I0a442cd4892f50ad0179884bebf3eb52881c022f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32924
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Don't add contents to the TheISA namespace in arch/generic.

Instead, add what you want other ISAs to be able to use to a generic,
fixed namespace, and then let those other ISAs bring those symbols in
with "using" if they want them.

Change-Id: I15bfaf56e76ffdc3bdb603deef4ad471211f4f24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32929
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,arm: Stop using TheISA in ARM specific files.

These can use ArmISA since there's no ambiguity about what ISA is being
used with those files.

Change-Id: I02e8ea0ab70215679eb939adaa949400e878b1ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32928
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Fix a small style issue in Linux::ThreadInfo.

Change-Id: I7f6f938f9412e535df0cbc0687ec9f2de2dbf8e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32918
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Don't construct and then copy the decoder in SimpleThread.

The SimpleThread constructor was constructing a temporary copy of the
decoder, and then copying it into it's local version. This copy is a
waste, and also requires there to be a copy operator for the Decoder.

Change-Id: I1123b4ec767e08ceb2f108b3a6b19ca18d7c677c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32900
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Create a base class for decoders.

This base class doesn't actually hold anything yet, it's just a place to
add shared functionality or interfaces later.

Change-Id: Ia33217bd78b1d1ff3df3b2202095576a4e5d8153
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32897
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Replace scalar TypedBufferArg with VPtr.

Change-Id: Ic8460ad133e3512c103b14820d90ee3df987d78d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31755
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

arch-riscv: Fix disassembling of CSR instructions

The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm

This patch fixes the problem.

Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,gpu-compute,mem-ruby: connect gmTokenPorts in apu_se

This patch adds gmTokenPorts to the ComputeUnit and RubyGPUCoalescer
python classes so the gmTokenPorts can be connected in apu_se.

Change-Id: Icf3cb05c757754d6935b46f14e4b1b1d5072c4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32677
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Rename CallbackQueue2 to CallbackQueue.

Now that the original CallbackQueue has been removed, CallbackQueue2 can
fully take it's place.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I925f647cbbd393045a22f7cbd5d8b4d7d23d19b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32651
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Get rid the Callback type.

This leaves only the lambda/std::function based CallbackQueue2, soon to
be renamed just CallbackQueue.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I4e2fd3b7b684c414be6db0e268284ab63e6cfdff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32650
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Replace Callback in the virtio device with a lambda.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Ia628ceb0080b11b81c7eee82e7c8c0049b2cd62f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32649
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Replace the Callback class with lambdas in ARM's flash devices.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I2694dd1952b7412c27c83c9d15d4645899bd28e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32648
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Use lambdas instead of the Callback type for serial devices.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Idb87fa0b90d14981fd61f997285f61b2ef304227
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32647
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Delete the unused PowerStateDumpCallback.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I8e66f31a3a6a82564d9525021ada49ce52beb1fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32646
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Make the stats callbacks use CallbackQueue2.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Idcbe04bdf4299925f321aa0ece263d86ed3fc8df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32645
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add import for FileSystemConfig in GPU_VIPER.py

GPU_VIPER.py uses FileSystemConfig to register CPUs and caches in SE
mode. Without the import, it crashes.

Change-Id: I539a4060d705f6e1b9a12aca7836eca271f61557
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32675
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Replace DirMem w/RubyDirectoryMemory, set addr_ranges

This was originally from the GCN staging branch, which only had
GPU_VIPER.py, but the other GPU_VIPER configs had DirMem as well, so I
applied this change to all of them.

The patch replaces the Directory in DirCntrl from DirMem to
RubyDirectoryMemory. This fixes errors that DirMem caused relating to
setting class variables. It also generates and sets addr_ranges in
DirCntrl as RubyDirectoryMemory uses the parent object's addr_ranges
in its code

The style checker complained about a line length in GPU_VIPER_Region,
so the patch also fixes that

Change-Id: Icec96777a51d8a826b576fc752fae0f7f15427bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32674
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: convert tlb to new style stats

Change-Id: I2a3f138b53496be6361a1a2b81fa471a56a4dc10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32794
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Early checking if debug is enabled in TLB

The patch is aiming at speeding up gem5 execution.  The TLB::translateFs
is in the critical path of the simulator: every fetch + ld/st will make
use of it.
Checking all the time for a breakpoint during fetch is rather expensive;
it is better to make use of the cached booleans in SelfDebug to do an
early check to see if any of
Watchpoint/Breakpopint/VectorCatch/SoftwareStep is enabled.
Most workloads won't use them so there's no point on calling the
testDebug method

Change-Id: I0189b84e0dc2e081acce04ff44787b9f1014477c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32776
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rename SelfDebug member variables

* enableFlag -> mde
The "enableFlag" variable, enabling the Breakpoint, Watchpoint, Vector
Catch exceptions is actually the cached version of MDSCR_EL1.MDE. The
"enableFlag" name looks too general as it's not covering the Software
Step exception case.

* bKDE -> kde
* bSDD -> sdd

The b prefix was likely referring to "breakpoint". However these bitfields
are actually used by watchpoints as well.

Change-Id: I48b762b32b2d763f4c4ceb7dcc28968cfb470fc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32775
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

arch-arm: Remove setters from SoftwareStep

Motivation:
Those helpers are used and meant to be used by the parent
(SelfDebug) class only. There is no point on exposing them to
the outer world. Better to make SelfDebug a friend class and to
allow it to access children's private data.

Change-Id: Ib945b1aa46742b90062ce7a5de563f164127075f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32774
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Make registerExitCallback use CallbackQueue2.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I526d4a19ca4e54a6469a4ee26693c1c0400fcc70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32644
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Use the new type of CallbackQueue in the MemBackdoor.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Ide40528f8c613b46204550d6e6840a7b274a366a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32643
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add a new type of CallbackQueue.

This type is templated on what arguments the callbacks in it accept, and
it inherits directly from std::list instead of containing one and
forwarding selected members.

This version is called CallbackQueue2, but once all CallbackQueue
instances have been replaced it will be renamed to CallbackQueue.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I32ab7454ea8c6a2af31cbcf5d4932a069ace1cb5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32642
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling of all register instructions

How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.

This patch fixes the problem.

Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: convert table_walker to new style stats

Change-Id: I347a72d33e3d0eb9f60ac01dfa2cc82bdbae3cbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32494
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache,python: Allow custom TLB and events in each prefetcher.

The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object.  This change redefines them as instance members to fix the
problem.

Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32394
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

util,systemc: Update the stats API used in one of the examples.

A new parameter as added to the initText method in March of this year,
but this example code was not updated which prevents it from compiling.

This change adds the parameter to the call and sets it to what the
documenting comments say is the default, true.

Change-Id: Ic8da46dba03f01f338c38a7bc02ba232a90ae349
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32641
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,systemc: Update the gem5-within-systemc TLM example code.

Some class names within gem5 changed in March of last year, and this
code was not updated to match. Change ExternalMaster::Port to
ExternalMaster::ExternalPort, and ExternalSlave::Port to
ExternalSlave::ExternalPort.

Change-Id: I04c0970c4107de3449473c24c7c6f99ada72bbb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32640
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add Xen compilation to gen_arm_fs_files.py

Change-Id: I61014d9686f0362ebb83dca5d4d33ac08d66d0a7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32557
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Remove dependency check

The list is rather old and it contains some entries which are likely
unneeded. Since we are also now able to select specific FS binaries
to be compiled individually, there is not point of requiring all
components to be installed.
Instead, if is better to rely on the error message of building process
and let the users figure out which packages they need to install

Change-Id: I16c74861cb1f2b09c3e91e408ace01a9bd7a234d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32556
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Allow the short -j option in gen_arm_fs_files.py

Change-Id: I15c3bad13882cd38683b7c733311191e1f51d13f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Change gen_arm_fs_files.py to allow selective compilation

With the -b/--fs-binaries option it is possible to specify a list
of fs binaries to be fetched/compiled.

Change-Id: I12a642f65b74e8606c82cdddcbc3a8172bad2381
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32554
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Dropped the i386 host tag in tests

Issue-on: https://gem5.atlassian.net/browse/GEM5-532
Change-Id: Ifee50d59c65f8b460248508688232d9253c040b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32596
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Use isSecure variable for Stage2Lookup

TLB entries are tagged with the security state of the cpu instead
of the security attribute of the physical address

Change-Id: I728ba1c841de1ec6c1ee03aee012b185c968d078
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32639
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix physmem NS attribute in VMSAv8-32 descriptors

The NS field in PTEs descriptors is tagging Secure/Non-secure physical
memory (pages). This field is relevant in Secure state only:

While in Secure state, software can access both the Secure and
Non-secure physical address spaces, software in Non-secure state can
only access Non-secure memory; the NS bit is hence discarded/treated as
1.

This patch is aligning VMSAv8-32 with VMSAv8-64, which is tagging the
pointed memory as Non-secure in case of a Non-secure lookup.

The old behaviour was probably not leading to incorrect execution:
once a translation completes, the security flag in the memory request
is chcked against the security state of the cpu (and not only relying
on the NS bit in the TLB entry)

if (isSecure && !te->ns) {
    req->setFlags(Request::SECURE);
}

so we were already forbidding secure accesses from non secure world
if NS = 0.

It is however misleading in the debug logs to see tlb entries with
NSTID = 1 and NS = 0.

Change-Id: I1f964069f88c33fb14362dd4101cb22538907226
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32638
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: VSTTBR_EL2 doesn't contain a VMID field

Change-Id: Ia6e14b509d7016020af9c85941e7b2d89dcdd359
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32637
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Disable HVC when SCR_EL3.HCE is 0

This was already implemented for AArch32 but it had been wrongly
removed by:

https://gem5-review.googlesource.com/c/public/gem5/+/31394

Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32636
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix XN in TLB permissions

The SIF condition check should be logically ORed with the TLB
entry XN attribute, instead of overriding it.

Change-Id: I70b38d97bbdc82b9f385d40ad06546785fc2c5bb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32635
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix SoftwareStep::debugExceptionReturnSS

debugExceptionReturnSS is called on an ERET instruction to
check for software step. The method was not using the
SPSR.width and it was relying on the more generic ELIs32 to
check the execution mode of the destination EL.

This is not only an efficiency problem: the helper might not work
when returning to EL0. In general it is not possible to
understand if EL0 is using AArch32 or AArch64 if the current
EL is not EL0 and EL1 is using AArch64.

This is instead visible by inspecting the spsr.width during the
execution of an ERET instruction

Change-Id: Ibc5a43633d0020139f2c0e372959a3ab4880da6e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32634
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use proper keywordargs for RedirectPath in apu_se

RedirectPath uses app_path and host_paths instead of src and dests.
This patch fixes that in apu_se.

The patch also changes the formatting for those lines, as simply
replacing dests with host_paths put the lines over the 80 char limit.

Change-Id: If7e4c41f2f52bc3d5aa26465c786294f9b68f8d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32655
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove unneeded variable assignments in apu_se

This patch removes:
A line assigning a variable to itself

An assignment to a variable (chroot) that is never used.
The above assignment also caused an error, "'NoneType' object
has no attribute 'startswith'"

Change-Id: Ib93c25fee4a0f7c1440de8067b086d8b96614796
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32654
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove remnants of /dev/shm mapping from apu_se

This patch removes a redirect for /dev/shm. It also removes
a function call that cleaned up the /dev/shm redirect

Change-Id: Iec2598c715223d079bc5dfd2ea52859945706cfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32354
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add build dependency to gcn Dockerfile

src/base/pngwriter.cc requires libpng-dev

Change-Id: I7f009cd8f5cacd64150c06b716b1ce3008832910
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32474
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

mem-ruby: Fix debug prints for regular Stores

In the updated implementation of LL/SC (27103) the default value
of success was changed, which results in printing "SC_Failed" for
any regular stores.

Change-Id: I4f2e0b26233ce0cbdf948aadd19c9d81bf18bec0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32514
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Free registers when execMask = 0

Flat instructions free some of their registers through their memory
requests, in particuar a call to scheduleWriteOperandsFromLoad(),
which gets called from GlobalMemPipeline::exec.

When execMask is 0, the instruction doesn't issue a memory request.

This patch adds in a call to scheduleWriteOperandsFromLoad() when
execMask is 0 for Flat Load and AtomicReturn instructions, as those
are the instructions that call scheduleWriteOperandsFromLoad()
in the memory pipeline.

This patch also adds in a missing return statement when execMask is 0
in one of the Flat instructions.

Change-Id: I09296adb7401e7515d3cedceb780a5df4598b109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32234
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fix races between data and DMA in MOESI_AMD_Base-dir

There are race conditions while running several benchmarks, where
the DMA engine and the CorePair simultaneously send requests for the
same block. This patch fixes two scenarios
(a) If the request from the DMA engine arrives before the one from the
CorePair, the directory controller records it as a pending request.
However, once the DMA request is serviced, the directory doesn't check
for pending requests. The CorePair, consequently, never sees a response
to its request and this results in a Deadlock.

Added call to wakeUpDependents in the transition from BDR_Pm to U
Added call to wakeUpDependents in the transition from BDW_P to U

(b) If the request from the CorePair is being serviced by the directory
and the DMA requests for the same block, this causes an invalid
transition because the current coherence doesn't take care of this
scenario.

Added transition state where the requests from DMA are added to the
stall buffer.

Updated B to U CoreUnblock transition to check all buffers, as the DMA
requests were being placed later in the stall buffer than was being checked

Change-Id: I5a76efef97723bc53cf239ea7e112f84fc874ef8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31996
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: make read2st64_b32 write proper registers

Per the GCN3 ISA, read2st64_b32 writes to consecutive registers

Change-Id: Ibc1672584a72cf7de12e06068a03fe304b34dce2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32236
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Fixing HSA's barrier bit implementation

This changeset fixes several bugs in the HSA barrier bit implementation.

1. Forces AQL packet launch to wait for completion of all previous packets
2. Enforces barrier bit blocking only if there are packets pending completion
3. Barrier bit unblocking is correclty done by the last pending packet
4. Implementing barrier bit for all packets to conform to HSA spec

Change-Id: I62ce589dff57dcde4d64054a1b6ffd962acd5eb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30354
Reviewed-by: Sooraj Puthoor <puthoorsooraj@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Install python six module in gcn dockerfile

six is used in develop, but wasn't used in the GCN staging branch.

Change-Id: Ic1ca42df871d1e683c288282497267d00421609f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32235
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Remove the stacktrace.hh switching header file.

This is no longer used.

Change-Id: I1419b28d51ff603beb7d8ab89632ad7038c3057e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32215
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-simple: Fix BaseSimpleCPU to reset group stats

BaseSimpleCPU::resetStats() should call Stats::Group::resetStats()
to reset new style hierarchy stats.

Change-Id: I932280449b29577d214db56ac8347aca4143c949
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32434
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add stub unit tests for the call types in the m5 utility.

These will be filled out in later changes. This CL just adds the
plumbing to the build script.

Change-Id: If58ea023d0c85eae0160f88217c83fca70346da2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27688
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Pull "usage()" out of the call types in the m5 utility.

Also pull common implementations of some call type methods into the base
class, and make disappearing call types clean themselves up to make the
test a little simpler and less error prone.

Change-Id: Ie178fe02d41587647ddc90a084d1d1142b84dde9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27687
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Reduce boilerplate when extracting SelfDebug from tc

Change-Id: I1746400617be64ac9c2f3194442734e178342909
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31354
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix <timer>_CTL_EL<x>.ISTATUS when masking the irq

According to the ArmArm:

"When the value of the ENABLE bit is 1, ISTATUS indicates whether the
timer condition is met.  ISTATUS takes no account of the value of the
IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then
the timer interrupt is asserted."

Since ISTATUS is simply flagging that timer conditions are met, an
interrupt mask (via the <timer>_CTL_EL<x>.IMASK) shouldn't reset the
field to 0.
Clearing the ISTATUS bit leads to the following problem
as an example:

1) virtual timer (EL1) issuing a physical interrupt to the GIC

2) hypervisor handling the physical interrupt; setting the
CNTV_CTL_EL0.IMASK to 1 before issuing the virtual interrupt
to the VM

3) The VM receives the virtual interrupt but it gets confused
since CNTV_CTL_EL0.ISTATUS is 0 (due to point 2)

What happens when we disable the timer?

"When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN."

So we are allowed to not clear the ISTATUS bit if the timer gets
disabled

Change-Id: I8eb32459a3ef6829c1910cf63815e102e2705566
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31775
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: don't wake up SE futex syscalls on ARM events

Before this commit:

* SEV events were not waking neither WFE (wrong) nor futex WAIT (correct)
* locked memory events (LLSC) due to LDXR and STXR were waking up both
  WFE (correct) and futex WAIT (wrong)

This commit fixes all wrong behaviours mentioned above.

The fact that LLSC events were waking up futexes leads to deadlocks,
as shown in the test case described at:
https://gem5.atlassian.net/browse/GEM5-537
because threads woken up by SVE are not removed from the waiter list
for the futex address they are sleeping on.

A previous fix atttempt was done at:
1531b56d605d47252dc0620bb3e755b7cf84df97
in which only sleeping threads are woken up. But that is not sufficient,
because the futex sleeping thread that was being wrongly woken up on SEV
can start to sleep on a second futex.

As an example, consider the case where 4 threads are fighting over two
critical sections protected by futex1 and futex2 addresses. In this case,
one thread wakes up the other thread after it is done with the section.

Suppose the following sequence of events:

* thread1 is awake and all others are suspended on futex1

* thread1 SEV wakes thread2 from the futex1 while in the critical region 1.

  This is the wrong behaviour that this patch prevents, because
  now thread2 is still in the sleeper list for futex1

* thread1 then futex wakes tread3, then proceeds to critical region 2.

* thread3 wakes up, but because thread2 has critical region, it sleeps
  again.

* thread2 finishes its work, futex wakes thread3, and then proceeds to
  futex2

  When it reaches futex2, thread1 is still working there, so it sleeps on
  futex2.

* thread3 futex wakes thread2, because it is still wrongly on the sleeper
  list of futex1. But thread2 is in futex2 now.

  If it weren't for this mistake, it should have awaken the final thread4
  instead.

Outcome: thread4 sleeps forever, no other thread ever wakes it, because all
other threads have woken from futex1 and awoken another thread.

The problem is fixed by adding the waitingTcs unordered_set FutexMap,
which is basically an inverse map to FutexMap, which tracks (addr,
tgid) -> ThreadContext. This allows us allow to quickly check
if a given ThreadContext is waiting on a futex in any address.

Then the SEV wakeup code path
now checks if the thread is k

Change-Id: Icec5e30b041f53e5aa3b6e0d291e77bc0e865984
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29777
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset

Both methods do basically the same, especially since they don't handle the
timeout which is basically the only difference between both modes of the
syscall (one uses absolute and the other relative time).

Remove the WaiterState::WaiterState(ThreadContext* _tc) constructor,
since the only calls were from FutexMap::suspend which does not use them
anymore. Instead, set the magic 0xffffffff constant as a parameter to
suspend_bitset.

Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29776
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: split futex_map.cc into header and source files

To speed up development when modifying the implementation.

Change-Id: I1b3c67c86f8faa38ed81a538521b08e256d21a5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29775
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips: Remove old TypeBufferArg call

TypeBufferArg was replaced by VPtr so this call is no longer needed.
This fixes the MIPS build / nightly build.

Change-Id: I3880229fa0ad87fad1ca35c136e12efc6c36ceda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32414
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add checkpoint parameters for VMA list

Add checkpoint parameters (together with corresponding serialization
and unserialization) for VMA list of class MemState into a separate
section named 'vmalist'.

Without these VMA list parameters, a page table fault will occur when
running with --restore-simpoint-checkpoint, because of an empty VMA
list. For example:

  $ ./build/RISCV/gem5.debug --debug-flags=Exec configs/example/se.py \
      -c tests/test-progs/hello/bin/riscv/linux/hello \
      --cpu-type=NonCachingSimpleCPU --restore-simpoint-checkpoint \
      --checkpoint-dir m5out/ -r 2
  ...
  2404000: system.switch_cpus: T0 : @_int_malloc+3392    : sd a5, 8(a0) \
      : MemWrite :  D=0x000000000001ed21 A=0x862e8
  panic: Page table fault when accessing virtual address 0x862e8
  ...

Example checkpoint output:

  [system.cpu.workload.vmalist]
  size=3

  [system.cpu.workload.vmalist.Vma0]
  name=stack
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma1]
  name=heap
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma2]
  ...

Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31875
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>