Nilay Vaish [Tue, 1 Sep 2015 20:50:32 +0000 (15:50 -0500)]
ruby: directory memory: drop unused variable.
Andreas Sandberg [Tue, 1 Sep 2015 14:28:45 +0000 (15:28 +0100)]
sim: Remove broken AutoSerialize support from the event queue
Event auto-serialization no longer in use and has been broken ever
since the introduction of PDES support almost two years
ago. Additionally, serializing the individual event queues is
undesirable since it exposes the thread structure of the
simulator. What this means in practice is that the number of threads
in the simulator must be the same when taking a checkpoint and when
loading the checkpoint.
This changeset removes support for the AutoSerialize event flag and
the associated serialization code.
Andreas Sandberg [Tue, 1 Sep 2015 14:28:44 +0000 (15:28 +0100)]
dev: Remove auto-serialization dependency in EtherLink
EtherLink currently uses a fire-and-forget link delay event that
delays sending of packets by a fixed number of ticks. In order to
serialize this event, it relies on the event queue's auto
serialization support. However, support for event auto serialization
has been broken for more than two years, which means that checkpoints
of multi-system setups are likely to drop in-flight packets.
This changeset the replaces rewrites this part of the EtherLink to use
a packet queue instead. The queue contains a (tick, packet) tuple. The
tick indicates when the packet will be ready. Instead of relying on
event autoserialization, we now explicitly serialize the packet queue
in the EhterLink::Link class.
Note that this changeset changes the way in-flight packages are
serialized. Old checkpoints will still load, but in-flight packets
will be dropped (just as before). There has been no attempt to upgrade
checkpoints since this would actually change the behavior of existing
checkpoints.
Andreas Sandberg [Tue, 1 Sep 2015 12:41:45 +0000 (13:41 +0100)]
sim: Remove autoserialize support for exit events
This changeset removes the support for the autoserialize parameter in
GlobalSimLoopExitEvent (including exitSimLoop()) and
LocalSimLoopExitEvent.
Auto-serialization of the LocalSimLoopExitEvent was never used, so
this is not expected to affect anything. However, it was sometimes
used for GlobalSimLoopExitEvent. Unfortunately, serialization of
global events has never been supported, so checkpoints with such
events will currently cause simulation panics.
The serialize parameter to exitSimLoop() has been left in-place to
maintain API compatibility (removing it would affect m5ops). Instead
of just dropping it, we now print a warning if the parameter is set
and the exit event is scheduled in the future (i.e., not at the
current tick).
Andreas Sandberg [Tue, 1 Sep 2015 12:40:28 +0000 (13:40 +0100)]
sim: Remove unused SerializeBuilder interface
Andreas Sandberg [Tue, 1 Sep 2015 12:40:25 +0000 (13:40 +0100)]
sim: Replace fromInt/fromSimObject with decltype
Andreas Sandberg [Tue, 1 Sep 2015 12:40:05 +0000 (13:40 +0100)]
sim: Move SimObject resolver to sim_object.hh
The object resolver isn't serialization specific and shouldn't live in
serialize.hh. Move it to sim_object.hh since it queries to the
SimObject hierarchy.
Nilay Vaish [Sun, 30 Aug 2015 17:24:19 +0000 (12:24 -0500)]
stats: updates due to recent changes.
Nilay Vaish [Sun, 30 Aug 2015 17:24:18 +0000 (12:24 -0500)]
ruby: specify number of vnets for each protocol
The default value for number of virtual networks is being removed. Each protocol
should now specify the value it needs.
Nilay Vaish [Sun, 30 Aug 2015 17:24:18 +0000 (12:24 -0500)]
ruby: network: drop member m_in_use
This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.
Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.
Nilay Vaish [Sun, 30 Aug 2015 17:24:18 +0000 (12:24 -0500)]
ruby: garnet: mark few functions const in BaseGarnetNetwork.hh
Nilay Vaish [Sun, 30 Aug 2015 15:52:58 +0000 (10:52 -0500)]
ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.
Nilay Vaish [Sat, 29 Aug 2015 15:19:23 +0000 (10:19 -0500)]
ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.
Andreas Sandberg [Fri, 28 Aug 2015 09:58:44 +0000 (10:58 +0100)]
ruby: Use the const serialize interface in RubySystem
The new serialization code (kudos to Tim Jones) moves all of the state
mangling in RubySystem to memWriteback. This makes it possible to use
the new const serialization interface.
This changeset moves the cache recorder cleanup from the checkpoint()
method to drainResume() to make checkpointing truly constant and
updates the checkpointing code to use the new interface.
Nilay Vaish [Thu, 27 Aug 2015 17:51:40 +0000 (12:51 -0500)]
ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.
Emilio Castillo [Wed, 26 Aug 2015 19:20:30 +0000 (14:20 -0500)]
cpu: quiesce pseudoinsts: Always do full quiesce
The O3CPU blocks the Fetch when it sees a quiesce instruction (IsQuiesce flag).
When the inst. is executed, a quiesce event is created to reactivate the
context and unblock the Fetch.
If the quiesceNs or quiesceCycles are called with a value of 0, the
QuiesceEvent will not be created and the Fetch stage will remain blocked.
Committed by Joel Hestness <jthestness@gmail.com>
Andreas Hansson [Mon, 24 Aug 2015 09:03:45 +0000 (05:03 -0400)]
mem: Revert requirement on packet addr/size always valid
This patch reverts part of (
842f56345a42), as apparently there are
use-cases outside the main repository relying on the late setting of
the physical address.
Andreas Hansson [Fri, 21 Aug 2015 11:03:27 +0000 (07:03 -0400)]
mem: Reflect that packet address and size are always valid
This patch simplifies the packet, and removes the possibility of
creating a packet without a valid address and/or size. Under no
circumstances are these fields set at a later point, and thus they
really have to be provided at construction time.
The patch also fixes a case there the MinorCPU creates a packet
without a valid address and size, only to later delete it.
Andreas Hansson [Fri, 21 Aug 2015 11:03:25 +0000 (07:03 -0400)]
arm, mem: Remove unused CLEAR_LL request flag
Cleaning up dead code. The CLREX stores zero directly to
MISCREG_LOCKFLAG and so the request flag is no longer needed. The
corresponding functionality in the cache tags is also removed.
Andreas Hansson [Fri, 21 Aug 2015 11:03:24 +0000 (07:03 -0400)]
mem: Remove unused cache squash functionality
Tidying up.
Andreas Hansson [Fri, 21 Aug 2015 11:03:23 +0000 (07:03 -0400)]
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.
--HG--
rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Andreas Hansson [Fri, 21 Aug 2015 11:03:21 +0000 (07:03 -0400)]
ruby: Move Rubys cache class from Cache.py to RubyCache.py
This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.
--HG--
rename : src/mem/ruby/structures/Cache.py => src/mem/ruby/structures/RubyCache.py
Andreas Hansson [Fri, 21 Aug 2015 11:03:20 +0000 (07:03 -0400)]
mem: Move cache_impl.hh to cache.cc
There is no longer any need to keep the implementation in a header.
Andreas Hansson [Fri, 21 Aug 2015 11:03:14 +0000 (07:03 -0400)]
cpu: Move invldPid constant from Request to BaseCPU
A more natural home for this constant.
Nilay Vaish [Wed, 19 Aug 2015 15:02:01 +0000 (10:02 -0500)]
ruby: reverts to changeset:
bf82f1f7b040
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: add accessor functions to SLICC def of MachineID
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: simple network: refactor code
Drops an unused variable and marks three variables as const.
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: profiler: provide the number of vnets through ruby system
The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: directory memory: drop unused variable.
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: slicc: remove a stray line in StateMachine.py
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: garnet: flexible: refactor flit
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: DataBlock: adds a comment
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: remove random seed
We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: SubBlock: refactor code
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: cache recorder: move check on block size to RubySystem.
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: abstract controller: mark some variables as const
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: simple network: store Switch* in PerfectSwitch and Throttle
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: remove unused functionalRead() function.
Nilay Vaish [Sat, 15 Aug 2015 00:28:44 +0000 (19:28 -0500)]
ruby: perfect switch: refactor code
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer().
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: cache memory: drop {try,test}CacheAccess functions
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: adds set and way indices to AbstractCacheEntry
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: slicc: use default argument value
Before this patch, while one could declare / define a function with default
argument values, but the actual function call would require one to specify
all the arguments. This patch changes the check for function arguments.
Now a function call needs to specify arguments that are at least as much as
those with default values and at most the total number of arguments taken
as input by the function.
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.
Nilay Vaish [Sat, 15 Aug 2015 00:28:43 +0000 (19:28 -0500)]
ruby: drop the [] notation for lookup function.
This is in preparation for adding a second arugment to the lookup
function for the CacheMemory class. The change to *.sm files was made using
the following sed command:
sed -i 's/\[\([0-9A-Za-z._()]*\)\]/.lookup(\1)/' src/mem/protocol/*.sm
Nilay Vaish [Sat, 15 Aug 2015 00:28:42 +0000 (19:28 -0500)]
ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.
Nilay Vaish [Sat, 15 Aug 2015 00:26:43 +0000 (19:26 -0500)]
stats: updates to ruby fs regression test
Changes due to recent patches:
fc1e41e88fd3,
882ce080c9f7,
e8a6637afa4c, and
e6e3b7097810 by Joel Hestness.
Nilay Vaish [Fri, 14 Aug 2015 17:04:51 +0000 (12:04 -0500)]
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
Nilay Vaish [Fri, 14 Aug 2015 17:04:47 +0000 (12:04 -0500)]
ruby: rename variables Addr to addr
Avoid clash between type Addr and variable name Addr.
Joel Hestness [Fri, 14 Aug 2015 06:19:34 +0000 (01:19 -0500)]
stats: Bump for MessageBuffer, cache latency changes
Joel Hestness [Fri, 14 Aug 2015 05:19:45 +0000 (00:19 -0500)]
ruby: Protocol changes for SimObject MessageBuffers
Joel Hestness [Fri, 14 Aug 2015 05:19:44 +0000 (00:19 -0500)]
ruby: Expose MessageBuffers as SimObjects
Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)
2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.
3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.
Joel Hestness [Fri, 14 Aug 2015 05:19:39 +0000 (00:19 -0500)]
ruby: Change PerfectCacheMemory::lookup to return pointer
CacheMemory and DirectoryMemory lookup functions return pointers to entries
stored in the memory. Bring PerfectCacheMemory in line with this convention,
and clean up SLICC code generation that was in place solely to handle
references like that which was returned by PerfectCacheMemory::lookup.
Joel Hestness [Fri, 14 Aug 2015 05:19:37 +0000 (00:19 -0500)]
ruby: Remove the RubyCache/CacheMemory latency
The RubyCache (CacheMemory) latency parameter is only used for top-level caches
instantiated for Ruby coherence protocols. However, the top-level cache hit
latency is assessed by the Sequencer as accesses flow through to the cache
hierarchy. Further, protocol state machines should be enforcing these cache hit
latencies, but RubyCaches do not expose their latency to any existng state
machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter
is superfluous for all caches. This is confusing for users.
As a step toward pushing L0/L1 cache hit latency into the top-level cache
controllers, move their latencies out of the RubyCache declarations and over to
their Sequencers. Eventually, these Sequencer parameters should be exposed as
parameters to the top-level cache controllers, which should assess the latency.
NOTE: Assessing these latencies in the cache controllers will require modifying
each to eliminate instantaneous Ruby hit callbacks in transitions that finish
accesses, which is likely a large undertaking.
Nilay Vaish [Tue, 11 Aug 2015 16:39:23 +0000 (11:39 -0500)]
sim: clocked object: function for converting cycles to ticks.
Nilay Vaish [Tue, 11 Aug 2015 16:39:23 +0000 (11:39 -0500)]
ruby: drop some redundant includes
Nilay Vaish [Tue, 11 Aug 2015 16:39:23 +0000 (11:39 -0500)]
ruby: slicc: allow mathematical operations on Ticks
Andreas Sandberg [Fri, 7 Aug 2015 16:43:21 +0000 (17:43 +0100)]
sim: Flag EventQueue::getCurTick() as const
Andreas Sandberg [Fri, 7 Aug 2015 14:39:17 +0000 (15:39 +0100)]
stats: Update ARM stats to include programmable oscillators
Andreas Sandberg [Fri, 7 Aug 2015 08:59:28 +0000 (09:59 +0100)]
mem: Cleanup packet accessor methods
The Packet::get() and Packet::set() methods both have very strange
semantics. Currently, they automatically convert between the guest
system's endianness and the host system's endianness. This behavior is
usually undesired and unexpected.
This patch introduces three new method pairs to access data:
* getLE() / setLE() - Get data stored as little endian.
* getBE() / setBE() - Get data stored as big endian.
* get(ByteOrder) / set(v, ByteOrder) - Configurable endianness
For example, a little endian device that is receiving a write request
will use teh getLE() method to get the data from the packet.
The old interface will be deprecated once all existing devices have
been ported to the new interface.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:26 +0000 (09:59 +0100)]
dev: Implement a simple display timing generator
Timing generator for a pixel-based display. The timing generator is
intended for display processors driving a standard rasterized
display. The simplest possible display processor needs to derive from
this class and override the nextPixel() method to feed the display
with pixel data.
Pixels are ordered relative to the top left corner of the
display. Scan lines appear in the following order:
* Vertical Sync (starting at line 0)
* Vertical back porch
* Visible lines
* Vertical front porch
Pixel order within a scan line:
* Horizontal Sync
* Horizontal Back Porch
* Visible pixels
* Horizontal Front Porch
All events in the timing generator are automatically suspended on a
drain() request and restarted on drainResume(). This is conceptually
equivalent to clock gating when the pixel clock while the system is
draining. By gating the pixel clock, we prevent display controllers
from disturbing a memory system that is about to drain.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:25 +0000 (09:59 +0100)]
arm: Add support for programmable oscillators
Add support for oscillators that can be programmed using the RealView
/ Versatile Express configuration interface. These oscillators are
typically used for things like the pixel clock in the display
controller.
The default configurations support the oscillators from a Versatile
Express motherboard (V2M-P1) with a CoreTile Express A15x2.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:23 +0000 (09:59 +0100)]
dev: Add a simple DMA engine that can be used by devices
Add a simple DMA engine that sits behind a FIFO. This engine can be
used by devices that need to read large amounts of data (e.g., display
controllers). Most aspects of the controller, such as FIFO size,
maximum number of in-flight accesses, and maximum request sizes can be
configured.
The DMA copies blocks of data into its FIFO. Transfers are initiated
with a call to startFill() command that takes a start address and a
size. Advanced users can create a derived class that overrides the
onEndOfBlock() callback that is triggered when the last request to a
block has been issued. At this point, the DMA engine is ready to start
fetching a new block of data, potentially from a different address
range.
The DMA engine stops issuing new requests while it is draining. Care
must be taken to ensure that devices that are fed by a DMA engine are
suspended while the system is draining to avoid buffer underruns.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:22 +0000 (09:59 +0100)]
sim: Split ClockedObject to make it usable to non-SimObjects
Split ClockedObject into two classes: Clocked that provides the basic
clock functionality, and ClockedObject that inherits from Clocked and
SimObject to provide the functionality of the old ClockedObject.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:19 +0000 (09:59 +0100)]
base: Rewrite the CircleBuf to fix bugs and add serialization
The CircleBuf class has at least one bug causing it to overwrite the
wrong elements when wrapping. The current code has a lot of unused
functionality and duplicated code. This changeset replaces the old
implementation with a new version that supports serialization and
arbitrary types in the buffer (not just char).
Andreas Sandberg [Fri, 7 Aug 2015 08:59:15 +0000 (09:59 +0100)]
dev, x86: Fix serialization bug in the i8042 device
The i8042 device drops the contents of a PS2 device's buffer when
serializing, which results in corrupted PS2 state when continuing
simulation after a checkpoint. This changeset fixes this bug and
transitions the i8042 model to use the new serialization API that
requires the serialize() method to be const.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:14 +0000 (09:59 +0100)]
dev: Make serialization in Sinic constant
This changeset transitions the Sinic device to the new serialization
framework that requires the serialization method to be constant.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:13 +0000 (09:59 +0100)]
base: Declare a type for context IDs
Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:12 +0000 (09:59 +0100)]
base: Use constexpr in Cycles
Declare the constructor and all of the operators that don't change the
state of a Cycles instance as constexpr. This makes it possible to use
Cycles as a static constant and allows the compiler to evaulate simple
expressions at compile time. An unfortunate side-effect of this is
that we cannot use assertions since C++11 doesn't support them in
constexpr functions. As a workaround, we throw an invalid_argument
exception when the assert would have triggered. A nice side-effect of
this is that the compiler will evaluate the "assertion" at compile
time when an expression involving Cycles can be statically evaluated.
Andreas Hansson [Fri, 7 Aug 2015 08:55:38 +0000 (04:55 -0400)]
mem: Remove extraneous acquire/release flags and attributes
This patch removes the extraneous flags and attributes from the
request and packet, and simply leaves the new commands. The change
introduced when adding acquire/release breaks all compatibility with
existing traces, and there is really no need for any new flags and
attributes. The commands should be sufficient.
This patch fixes packet tracing (urgent), and also removes the
unnecessary complexity.
Andreas Sandberg [Wed, 5 Aug 2015 09:27:11 +0000 (10:27 +0100)]
sim: Fixup comments and constness in draining infrastructure
Fix comments that got outdated by the draining rewrite. Also fixup
constness for methods in the querying drain state in the DrainManager.
Andreas Sandberg [Wed, 5 Aug 2015 09:12:12 +0000 (10:12 +0100)]
mem: Fixup incorrect include guards
--HG--
extra : rebase_source :
9dba84eaf9c734a114ecd0940e1d505303644064
Andreas Hansson [Wed, 5 Aug 2015 08:36:31 +0000 (04:36 -0400)]
util: Enable DRAM sweep to print power and efficiency
This patch enhances the functionality of the DRAM sweep script to not
only plot the bandwidth utilisation, but also total power and power
efficiency. To do so, a command-line switch is added, and a bit more
data extracted from the stats.
Andreas Hansson [Wed, 5 Aug 2015 08:36:29 +0000 (04:36 -0400)]
stats: Reflect current behaviour
Not sure what went wrong in the pushing of the Ruby patches, but
somehow these regressions are not updated.
Andreas Sandberg [Tue, 4 Aug 2015 09:31:37 +0000 (10:31 +0100)]
sim: Initialize Drainable::_drainState to the system's state
It is sometimes desirable to be able to instantiate Drainable objects
when the simulator isn't in the Running state. Currently, we always
initialize Drainable objects to the Running state. However, this
confuses many of the sanity checks in the base class since objects
aren't expected to be in the Running state if the system is in the
Draining or Drained state.
Instead of always initializing the state variable in Drainable to
DrainState::Running, initialize it to the state the DrainManager is
in.
Note: This means an object can be created in the Draining/Drained
state without first calling drain().
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
stats: Update stats for tgen to reflect CommMonitor changes
The name of the stack distance stats changed slightly when the stack
distance calculator was redesigned as a probe. Update the reference
stats to reflect this.
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
mem: Move trace functionality from the CommMonitor to a probe
This changeset moves the access trace functionality from the
CommMonitor into a separate probe. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.
This patch moves the dependency on Google's Protocol Buffers library
from the CommMonitor to the MemTraceProbe, which means that the
CommMonitor (including stack distance profiling) no long depends on
it.
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
mem: Redesign the stack distance calculator as a probe
This changeset removes the stack distance calculator hooks from the
CommMonitor class and implements a stack distance calculator as a
memory system probe instead. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
mem: Add probe support to the CommMonitor
This changeset adds a standardized probe point type to monitor packets
in the memory system and adds two probe points to the CommMonitor
class. These probe points enable monitoring of successfully delivered
requests and successfully delivered responses.
Memory system probe listeners should use the BaseMemProbe base class
to provide a unified configuration interface and reuse listener
registration code. Unlike the ProbeListenerObject class, the
BaseMemProbe allows objects to be wired to multiple ProbeManager
instances as long as they use the same probe point name.
Matthias Jung [Tue, 4 Aug 2015 04:08:40 +0000 (23:08 -0500)]
misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.
Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension. For event
handling single events are now created.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Timothy Jones [Tue, 4 Aug 2015 04:08:40 +0000 (23:08 -0500)]
sim: function for testing for auto deletion
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Timothy Jones [Tue, 4 Aug 2015 04:08:40 +0000 (23:08 -0500)]
uby: Fix checkpointing and restore
There are 2 problems with the existing checkpoint and restore code in ruby.
The first is that when the event queue is altered by ruby during serialization,
some events that are currently scheduled cannot be found (e.g. the event to
stop simulation that always lives on the queue), causing a panic.
The second is that ruby is sometimes serialized after the memory system,
meaning that the dirty data in its cache is flushed back to memory too late
and so isn't included in the checkpoint.
These are fixed by implementing memory writeback in ruby, using the same
technique of hijacking the event queue, but first descheduling all events that
are currently on it. They are saved, along with their scheduled time, so that
the event queue can be faithfully reconstructed after writeback has finished.
Events with the AutoDelete flag set will delete themselves when they
are descheduled, causing an error when attempting to schedule them again.
This is fixed by simply not recording them when taking them off the queue.
Writeback is still implemented using flushing, so the cache recorder object,
that is created to generate the trace and manage flushing, is kept
around and used during serialization to write the trace to disk.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Tue, 4 Aug 2015 03:44:29 +0000 (22:44 -0500)]
ruby: mesi three level: multiple corrections to the protocol
1. Eliminate state NP in L0 and L1 Caches: The two states 'NP' and 'I' both
mean that the cache block is not present in the cache. 'I' also means that the
cache entry has been allocated. This causes problems when we do not correctly
initialize the cache entry when it is re-used. Hence, this patch eliminates
the state NP altogether. Everytime a new block comes into the cache, a cache
entry is allocated. Everytime a block leaves, the corresponding entry is
deallocated.
2. Separate transient state for instruction fetches: purely for accouting
purposes.
3. Drop state IS_I in L1 Cache and the message type STALE_DATA: when
invalidation is received for a block in IS, the block used to be moved to IS_I.
This meant that the data that would arrive in future would be used but not
stored since the controller lost the permissions after gaining them. This
state is being dropped and now invalidation messages would not processed till
the data has arrived. This also means that STALE_DATA type is not longer
required.
Nilay Vaish [Tue, 4 Aug 2015 03:44:28 +0000 (22:44 -0500)]
ruby: mesi two,three level: copy data only when dirty
The level 2 controller has a bug. In one particular action, the data block was
copied from a message irrespective whether the block is dirty or not. In cases
when L1 sends no data, the data value copied was incorrect.
Nilay Vaish [Tue, 4 Aug 2015 03:44:27 +0000 (22:44 -0500)]
ruby: correctly number the sequencer in MESI_Three_Level.py
Brad Beckmann [Sat, 1 Aug 2015 16:59:47 +0000 (12:59 -0400)]
ruby: removed invalid assert in message comparitor
It is perfectly valid to compare the same message and the greater than
operator should work correctly.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: improved stall and wait debugging
Added dprintfs and asserts for identifying stall and wait bugs.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: fix error in conflicing symbol declaration
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: enable overloading in functions not in classes
For many years the slicc symbol table has supported overloaded functions in
external classes. This patch extends that support to functions that are not
part of classes (a.k.a. no parent). For example, this support allows slicc
to understand that mapAddressToRange is overloaded and the NodeID is an
optional parameter.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: change router pipeline stages to 2
This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: change advance_stage for flit_d
Sets m_stage.second to the second parameter of the function.
Then, for every place where advance_stage is called, adds
a cycle to the argument being passed.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: improved stalling support in protocols
Adds features to allow protocols to reschedule controllers when conditionally
stalling within inport logic or actions. Also insures that resource and
protocol stalls are re-evaluated the next cycle.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: expose access permission to replacement policies
This patch adds support that allows the replacement policy to identify each
cache block's access permission. This information can be useful when making
replacement decisions.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: adds size and empty apis to the msg buffer stallmap
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: fix deadlock bug in banked array resource checks
The Ruby banked array resource checks (initiated from SLICC) did a check and
allocate at the same time. If a transition needs more than one resource, then
it might check/allocate resource #1, then fail to get resource #2. Another
transition might then try to get the same resources, but in reverse order.
Deadlock.
This patch separates resource checking and resource reservation into two
steps to avoid deadlock.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: Fix for stallAndWait bug
It was previously possible for a stalled message to be reordered after an
incomming message. This patch ensures that any stalled message stays in its
original request order.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
config: add base class for ruby controllers
The CntrlBase python class handles configuration parameters such as running
counts of controllers and sequencers.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: add request types for acquire and release
Add support for acquire and release requests. These synchronization operations
are commonly supported by several modern instruction sets.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: allocate a block in CacheMemory without updating LRU state