python: Make meta class declarations Python 3 safe

Python 2.x and Python 3 use different meta class syntax. Fix this by
implementing meta classes using the add_metaclass decorator in the six
Python library.

Due to the way meta classes are implemented in six,
MetaParamValue.__new__ seems to be called twice for some classes. This
triggers an assertion which when param that checks that Param types
have only been registered once. I have turned this assertion into a
warning.

The assertion was triggered in params.CheckedInt and params.Enum. It
seems like the cause of the issue is that these classes have their own
meta classes (CheckedIntType and MetaEnum) that inherit from
MetaParamValue and a base class (ParamValue) that also inherits from
MetaParamValue.

Change-Id: I5dea08bf0558cfca57897a124cb131c78114e59e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26083
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Change some default values in the Request class.

These values are more abnormal than the 0s they replace, and so it
would be more obvious when something is accidentally left
uninitialized.

Change-Id: Ie7f14abe9e22f9df1ff238f29d4a783c890f4a20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26237
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch: Remove the "process.hh" switching header file.

This file is not included anywhere in gem5.

Change-Id: I936ac482b9b1d527f141267d0dfb86dda3de34df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26235
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Fix relative import in non-package in configs

Fix "ValueError: Attempted relative import in non-package"

Python "compilation" fails when running, among other configs:
    ./build/X86/gem5.fast ./configs/example/ruby_random_test.py

The files in the configs/folder_name folder that are not named
"folder_name.py" are not packages, and thus Python does not allow
relative imports in them.

This fixes the bug reported in
    https://gem5.atlassian.net/projects/GEM5/issues/GEM5-188

Change-Id: Ic8befc30e4cff1d6e8d2f5db1b7f9b89b0fc1395
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24163
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base,cpu,sim: Stop including arch/vtophys.hh when not using vtophys.

These #includes are leftovers from when vtophys was used much more
prevalently in the simulator.

Change-Id: Ib2e947bc95f1e21acc9eff8e856f38b31d3fd933
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26225
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Get rid of unused/unimplemented vtophys variants.

The version of vtophys which didn't take a ThreadContext had only been
implemented on Alpha which has since been removed, so this version of
the function was completely unimplemented and never used.

This change also gets rid of the dbg_vtophys which was sometimes
implemented but also never used, and takes the opportunity to fix up
some style problems in some of the vtophys arch files.

Change-Id: Ie10f881f8ce08c7188e71805357cf3264be4c81a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26224
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Implement translateFunctional in the TLB class.

This is a slightly munged version of vtophys, but which returns faults
like the normal translate functions if the address is malformed. It
attempts to return an approximately correct fault if the translation
isn't found, but since SPARC doesn't have hardware managed TLBs that
has to be an approximation.

translateFunctional also ignores permissions type checks (unless
they're built into the "lookup" method?) in line with vtophys type
semantics. The idea is that translateFunctional is used in conjunction
with functional accesses, and those are intended to reach beyond
normal barriers/boundaries to give unfettered access to the system for
debugging or setup purposes.

Change-Id: I000d9c31877b82043489792de037e7d664914fa9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26404
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Clean up condcodes.hh slightly.

Correct some minor style issues, make the functions static, and use the
single bit version of bits.

Change-Id: I4708961745a33caabecfbb06f8113ce8980e399e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26424
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Delete some commented out code in the TLB.

Change-Id: I80c455403422ec35bafa1f3ed86628f8327d1da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26403
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch,cpu,gpu-compute,mem: Remove asid from Request objects.

This is passed around a lot and set all over the place (usually to 0),
but it's never actually used for anything.

Change-Id: I38ca08387beabeaf9e339b4915ec7eba9e19eecb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26232
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Merge the virtual Request constructors.

The only difference was whether the the atomic op functor was accepted
as an argument. If it wasn't, setVirt would be called without an op
functor argument where it will default to nullptr.

This change deletes the constructor which doesn't take an atomic op
functor and in the other defaults the functor to nullptr. Functionally
nothing changes, but the code is now simpler.

Change-Id: Iff06543b1046594df297344e16961ee9d0f0a373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26231
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Get rid of one more unused Request constructor.

Also collapse setPhys, which is private, into the only caller which is
the Request constructor which takes a physical address.

Change-Id: I872c489cd168d7c364a57e26efce2350a3632c82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26230
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Get rid of another unused Request constructor.

This one took an explicit "time" value instead of using curTick().

Change-Id: I935ba1dfc194dcf156d7defedb6ce540db461ce4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26228
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Add default initializers to the fields in Request.

This avoids having to have bunches of uninteresting initializers in the
Request constructors, and accidentally forgetting to initialize any of
them.

Change-Id: If7a91fdf4aa6cd774f6f53474f55034ed6eda5f0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26227
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Disable a warning in hdf5.cc which comes from an external header.

This warning comes from an external header which we don't have the
ability to fix directly. We can disable it in hdf5.cc specifically
which should keep things building without defeating the warning in
cases where we could fix it.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-365

Change-Id: Ie1f4d91340e68cee7514beab9d03bba1d1c9bb38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26325
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Optimize and otherwise fix a couple of functions in intmath.hh.

As described in the Jira issue, this replaces the implementation of
isPowerOf2() and power(). It also revamps floorLog2 so that there only
needs to be one implementation and no assumptions about how big certain
types are.

The way power() used to work was to raise a number n to an exponent e
by multiplying n times itself e times. As a warning in this function
explains, this can be quite slow for large e. A much more efficient
way to raise a number to an exponent is to square n over and over, and
to multiply in the current square if that bit of e is set.

n ^ 15 = (n^1) * (n^2) * (n^4) * (n^8)
n^8 = (n^4)^2
n^4 = (n^2)^2
n^2 = n^2
n^1 = n

So that takes 6 multiplications, n^2, (n^2)^2, (n^4)^2, and then each
multipy to compute the final result, instead of 14.

The difference is more pronounced for larger exponents, although you'd
quickly start to overflow a uint64_t.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-140

Change-Id: I0ae05aeba1b5882d2a616613b1679e6206b4cbfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26164
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Get rid of an unused Request constructor.

This constructor took a physical address and a PC. After deleting it
all ISAs still compile.

Change-Id: I25f404f80ce7e995688165dc86ac8899da7aa919
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26226
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Switch away from some fringe Request constructors.

These are only used in these two files, one each, and pass one dummy
argument with a default value and one extra argument with an actual
value compared to the more common constructors.

Instead, switch to constructors without those two arguments and set the
one extra value explicitly after construction.

The constructor will likely be inlined, and merged with this additional
assignment.

Change-Id: I75ca539d5ca95b57b4f4322ffa050af2031544dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26229
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Remove the version of the FS translating port proxy with no tc.

This version is not used and is the only remaining consumer of the
vtophys variant with no ThreadContext.

Change-Id: I8cb870b841fe064cee121e4930cb163d2ec7628f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26223
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove unused getArmSystem helper

Change-Id: Ifbb1619fa1cfd6c6cda5c390889c423dbe62dc7e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25963
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Minor Ruby Prefetcher fixes

Minor fixes to the Ruby stride prefetcher. This includes removing unused
statistics and changing where/when some statistics are updated.

Change-Id: If758bf009f53fad277cb3cd754d57a0b10737599
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24363
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Track message based interrupt cleanup functions in sender state.

This makes sure the completion function follows the packet, and allows
multiple packets to be in flight at once without the functions
overwritting each other.

Change-Id: Ic49c7b646d56b32c0453931942ee22ae07828bb6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu,mem: Replace the mmmapped IPR mechanism with local accesses.

The new local access mechanism installs a callback in the request which
implements what the mmapped IPR was doing. That avoids having to have
stubs in ISAs that don't have mmapped IPRs, avoids having to encode
what to do to communicate from the TLB and the mmapped IPR functions,
and gets rid of another global ISA interface function and header files.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I772c2ae2ca3830a4486919ce9804560c0f2d596a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23188
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Disable the unused-value warning in clang for pybind.

pybind internally uses a construct which initializes an array of bools
as a way to run a function on each member of a parameter pack. It then
discards the array since it was just trying to run the function. This
triggers a warning in clang 11 called unused-value which breaks the
build.

This change adds some pragmas to the pybind11.h header which disable
that warning while in pybind11 which is less intrusive than trying to
fix the false positive warning, and better than disabling the warning
universally. Since g++ and clang++ will complain if they see this
pragma guarded by the other's name, these pragmas are also surrounded
by ifdefs which should make them only visible to clang.

Change-Id: Ie9b5c65e8cadc8b96fbc1bd7971bed4a61c4340d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25228
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

tests,misc: Created presubmit.yaml Google Cloud Build files

This will replicate kokoro on Google Cloud services. At present, this
can be run via execution of `gcloud builds submit--config
cloudbuild_presubmit.yaml`.

Jira: https://gem5.atlassian.net/browse/GEM5-271
Change-Id: I5a71ef7fdbe5546b4e6970e4f4641f9e14cc640b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24543
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: simple_ruby_test's valid_host is X86 only

This is because the binary is dynamically linked thus it can run
on a x86 host only.

Change-Id: I7391414fdcd8f861f62e54c4d681e29360eb7443
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Add a warning if pydot is not available.

Silently failing makes it hard to debug what happened. Add a warning.

Change-Id: Ia61b8de937bb254898726ad551fb5c894104d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26045
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Fix corrupted rename map in vector mode switching

This patch fixes the AArch32-AArch64 interprocessing issue introduced in
3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model.

When O3CPU switches vector renaming mode, architectural-physical mapping
and physical free list are switched in the following way so that content
of vectors has no change from software view:

Case 1. Full mode -> Elem mode (AArch64 -> AArch32):
1.1. Split vector-vector mapping into element-element mapping.
1.2. Split vectors in free list into elements.

Case 2. Elem mode -> Full mode (AArch32 -> AArch64):
2.1. Move content of all N*M mapped physical elements to first N*M
     physical elements in architectural order (N = number of
     architectural vectors, M = number of elements per vector).
2.2. Map N architectural vectors to first N physical vectors (i.e.
     initial mapping in full mode).
2.3. Place remaining physical vectors in free list (i.e. initial free
     list in full mode).

Previous gem5 revision misses step 2.2 when AArch32->AArch64 switch.
The wrong mapping will lead to the situation in which a physical vector
is assigned twice to a same architectural vector without being freed.
Once this occurs, the physical vector will not be freed anymore, since
it is treated as a special register (e.g. zero or misc) by O3CPU's
renaming logic. Eventually O3CPU will either stall forever when all
physical vectors get stuck, or trigger the panic condition "The free
list has lost vector registers" when AArch64->AArch32 switch. This patch
adds the missing step and fixes the issue.

Change-Id: I32233635c28763260bcbb776b52ed198a9abace9
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25743
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added MIPS ISA test to learning_gem5/part1_tests.py

Running these tests on the MIPS ISA was part of the old scons-based
scripts and was not present in the Python testlib framework (those
executed via `tests/main.py`). This has been migrated.

Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: Id87022e99ea83768710fb96b55136f777182fd43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25803
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Updated 'hello_se' to include other CPU types

Some tests are ignored due to bugs in the test executables. This has
been logged in the Jira issue here:
https://gem5.atlassian.net/browse/GEM5-356

Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: Idd2db04175333d1c24604e736df7833c1e441480
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25063
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

cpu: update info related direction into BP if mispredicted.

Update direction info of a branch into BP if, the branch is not
found in the target buffer. Therefore, this  updated direction is
used to squash the branch later on. Previously, some mispredicted
branches were not sqaushed as the BP had old info.

Reported-by: Dimitrios Chasapis
Change-Id: I4be2eb706edc5ffa9935948fb52a01667286c721
jira-issue: https://gem5.atlassian.net/browse/GEM5-355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25903
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Dimitrios Chasapis <k4s4s.heavener@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add missing UARTs (PL011) to VExpress_GEM5 platform

This uarts are present in the VE RS1 memory map

Change-Id: I894f401bf524dfd46f6a663980436d8e12e0cd69
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25986
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add trusted SP805 to VExpress_GEM5 platform

This watchdog is present in the VE RS2 memory map when security is
enabled.

Change-Id: I732debf4d3e987a351cc09ca7206ef40b52ada41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25985
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add trusted SRAM memory to VExpress_GEM5 platform

This memory is present in the VE RS1 memory map when security is enabled

Change-Id: I2e4fb95c2124d6e60b556903acb17fc4b1dba1a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25984
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add flash0 memory to VExpress_GEM5 platform

This memory is present in the VE RS1 memory map

Change-Id: Ia00c802f137d8a82c93b984f4043ba9f7fd8027a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25983
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix argument handling sweep.py

Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25710
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Remove unnecessary exports from pybind enums

According to pybind documentation [1], enum entries use
.export_values() to export the enum entries into the parent
scope. However, strongly typed C++11 class enums are in their own
scope and therefore do not need to be exported.

[1]: https://pybind11.readthedocs.io/en/stable/classes.html#enume
rations-and-internal-types

Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25709
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated 51.memcheck scons-based tests to testlib

"configs/example/memcheck.py" has been modified to keep the generated
"memcheck.cfg" in the "configs/example" directory. This generated file
is now ignored by git.

Change-Id: I19fab96419aa29e851139e759cc88b96465dd668
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: PL031, fix AMBA ID and clock names

This patch fixes the AMBA ID of the PL031 RTC. It also adds the
"clock-names" property to its auto-DTB generation. This fixes and
enables correct probing from Linux.

Change-Id: I331bfa81664f57a35f21f35d658772eb40380e35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25432
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

learning-gem5: Use zero initialization in hello_goodbye test

This is likely fixing:

JIRA: https://gem5.atlassian.net/browse/GEM5-328

the exitCause method was randomically printing an invalid string coming
from a non 0 terminated char buffer, whose pointer is provided via the
exitSimLoop.
By doing zero-initialization we make sure last character is '\0'.

Change-Id: I514a9bd240a0d5489ce9652ad14289f834752abe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25987
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Fixed .testignore from 'arch64' to 'aarch64'

Entries in `tests/gem5/.testignore` which were ignoring insttest tests,
were stating the host system as 'arch64' instead of 'aarch64'. This has
been fixed.

Change-Id: Ib90bd89e0544d225afc012fefca98db0ea2d8dd0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25845
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Expose the constants which select a semihosting operation.

Give these constants meaningful names instead of opaque constants only
visible in the .cc file.

Change-Id: Ib88912dae79960f785099c236c337db52a69d563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25945
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use a const ThreadContext * and readMiscRegNoEffect in places.

Unlike readMiscReg, readMiscRegNoEffect won't have any read related
side effects and so can be used on a const ThreadContext. Also, using
a const ThreadContext * in a few functions which don't actually intend
to change state makes them usable in more situations.

Change-Id: I4fe538ba1158b25f512d3cccd779e12f6c91da6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25944
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,arch: Move code that waits for a GDB connection to startup().

Currently the System class has a mechanism to wait for a GDB connection
for each CPU which has requested it through one of its parameters.
Unfortunately, not every thread context/CPU will be ready for GDB at
that point, particularly considering that in an FS simulation the
kernel won't have been read so there will be no symbols, none of the
registers or the entry point will have been set.

Also in the fast models, the CPUs haven't had a chance to initialize
themselves enough by that point to respond to the API calls which are
used to implement GDB support.

Change-Id: If27cb3e0259a1f67599ab0493695b2f8af640d8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24963
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: change the location of BTBlookup

BTBlookup should be done only if BTB is used, previously
this stat was updated for indirector predictor as well.

https: //gem5.atlassian.net/browse/GEM5-338
Change-Id: I20695dc7a8677d4fd0c4ae9f4f7d279387d5ad62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25625
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Updated tests/.gitignore to ignore test resources

Tests run via main.py create some temp resources. These are now ignored.

Change-Id: I63e2b7e1d70f8813e12c2e538a633046d614f1d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24324
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

Merge "misc: merge branch 'release-staging-v19.0.0.0' into develop" into develop

tests: Removed unneeded 02.insttest data

This test has been migrated to be run via `./main.py`.

Change-Id: I3608306da62c301bf0ebea6c5fbd1eebac703467
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25844
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: print --debug-flag Event execution and instance ID

This makes it much easier to determine what event is causing something to
happen, especially when there are multiple events happening at the
same time.

Change-Id: I17378e16bd3de1d98e936a6252aab2cd8c303b23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25383
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: merge branch 'release-staging-v19.0.0.0' into develop

Change-Id: I8430c6717697563386d165a40a0d080b0d18832e

tests: Migrated insttest tests to be run via  `./main.py run`

Some of these tests are ignored due to them failing. These should be
fixed at a later date.

Change-Id: Ida2810e00b7c9daa6b33caa01ab9dfd5b79bf03e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24323
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Change guest ABI for x86 pseudo insts

Change the guest ABI for x86 pseudo instructions to explictly write rax.
This is required because for some reason, the KVM CPU overwrites rax
after the KVM MMIO sets the value.

Note: This is hacky. It will only work for the current implementations
of x86 m5 ops which have their return value in RAX. A comment is added
to the m5ops file to make this clear.

Change-Id: I9466bf050b26db3650cfe3d23008e0f77fda8bc0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25664
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

dev-arm: RealView, add support for off-chip memory

This patch adds support for attaching off-chip memory in
"RealView" derived platforms.

Change-Id: Id1d430654abe83e76b532c8cf1ce2683a5a1e719
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25644
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: default _on_chip_memory on RealView

The _on_chip_memory member function is utilised at RealView level, but
it does not provide a default implementation. This assumes all platforms
extending RealView have on-chip memory. This patch provides a default
implementation for safeness.

Change-Id: Iaaa2bee7a85653ee97bfa95b50047eb350a88b58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25643
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Merged release-staging-v19.0.0.0 into develop

misc: Updated CONTRIBUTING.md to reflect altered release policy

It has been decided that contributions can be made to the staging branch
(assuming they are of a high enough importance). The staging branch will
then be merged into both the master and develop branches.

The time in which the staging branch exists has been extended to two
weeks.

Jira: https://gem5.atlassian.net/browse/GEM5-334
Change-Id: I3cd0b344be9768871b7fd79261c603d17d8ac1b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25523
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Use using to expose a print method that would otherwise be hidden.

This method would be hidden in the subclass which upset clang 11, and
that caused the build to break.

Change-Id: Ie678fc96a26809eb8f2acd0bddc1df81c0a9aa1e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25227
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Convert the static constexpr SIZE in vec_reg to a function.

When defining a static constexpr variable in C++11, it is still
required to have a separate definition someplace, something that can
be particularly problematic in template classes. C++17 fixes this
problem by adding inline variables which don't, but in the mean time
having a static constexpr value with no backing store will, if the
compiler decides to not fold away the storage location, cause linking
errors.

This happened to me when trying to build the debug build of ARM just
now.

By turning these expressions into static inline functions, then they
no longer need definitions elsewhere, still fold away to nothing, and
are compliant with C++11 which is currently the standard gem5 expects
to be using.

Change-Id: I647d7cf4a1e8de98251ee9ef116f007e08eac1f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24964
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Use all possible address spaces when setting up a bp.

gem5 does not historically distinguish between address spaces when
interacting with gdb, and gdb doesn't really give it any address space
information to work with. To ensure we catch whatever address space
we might be in by the time we get to the interesting address, we'll set
a breakpoint in all possible address spaces simultaneously with the
expectation that we'll hit one of them.

Change-Id: I9f4b93d04914db7a3c42be6236a523d35194afda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25268
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>

dev-arm: Fix setupBootloader for VExpress_GEM5_V2

Recent changes in the setupBootloader method didn't take into account
that the VExpress_GEM5_Base class does require "loc" to be passed
to the bootloader setup method:

setupBootLoader(self, cur_sys, loc, boot_loader=None)

However VExpress_GEM5_V2_Base was just passing cur_sys and boot_loader
so that the bootloader was being passed as loc and boot_loader was
passed as None (default parameter):

super(VExpress_GEM5_V2_Base, self).setupBootLoader(
        cur_sys, boot_loader)

This patch is fixing this by removing loc from the VExpress_GEM5_Base
interface: the bootloader defaults (usinbg loc) are being set in the
derived classes (V1 and V2)

Change-Id: Ic4d4e4fd8d45a7af9207900287828119c3d7d56c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25583
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Use a shared pointer to track PC events.

When the last event is removed from a breakpoint, then the breakpoint
itself is uninstalled from IRIS, and the list is deleted. Even though
the list has been traversed and so we don't lose track of any other
events that need to be processed, we also still need to check against
end() to see that we're done. If that now freed memory gets
overwritten, then we won't see the end and will wander right off the
end of the list into nonsense.

This change modifies the breakpoint info tracking structure to keep a
shared pointer to the event list. The pointer will still automatically
manage the list's memory so that it doesn't leak, and it won't get
deleted out from under us as we're iterating through it.

Change-Id: I5ad0f095d07f0a3a5cce9c10f03121827a674c33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24965
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>

fastmodel: Add in a missing include and namespace for itState.

Change-Id: I47661d95ae6f07768cb6ac1610bc29bc029c2bd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25624
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Return nullptr from getCheckerCpuPtr on fast model CPUs.

Fast model CPUs won't (at least as of now) have a checker CPU attached
to them. We can safely return nullptr to signal that to calling code.

Change-Id: I7edd4f895d9c3767cb991a2b2af6538cf9661969
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24966
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

fastmodel: Ignore clearArchRegs for now.

This only seems to be used from outside of the CPU when resetting state
at the start of execution. Since this state is already reset in
fast model, we can mostly ignore that call for now.

When more accessors are implemented, this function can be use them to
clear registers like it would on other thread contexts.

Change-Id: I5146273387ec17987770abc67f6f426c4480e0b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24967
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Fix pseudo instruction parameter loading

With the new ABI API the position argument of the pseudo inst ABI was
not updated correctly. The position needs to be incremented (at least)
once per argument.

Note: `position++` must be outside of the function call because of a GCC
complaint:
build/X86/sim/pseudo_inst.hh:80:48: error: cannot bind non-const lvalue
reference of type 'int&' to an rvalue of type 'PseudoInstABI::Position
{aka int}'
         return TheISA::getArgument(tc, position++, sizeof(uint64_t),
false);

Issue: https://gem5.atlassian.net/browse/GEM5-351
Change-Id: Idd890a587a565b8ad819f094147a02dc1519e997
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25543
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Set itstate when building a PCState from IRIS.

These bits are probably never going to be non-zero since we'd have to
take a checkpoint part way through an if/then construct in thumb, but
they're easy to extract and we might as well store them properly.

Change-Id: Ifc5c34063dd23f72cc106c0d77d90c5e6ee871be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24328
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: ArmISA::clear, inval TLB cached miscregs

ArmISA::clear resets the value of the architecture registers. Some of
these are cached in ArmTLB, including SCTLR. This patch invalidates the
cached copies on clear; this fixes a bug when resetting CPU cores by which
the cached SCTLR was used and SCTLR.M was set, resulting in non-arch
compliant reset behaviour and a PA being treated as a VA on translation.

Change-Id: I8d4eeeaf807325bd7b300a7a317abfa40ad23c87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25466
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: pass ThreadContext on ISA clear

This patch changes the clear API for the ISAs to pass the ThreadContext
issuing the call. This allows the ISA to carry out maintainance
operations on the TC state.

Change-Id: I40d6cf39c321521a221146aa0fd8f2cf665d39c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25465
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix vector renaming bug

The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/25009

moved initialization of vecMode out of initializing list.
In this way regFile gets initialized with an invalid initial renaming
mode.

Change-Id: Ib7bab9eaac0f5850fd3b3151584132f809a641e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25430
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, arch-arm: Use BaseISA in RenameMode interface

Please note: we are still templatizing the RenameMode class to avoid
virtual methods

Change-Id: I4afd99f45eaa45be9e032b67e106884a21c83234
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25429
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix CNTFRQ_EL0 permission bits

The register is marked as being writable at EL3 only (mon).  However the
arm arm states the register is accessible at the highest implemented EL.
Which means that if EL1 is the highest EL, EL1 code should be able to
modify the register value.

Change-Id: If9884fa2232869c043c96eba320e3c69efbab517
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25428
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,systemc: disable systemc tests scons by default

Not running the systemc test SConscript reduces the scons startup time
(before any file is compiled) from about 10s to 4s on my machine.

The performance investigation was done at:
https://gem5.atlassian.net/browse/GEM5-256

As before, the systemc tests are still automatically built when
they are run with:

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt

Change-Id: I33b7a53c0a7d70386ab17d7bb4886c84a97a2eb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25385
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add used attribute to pauth_helpers asserts

Adding M5_VAR_USED attribute to variables in pauth_helpers so that
gem5.fast builds.

Change-Id: I45dd70ea2e921f7ce68ea52147abdd40da99f37e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25364
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Remove ALPHA from the regress script.

The default architecture will now be ARM.

Change-Id: Ib2bda3d4ce1fc25f1fec1c9f62eeb9b81032017b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25460
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

util: Delete some Alpha related files from the m5 utility.

Change-Id: I5d751996d09459e79427851e80a4826e18f9db27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25459
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

util: Delete authors lists from files in util.

Change-Id: I2a165d3130c1464a73823046e4c7b03ba0355459
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25457
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Delete some test files which are specific to Alpha.

Change-Id: Idbffab70abdbb59817c6e002e26b8cb0fa96a4e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25458
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Remove mention of ALPHA from the README.

Change-Id: Ic0faf22e5ed94cf7e7591175a808c4696de29e25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25462
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Remove arch-alpha from the MAINTAINERS file.

This architecture no longer exists in gem5, and so doesn't need a
maintainer.

Change-Id: I41cfba1e60d24fd4016953addfb7933993bce98b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25461
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Remove mention of ALPHA from the SConstruct.

I've arbitrarily chosen to make ARM the default ISA for now, since I
think it's the best supported ISA with X86 somewhere a little behind
it. As a compromise, I change all mention of ALPHA (or even ALPHA_SE!)
in comments to be X86 instead, so it gets some attention too.

Change-Id: I1d8edc7925ca2d94f11b26e2c0b9314216e9b97d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25463
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Delete authors lists from shared include files.

Change-Id: I65d3d2e8df9799d9d3dc61734265a62b4dc9d67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25456
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system: Delete authors lists from system source files.

Change-Id: I899bd4d04ad1cbf5ab32d57df88e2a146d2e2e4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25455
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Delete authors lists from test files.

Change-Id: Id3628d34adccf8cc1044195b7209f3b01f061c93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25454
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Delete authors lists from x86 files.

Change-Id: I7f842105e2c506664fd62d5f671f90db59e42c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25453
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Delete authors lists from sparc files.

Change-Id: Iac3f9bb546121c73e6e73a0377d2a917c40df5f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25452
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Delete authors lists from riscv files.

Change-Id: I94135c8f0e1baee741d6470cb80b4da5e5f8e673
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25451
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Delete the authors lists from the power ISA.

Change-Id: Ib661723a9fcc09dd6e1e68a7c38a99e6d404dc46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25450
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Delete authors lists from mips files.

Change-Id: I56c054c64fe3d1e39ed5d315b8ac78de2e993dc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25449
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

hsail: Delete the author list from gpu_isa.hh.

Change-Id: I9c90fef4420286dbda7157d8961b4cf3c79a7c27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25448
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Delete authors lists from the arm files.

Change-Id: I6e9f5b70faebe5d279bff303c42f59a00a7845ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25447
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Delete authors lists from the null arch files.

Change-Id: Ief42708d8961a5c33db5e8a603ee8fff8df8b198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25446
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Delete authors lists from generic arch files.

Change-Id: I831a0f1876845f37ab12a2448e898719e74a0b55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25445
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,mips: Delete a large binary file from src/dev/mips.

This file doesn't seem to actually get referred to by anything in gem5,
and additionally MIPS FS mode has a ways to go before it can be used.
If this file is really necessary for running MIPS, it can be retrieved
from the history in the future.

Change-Id: I3a86fc928a4be1c9159f0fafb986dfb06d09bb7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25404
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Delete authors lists from files in sim.

Change-Id: I09a6117772c092157bf83701cf853145bb88ccf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25411
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Delete authors lists from systemc files.

Change-Id: I6c6219732029d5a9db1d317c130086cf2d16a272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25410
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Delete the authors list from files in src/dev.

Change-Id: I0907a6f1ada3038305c2d83a350a8d435ac657ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25403
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Be more verbose on load/store construction

This is achieved by using keyword arguments to improve readibility.
Some of the building helpers are using native types and can be annoying
for a reader to understand what those sequences of number and boolean
mean. It is also easier in this way to commit mistakes.

Change-Id: I63081d09a1f621550c5b6522b8107f349939b21d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24044
Tested-by: kokoro <noreply+kokoro@google.com>

base: Use a int to store fgetc return value

The stdio fgetc returns the character read as an unsigned char cast to
an int.
The reason why it gets casted from unsigned char to int is because EOF
is defined as a negative value (usually -1).

At the moment in the atomicio.test we store the int in a char.

However the C standard states that the sign of a char is implementation
specific. This makes the test non portable: an architecture/ABI which
which is considering a char as a unsigned char won't compile since a
unsigned value will always be != -1 (EOF).

This is the error message you would get on a aarch64 host /w gcc/5.4.0

build/ARM/base/atomicio.test.cc:121:48:
error: comparison is always true due to limited range of data type
[-Werror=type-limits]

Change-Id: I120e44b5204d98e643f19b8dd6fa2762342a6e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25384
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix ArmKVM build

BaseInterrupts don't have a checkRaw method.
This was breaking gem5 compilation on a Arm machine

Change-Id: I8717b1bcf64ed14e8a0f63a9dcaca6041dbea4d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25431
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Delete authors lists from the cpu directory.

Change-Id: Icfba8e23b5f6820a6ddefe1a50abbe5f8825b7b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25444
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>