binutils-gdb.git
23 months agold: Copy other symbols into PDB file
Mark Harmstone [Fri, 9 Dec 2022 01:52:39 +0000 (01:52 +0000)]
ld: Copy other symbols into PDB file

23 months agold: Write globals stream in PDB
Mark Harmstone [Fri, 9 Dec 2022 01:52:38 +0000 (01:52 +0000)]
ld: Write globals stream in PDB

23 months agold: Parse LF_UDT_SRC_LINE records when creating PDB file
Mark Harmstone [Fri, 9 Dec 2022 01:52:37 +0000 (01:52 +0000)]
ld: Parse LF_UDT_SRC_LINE records when creating PDB file

23 months agold: Write types into IPI stream of PDB
Mark Harmstone [Fri, 9 Dec 2022 01:52:36 +0000 (01:52 +0000)]
ld: Write types into IPI stream of PDB

23 months agold: Write types into TPI stream of PDB
Mark Harmstone [Fri, 9 Dec 2022 01:52:35 +0000 (01:52 +0000)]
ld: Write types into TPI stream of PDB

23 months agold: Write DEBUG_S_LINES entries in PDB file
Mark Harmstone [Fri, 9 Dec 2022 01:52:34 +0000 (01:52 +0000)]
ld: Write DEBUG_S_LINES entries in PDB file

23 months agold: Fix segfault in populate_publics_stream
Mark Harmstone [Fri, 9 Dec 2022 01:52:33 +0000 (01:52 +0000)]
ld: Fix segfault in populate_publics_stream

23 months agold: Write DEBUG_S_FILECHKSMS entries in PDBs
Mark Harmstone [Fri, 9 Dec 2022 01:52:32 +0000 (01:52 +0000)]
ld: Write DEBUG_S_FILECHKSMS entries in PDBs

23 months agold: Generate PDB string table
Mark Harmstone [Fri, 9 Dec 2022 01:52:31 +0000 (01:52 +0000)]
ld: Generate PDB string table

23 months agopdb build fixes
Alan Modra [Thu, 22 Dec 2022 01:19:09 +0000 (11:49 +1030)]
pdb build fixes

Enable compilation of ld/pdb.c just for x86, as is done for bfd/pdb.c.
This reduces the size of ld and is necessary with the following
patches that call a COFF-only bfd function from ld/pdb.c.  Without it
we'd break every non-COFF target build.

23 months agosim: lm32/m32r: drop redundant opcode/cgen.h include
Mike Frysinger [Fri, 23 Dec 2022 05:37:32 +0000 (00:37 -0500)]
sim: lm32/m32r: drop redundant opcode/cgen.h include

The xxx-desc.h header file already includes this, and it's how the
other cgen ports are getting it, so drop it from these two.

23 months agosim: ppc: drop unused types from sim-main.h
Mike Frysinger [Fri, 23 Dec 2022 05:27:08 +0000 (00:27 -0500)]
sim: ppc: drop unused types from sim-main.h

The common sim headers should define these for us already, so there's
no need for the ppc header to set them up.

23 months agosim: cgen: move symcat.h include to where it's used
Mike Frysinger [Fri, 23 Dec 2022 05:32:29 +0000 (00:32 -0500)]
sim: cgen: move symcat.h include to where it's used

Move this out of the global sim-main.h and to the few files that
actually use functions from it.  Only the cgen ports were pulling
this, so this makes cgen & non-cgen behave more the same.

23 months agosim: cgen: move cgen-types.h include to cgen-defs.h
Mike Frysinger [Fri, 23 Dec 2022 04:21:59 +0000 (23:21 -0500)]
sim: cgen: move cgen-types.h include to cgen-defs.h

The cgen-types.h header sets up types that are needed by cgen-defs.h,
so move the include out of sim-main.h and to that header.  It might
be needed in other specific modules, but for now let's kick it out of
sim-main.h to make some progress.  Things still build with just this.

23 months agoRevert "sim: mn10300: drop unused sim-main.c"
Mike Frysinger [Fri, 23 Dec 2022 05:20:52 +0000 (00:20 -0500)]
Revert "sim: mn10300: drop unused sim-main.c"

This reverts commit 681a422b855e4b20086554b170dae051361f00c7.

I missed that this was included via common/sim-inline.c.  I thought
I had grepped the top of the tree, but I must have only done mn10300.

Add a comment to make it clear where/how this file is used.

23 months agosim: mn10300: drop unused sim-main.c
Mike Frysinger [Fri, 23 Dec 2022 04:38:32 +0000 (23:38 -0500)]
sim: mn10300: drop unused sim-main.c

Nothing compiles or references this, so punt it.

23 months agosim: endian: move bfd.h from header to source
Mike Frysinger [Fri, 23 Dec 2022 03:06:52 +0000 (22:06 -0500)]
sim: endian: move bfd.h from header to source

The bfd APIs are used only by sim-n-endian.h which is only included by
sim-endian.c, so move the bfd.h include there and out of sim-endian.h
which is included by many other modules.

23 months agosim: move bfd.h include out of sim-main.h
Mike Frysinger [Fri, 23 Dec 2022 03:01:19 +0000 (22:01 -0500)]
sim: move bfd.h include out of sim-main.h

Not all arches include this in sim-main.h, and the ones that do don't
actually use bfd defines in the sim-main.h header.  Prune it to make
sim-main.h simpler so we can kill it off entirely in the future.

We add the include to the files that utilize e.g. bfd_vma though.

23 months agosim: mcore: replace custom "word" type with int32_t
Mike Frysinger [Fri, 23 Dec 2022 02:53:51 +0000 (21:53 -0500)]
sim: mcore: replace custom "word" type with int32_t

This is a 32-bit architecture with 32-bit registers, so replace the
custom "word" long int typedef with an explicit int32_t.  This is
a correctness fix since long will be 64-bits on most 64-bit hosts.

23 months agosim: moxie: replace custom "word" type with int32_t
Mike Frysinger [Fri, 23 Dec 2022 02:45:15 +0000 (21:45 -0500)]
sim: moxie: replace custom "word" type with int32_t

This is a 32-bit architecture with 32-bit registers, so replace the
custom "word" int typedef with an explicit int32_t.  Practically
speaking, this produces the same code, but it should hopefully make
it easier to merge common code in the future.

23 months agosim: cr16/d10v/mcore/moxie: clean up unused word & uword types
Mike Frysinger [Fri, 23 Dec 2022 02:36:24 +0000 (21:36 -0500)]
sim: cr16/d10v/mcore/moxie: clean up unused word & uword types

Nothing actually uses these, so punt them.  Some of the ports are
using local "word" types, but we'll clean those up in a follow up.

23 months agosim: mips: trim redundant igen settings
Mike Frysinger [Fri, 23 Dec 2022 02:28:16 +0000 (21:28 -0500)]
sim: mips: trim redundant igen settings

These variables are setting the same value as the defaults.  Trim
this redundant logic to make it easier to see the real differences
so we can try to keep unifying cases.

23 months agosim: mips: merge mips64* with existing multi-run build
Mike Frysinger [Fri, 11 Nov 2022 16:58:23 +0000 (23:58 +0700)]
sim: mips: merge mips64* with existing multi-run build

Change the default (unhandled) mips64* targets to use the existing
mips64 multi-run build.  It already handles the formats, we just
have to list the mips8000 bfd for it.

23 months agosim: mips: merge mips64vr5000 with existing multi-run build
Mike Frysinger [Fri, 11 Nov 2022 16:52:59 +0000 (23:52 +0700)]
sim: mips: merge mips64vr5000 with existing multi-run build

The existing mips64vr-* multi-run build already handles mips5000
targets, so reuse that for mips64vr5* targets too.  This moves
more logic from build-time to runtime so we can have a single
binary that supports many targets.

23 months agoRISC-V: Relax the order checking for the architecture string
Nelson Chu [Wed, 21 Dec 2022 03:22:06 +0000 (11:22 +0800)]
RISC-V: Relax the order checking for the architecture string

* riscv-toolchain-conventions,
PR, https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14
Issue, https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11

* Refer to the commit afc41ffb,
RISC-V: Reorder the prefixed extensions which are out of order.

In the past we only allow to reorder the prefixed extensions.  But according
to the PR 14 in the riscv-toolchain-convention, we can also relax the order
checking to allow the whole extensions be written out of orders, including
the single standard extensions and the prefixed multi-letter extensions.
Just that we still need to follow the following rules as usual,

1. prefixed extensions need to be seperated with `_'.
2. prefixed extensions need complete <major>.<minor> version if set.

Please see the details in the march-ok-reorder gas testcase.

Passed the riscv-gnu-toolchain regressions.

bfd/
    * elfxx-riscv.c (enum riscv_prefix_ext_class): Changed RV_ISA_CLASS_UNKNOWN
    to RV_ISA_CLASS_SINGLE, since everything that does not belong to the
    multi-keyword will possible be a single extension for the current parser.
    (parse_config): Likewise.
    (riscv_get_prefix_class): Likewise.
    (riscv_compare_subsets): Likewise.
    (riscv_parse_std_ext): Removed, and merged with riscv_parse_prefixed_ext
    into riscv_parse_extensions.
    (riscv_parse_prefixed_ext): Likewise.
    (riscv_parse_subset): Only need to call riscv_parse_extensions to parse
    both single standard and prefixed extensions.
gas/
    * testsuite/gas/riscv/march-fail-order-std.d: Removed since the relaxed
    order checking.
    * testsuite/gas/riscv/march-fail-order-std.l: Likewise.
    * testsuite/gas/riscv/march-fail-order-x-std.d: Likewise.
    * testsuite/gas/riscv/march-fail-order-z-std.d: Likewise.
    * testsuite/gas/riscv/march-fail-order-zx-std.l: Likewise.
    * testsuite/gas/riscv/march-fail-unknown-std.l: Updated.
    * testsuite/gas/riscv/march-ok-reorder.d: New testcase.

23 months agosim: drop unused SIM_ADDR type [PR sim/7504]
Mike Frysinger [Fri, 23 Dec 2022 01:01:37 +0000 (20:01 -0500)]
sim: drop unused SIM_ADDR type [PR sim/7504]

Now that sim APIs either use 64-bit addresses all the time, or more
appropriate target-specific types, drop this now-unused 32-bit-only
address type.

Bug: https://sourceware.org/PR7504

23 months agosim: mips: switch from SIM_ADDR to address_word
Mike Frysinger [Fri, 23 Dec 2022 00:59:38 +0000 (19:59 -0500)]
sim: mips: switch from SIM_ADDR to address_word

The latter type matches the address size configured for this sim.

Also take the opportunity to simplify printf logic by leveraging
PRI* macros.

23 months agosim: v850: switch from SIM_ADDR to address_word
Mike Frysinger [Fri, 11 Nov 2022 18:25:42 +0000 (01:25 +0700)]
sim: v850: switch from SIM_ADDR to address_word

The latter type matches the address size configured for this sim.

23 months agosim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]
Mike Frysinger [Fri, 11 Nov 2022 18:15:32 +0000 (01:15 +0700)]
sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]

We've been using SIM_ADDR which has always been 32-bit.  This means
the upper 32-bit address range in 64-bit sims is inaccessible.  Use
64-bit addresses all the time since we want the APIs to be stable
regardless of the active arch backend (which can be 32 or 64-bit).

The length is also 64-bit because it's completely feasible to have
a program that is larger than 4 GiB in size/image/runtime.  Forcing
the caller to manually chunk those accesses up into 4 GiB at a time
doesn't seem useful to anyone.

Bug: https://sourceware.org/PR7504

23 months agosim: use bfd_vma when reading start addr from bfd info
Mike Frysinger [Fri, 11 Nov 2022 18:13:26 +0000 (01:13 +0700)]
sim: use bfd_vma when reading start addr from bfd info

Since SIM_ADDR is always 32-bit, it might truncate the address with
64-bit ELFs.  Since we load that addr from the bfd, use the bfd_vma
type which matches the bfd_get_start_address API.

23 months agosim: m32r: include sim-hw.h for sim_hw_parse
Mike Frysinger [Fri, 23 Dec 2022 00:11:04 +0000 (19:11 -0500)]
sim: m32r: include sim-hw.h for sim_hw_parse

23 months agoCOFF build-id writes uninitialised data to file
Alan Modra [Thu, 22 Dec 2022 22:57:14 +0000 (09:27 +1030)]
COFF build-id writes uninitialised data to file

1) The first write in write_build_id wrote rubbish past the struct
external_IMAGE_DEBUG_DIRECTORY, which was later overwritten with
correct data.  No user visible problem there, except that tools like
valgrind complain.
2) The size for the pdb name was incorrectly calculated.

* emultempl/pe.em (write_build_id): Write the debug directory,
not the entire section contents.
(setup_build_id): Add size for the base name of pdb_name, not
the full path.
* emultempl/pep.em: Likewise.
* testsuite/ld-pe/pdb2-section-contrib.d: Update.

23 months agosim: mips: merge mips64vr4300 with existing multi-run build
Mike Frysinger [Fri, 11 Nov 2022 16:37:44 +0000 (23:37 +0700)]
sim: mips: merge mips64vr4300 with existing multi-run build

The existing mips64vr-* multi-run build already handles mips4300
targets, so reuse that for mips64vr43* targets too.  This moves
more logic from build-time to runtime so we can have a single
binary that supports many targets.

23 months agoAutomatic date update in version.in
GDB Administrator [Fri, 23 Dec 2022 00:01:40 +0000 (00:01 +0000)]
Automatic date update in version.in

23 months agosframe: doc: update documentation for pauth key in SFrame FDE
Indu Bhagat [Thu, 22 Dec 2022 17:58:21 +0000 (09:58 -0800)]
sframe: doc: update documentation for pauth key in SFrame FDE

ChangeLog:

* libsframe/doc/sframe-spec.texi

23 months agogas: sframe: testsuite: add testcase for .cfi_b_key_frame
Indu Bhagat [Thu, 22 Dec 2022 17:57:52 +0000 (09:57 -0800)]
gas: sframe: testsuite: add testcase for .cfi_b_key_frame

This is actually a composite test that checks SFrame unwind information
generation for both the .cfi_negate_ra_state and .cfi_b_key_frame
directives on aarch64.

ChangeLog:

* testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d:
New test.
* testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.s:
Likewise.
* testsuite/gas/cfi-sframe/cfi-sframe.exp: Run new test.

23 months agoobjdump/readelf: sframe: emit marker for SFrame FDE with B key
Indu Bhagat [Thu, 22 Dec 2022 17:57:27 +0000 (09:57 -0800)]
objdump/readelf: sframe: emit marker for SFrame FDE with B key

ChangeLog:

* libsframe/sframe-dump.c (is_sframe_abi_arch_aarch64): New
definition.
(dump_sframe_func_with_fres): Emit a string if B key is used.

23 months agogas: sframe: add support for .cfi_b_key_frame
Indu Bhagat [Thu, 22 Dec 2022 17:57:16 +0000 (09:57 -0800)]
gas: sframe: add support for .cfi_b_key_frame

Gather the information from the DWARF FDE on whether frame's return
addresses are signed using the B key or A key.  Reflect the information in
the SFrame counterpart data structure, the SFrame FDE.

ChangeLog:

* gas/gen-sframe.c (get_dw_fde_pauth_b_key_p): New definition.
(sframe_v1_set_func_info): Add new argument for pauth_key.
(sframe_set_func_info): Likewise.
(output_sframe_funcdesc): Likewise.
* gas/gen-sframe.h (struct sframe_version_ops): Add new argument
to the function pointer declaration.
* gas/sframe-opt.c (sframe_convert_frag): Handle pauth_key.

23 months agosframe.h: add support for .cfi_b_key_frame
Indu Bhagat [Thu, 22 Dec 2022 17:57:02 +0000 (09:57 -0800)]
sframe.h: add support for .cfi_b_key_frame

ARM 8.3 provides five separate keys that can be used to authenticate
pointers. There are two key for executable (instruction) pointers. The
enum pointer_auth_key in gas/config/tc-aarch64.h currently holds two keys:
  enum pointer_auth_key {
    AARCH64_PAUTH_KEY_A,
    AARCH64_PAUTH_KEY_B
  };

Analogous to the above, in SFrame format V1, a bit is reserved in the SFrame
FDE to indicate which key is used for signing the frame's return addresses:
  - SFRAME_AARCH64_PAUTH_KEY_A has a value of 0
  - SFRAME_AARCH64_PAUTH_KEY_B has a value of 1

Note that the information in this bit will always be used along with the
mangled_ra_p bit, the latter indicates whether the return addresses are
mangled/contain PAC auth bits.

include/ChangeLog:

* sframe.h (SFRAME_AARCH64_PAUTH_KEY_A): New definition.
(SFRAME_AARCH64_PAUTH_KEY_B): Likewise.
(SFRAME_V1_FUNC_INFO): Adjust to accommodate pauth_key.
(SFRAME_V1_FUNC_PAUTH_KEY): New macro.
(SFRAME_V1_FUNC_INFO_UPDATE_PAUTH_KEY): Likewise.

23 months agogas: re-arrange listing output for .irp and alike
Jan Beulich [Thu, 22 Dec 2022 13:31:11 +0000 (14:31 +0100)]
gas: re-arrange listing output for .irp and alike

It is kind of odd to have the expansions of such constructs ahead of
their definition in listings with macro expansion enabled. Adjust this
by pulling ahead the output of the definition lines, taking care to
avoid producing a listing line for (non-existing) line 0 when the source
is stdin.

Note that with the code movement the conditional operator isn't
necessary anymore - list->line now match up.

23 months agox86: correct/improve TSX controls
Jan Beulich [Thu, 22 Dec 2022 08:36:16 +0000 (09:36 +0100)]
x86: correct/improve TSX controls

TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx"
extension option covering both RTM and HLE, paralleling the "abm" one we
already have.

23 months agox86: add dependencies on SVME
Jan Beulich [Thu, 22 Dec 2022 08:35:53 +0000 (09:35 +0100)]
x86: add dependencies on SVME

SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES,
and yet in turn RMPQUERY is a SNP extension.

Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains
unused (just like CPU_SNP_FLAGS already is).

23 months agox86: add dependencies on VMX
Jan Beulich [Thu, 22 Dec 2022 08:35:32 +0000 (09:35 +0100)]
x86: add dependencies on VMX

Both EPT and VMFUNC are extensions to VMX.

23 months agox86: correct XSAVE* dependencies
Jan Beulich [Thu, 22 Dec 2022 08:35:11 +0000 (09:35 +0100)]
x86: correct XSAVE* dependencies

Like various other features AMX-TILE takes XSAVE as a prereq.

XSAVES, unconditionally using compacted format, in turn effectively
takes XSAVEC as a prereq (an SDM clarification to this effect is in the
works).

23 months agox86: correct dependencies of a few AVX512 sub-features
Jan Beulich [Thu, 22 Dec 2022 08:34:50 +0000 (09:34 +0100)]
x86: correct dependencies of a few AVX512 sub-features

Like AVX512-FP16, several other extensions require wider than 16-bit
mask registers. As a result they take AVX512BW as a prereq, not (just)
AVX512F. Which in turn points out wrong expectations in the noavx512-1
testcase.

23 months agox86: rework noavx512-1 testcase
Jan Beulich [Thu, 22 Dec 2022 08:34:17 +0000 (09:34 +0100)]
x86: rework noavx512-1 testcase

So far the set of ".noavx512*" has been accumulating, which isn't ideal.
In particular this hides issues with dependencies between features.
Switch back to the default ISA before disabling a particular subset.
Furthermore limit redundancy by wrapping the repeated block of insns in
an .irp.

23 months agox86: add dependencies on AVX2
Jan Beulich [Thu, 22 Dec 2022 08:33:53 +0000 (09:33 +0100)]
x86: add dependencies on AVX2

Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating
on up to 256-bit packed integer vectors.

23 months agox86: correct SSE dependencies
Jan Beulich [Thu, 22 Dec 2022 08:33:26 +0000 (09:33 +0100)]
x86: correct SSE dependencies

SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI
and KL take SSE2 as a prereq, for operating on packed integers. And
while correcting KL also record it as a prereq to WIDEKL.

23 months agox86: correct what gets disabled by certain ".arch .no*"
Jan Beulich [Thu, 22 Dec 2022 08:33:01 +0000 (09:33 +0100)]
x86: correct what gets disabled by certain ".arch .no*"

Features with prereqs as well as features with dependents cannot re-use
CPU_*_MASK for the 3rd argument of SUBARCH() - they need to use
CPU_ANY_*_MASK in order to avoid disabling too many (when there are
prereqs) and/or too few (when there are dependents) features.

Generally any CPU_ANY_*_MASK which exist should not remain unused.
Exceptions are
- FISTTP which has no corresponding entry in cpu_arch[],
- IAMCU which is a base architecture and hence uses ARCH(), not
  SUBARCH() (only extensions can be disabled, but unlike for Cpu*86 it
  would be a little more clumsy to suppress generating of the #define).

23 months agox86: re-work ISA extension dependency handling
Jan Beulich [Thu, 22 Dec 2022 08:32:29 +0000 (09:32 +0100)]
x86: re-work ISA extension dependency handling

Getting both forward and reverse ISA dependencies right / consistent has
been a permanent source of mistakes. Reduce what needs specifying
manually to just the direct forward dependencies. Transitive forward
dependencies as well as reverse ones are now derived and hence cannot go
out of sync anymore (at least in the vast majority of cases; there are a
few special cases to still take care of manually). In the course of this
several CPU_ANY_*_FLAGS disappear, requiring adjustment to the
assembler's cpu_arch[].

Note that to retain the correct reverse dependency of AVX512F wrt
AVX512-VP2INTERSECT, the latter has the previously missing AVX512F
prereq added.

Note further that to avoid adding the following undue prereqs:
* ATHLON, K8, and AMDFAM10 gain CMOV and FXSR,
* IAMCU gains 387,
auxiliary table entries (including a colon-separated modifier) are
introduced in addition to the ones representing from converting the old
table.

To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a)
(i.e. "nosse" not disabling AVX), reverse dependency tracking is
artifically suppressed.

As a side effect disabling of SSE or SSE2 will now also disable AES,
PCLMUL, and SHA (respective elements were missing from
CPU_ANY_SSE2_FLAGS).

23 months agosim: mips: match target on cpu settings
Mike Frysinger [Fri, 11 Nov 2022 16:27:12 +0000 (23:27 +0700)]
sim: mips: match target on cpu settings

We don't need to enforce larger target settings when the only thing
the sim should care about is the CPU target.  So reduce most of the
target matches to only check the CPU.

23 months agosim: mips: move fpu bitsize defines to top-level configure
Mike Frysinger [Fri, 11 Nov 2022 09:15:46 +0000 (16:15 +0700)]
sim: mips: move fpu bitsize defines to top-level configure

This drops support for the --enable-sim-float configure option,
but it's not clear anyone ever actually used that.  Eventually
we'll want this to be a runtime option anyways.

23 months agosim: mips: move bitsize defines to top-level configure
Mike Frysinger [Fri, 11 Nov 2022 08:57:55 +0000 (15:57 +0700)]
sim: mips: move bitsize defines to top-level configure

Since the msb value is always defined as the wordsize-1, stop
hardcoding that value directly, and use a CPP value instead.

23 months agosim: mips: move subtarget defines to top-level configure
Mike Frysinger [Fri, 11 Nov 2022 08:44:57 +0000 (15:44 +0700)]
sim: mips: move subtarget defines to top-level configure

We want to kill off mips/configure entirely.  Move this small part
out now to get started.

23 months agosim: mips: always resolve active bfd mach dynamically
Mike Frysinger [Fri, 11 Nov 2022 15:57:05 +0000 (22:57 +0700)]
sim: mips: always resolve active bfd mach dynamically

Don't assume that the default bfd that we configured for is the one
that is always active when running a program.  We already have access
to the real runtime value, so use it directly.  This simplifies the
code quite a bit, and will make it easier to support multiple mach's
in a single binary.

23 months agosim: hw-config.h: move generation to top-level
Mike Frysinger [Sun, 6 Nov 2022 15:57:06 +0000 (22:57 +0700)]
sim: hw-config.h: move generation to top-level

In order to compile arch objects from the top-level, we need to
generate the hw-config.h header, so move that logic up to the top
level first.

23 months agosim: build: hoist lists of hw devices up
Mike Frysinger [Sun, 6 Nov 2022 14:40:56 +0000 (21:40 +0700)]
sim: build: hoist lists of hw devices up

We need these in the top-level to generate libsim.a, but also in the
subdirs to generate hw-config.h.  Move it to the local.mk, and pass
it down when running recursive make.  This avoids duplication, and
makes it available to both.  We can simplify this once we move the
various steps up to the top-level too.

23 months agosim: build: hoist lists of common objects up
Mike Frysinger [Sun, 6 Nov 2022 14:24:24 +0000 (21:24 +0700)]
sim: build: hoist lists of common objects up

In order to create libsim.a in the common dir, we need the list of
objects for each target.  To avoid duplicating the list with the
recursive make in each port, pass it down as a variable.  This is
a temporary hack until the top-level creates libsim.a for ports.

23 months agoAutomatic date update in version.in
GDB Administrator [Thu, 22 Dec 2022 00:01:01 +0000 (00:01 +0000)]
Automatic date update in version.in

23 months agoPR29925, Memory leak in find_abstract_instance
Alan Modra [Wed, 21 Dec 2022 11:10:12 +0000 (21:40 +1030)]
PR29925, Memory leak in find_abstract_instance

The testcase in the PR had a variable with both DW_AT_decl_file and
DW_AT_specification, where the DW_AT_specification also specified
DW_AT_decl_file.  This leads to a memory leak as the file name is
malloced and duplicates are not expected.

I've also changed find_abstract_instance to not use a temp for "name",
because that can result in a change in behaviour from the usual last
of duplicate attributes wins.

PR 29925
* dwarf2.c (find_abstract_instance): Delete "name" variable.
Free *filename_ptr before assigning new file name.
(scan_unit_for_symbols): Similarly free func->file and
var->file before assigning.

23 months agoFix compiling of top.c
Andrew Pinski [Wed, 21 Dec 2022 17:30:14 +0000 (17:30 +0000)]
Fix compiling of top.c

When I moved my last patch forward, somehow I missed removing
the #endif for the HAVE_LIBMPFR case.

Committed as obvious after a quick build.

gdb/ChangeLog:
* top.c: Remove the extra #endif which was missed.

23 months agoUse toplevel configure for GMP and MPFR for gdb
Andrew Pinski [Tue, 8 Nov 2022 07:57:18 +0000 (07:57 +0000)]
Use toplevel configure for GMP and MPFR for gdb

This patch uses the toplevel configure parts for GMP/MPFR for
gdb. The only thing is that gdb now requires MPFR for building.
Before it was a recommended but not required library.
Also this allows building of GMP and MPFR with the toplevel
directory just like how it is done for GCC.
We now error out in the toplevel configure of the version
of GMP and MPFR that is wrong.

OK after GDB 13 branches? Build gdb 3 ways:
with GMP and MPFR in the toplevel (static library used at that point for both)
With only MPFR in the toplevel (GMP distro library used and MPFR built from source)
With neither GMP and MPFR in the toplevel (distro libraries used)

Changes from v1:
* Updated gdb/README and gdb/doc/gdb.texinfo.
* Regenerated using unmodified autoconf-2.69

Thanks,
Andrew Pinski

ChangeLog:
* Makefile.def: Add configure-gdb dependencies
on all-gmp and all-mpfr.
* configure.ac: Split out MPC checking from MPFR.
Require GMP and MPFR if the gdb directory exist.
* Makefile.in: Regenerate.
* configure: Regenerate.

gdb/ChangeLog:

PR bug/28500
* configure.ac: Remove AC_LIB_HAVE_LINKFLAGS
for gmp and mpfr.
Use GMPLIBS and GMPINC which is provided by the
toplevel configure.
* Makefile.in (LIBGMP, LIBMPFR): Remove.
(GMPLIBS, GMPINC): Add definition.
(INTERNAL_CFLAGS_BASE): Add GMPINC.
(CLIBS): Exchange LIBMPFR and LIBGMP
for GMPLIBS.
* target-float.c: Make the code conditional on
HAVE_LIBMPFR unconditional.
* top.c: Remove code checking HAVE_LIBMPFR.
* configure: Regenerate.
* config.in: Regenerate.
* README: Update GMP/MPFR section of the config
options.
* doc/gdb.texinfo: Likewise.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28500

23 months agogdb/c++: validate 'using' directives based on the current line
Bruno Larsen [Wed, 19 Oct 2022 14:57:44 +0000 (16:57 +0200)]
gdb/c++: validate 'using' directives based on the current line

When asking GDB to print a variable from an imported namespace, we only
want to see variables imported in lines that the inferior has already
gone through, as is being tested last in gdb.cp/nsusing.exp. However
with the proposed change to gdb.cp/nsusing.exp, we get the following
failures:

(gdb) PASS: gdb.cp/nsusing.exp: continue to breakpoint: marker10 stop
print x
$9 = 911
(gdb) FAIL: gdb.cp/nsusing.exp: print x, before using statement
next
15        y += x;
(gdb) PASS: gdb.cp/nsusing.exp: using namespace M
print x
$10 = 911
(gdb) PASS: gdb.cp/nsusing.exp: print x, only using M

Showing that the feature wasn't functioning properly, it just so
happened that gcc ordered the namespaces in a convenient way.
This happens because GDB doesn't take into account the line where the
"using namespace" directive is written. So long as it shows up in the
current scope, we assume it is valid.

To fix this, add a new member to struct using_direct, that stores the
line where the directive was written, and a new function that informs if
the using directive is valid already.

Unfortunately, due to a GCC bug, the failure still shows up. Compilers
that set the declaration line of the using directive correctly (such as
Clang) do not show such a bug, so the test includes an XFAIL for gcc
code.

Finally, because the final test of gdb.cp/nsusing.exp has turned into
multiple that all would need XFAILs for older GCCs (<= 4.3), and that
GCC is very old, if it is detected, the test just exits early.

Approved-by: Tom Tromey <tom@tromey.com>
23 months agoUpdated Romanian translation for the BFD sub-directory.
Nick Clifton [Wed, 21 Dec 2022 12:19:04 +0000 (12:19 +0000)]
Updated Romanian translation for the BFD sub-directory.

23 months agoFix an attempt to allocate an unreasonably large amount of memory when parsing a...
Nick Clifton [Wed, 21 Dec 2022 11:51:23 +0000 (11:51 +0000)]
Fix an attempt to allocate an unreasonably large amount of memory when parsing a corrupt ELF file.

PR  29924
* objdump.c (load_specific_debug_section): Check for excessively
large sections.

23 months agoKeep the .drectve section when performing a relocateable link.
Nick Clifton [Wed, 21 Dec 2022 10:23:08 +0000 (10:23 +0000)]
Keep the .drectve section when performing a relocateable link.

PR 29900
* scripttempl/pe.sc: Keep the .drectve section when performing a
relocateable link.
* scripttempl/pep.sc: Likewise.

23 months agox86: rename CheckRegSize to CheckOperandSize
Jan Beulich [Wed, 21 Dec 2022 08:07:03 +0000 (09:07 +0100)]
x86: rename CheckRegSize to CheckOperandSize

While originally indeed used for register size checking only, the
attribute has been used for memory operand size checking as well already
for quite a while, with more such uses recently having been added.

23 months agogprofng/testsuite: restrict testing to native configurations
Jan Beulich [Wed, 21 Dec 2022 08:05:43 +0000 (09:05 +0100)]
gprofng/testsuite: restrict testing to native configurations

The binaries involved in testing gprofng are native ones, and hence a
cross build of binutils won't really test intended functionality. Since
this testing takes quite a bit of time (typically more than running all
of binutils, gas, and ld testsuites together), restrict the testing to
native configurations only.

23 months agoenable-non-contiguous-regions warnings
Alan Modra [Wed, 21 Dec 2022 05:36:55 +0000 (16:06 +1030)]
enable-non-contiguous-regions warnings

The warning about discarded sections in elf_link_input_bfd doesn't
belong there since the code is dealing with symbols.  Multiple symbols
in a discarded section will result in multiple identical warnings
about the section.  Move the warning to a new function in ldlang.c.

The patch also tidies the warning quoting of section and file names,
consistently using `%pA' and `%pB'.  I'm no stickler for one style of
section and file name quoting, but they ought to be consistent within
a warning, eg. see the first one fixed in ldlang.c, and when a warning
is emitted for multiple targets they all ought to use exactly the same
format string to reduce translation work.  elf64-ppc.c loses the
build_one_stub errors since we won't get there before hitting the
fatal errors in size_one_stub.

bfd/
* elflink.c (elf_link_input_bfd): Don't warn here about
discarded sections.
* elf32-arm.c (arm_build_one_stub): Use consistent style in
--enable-non-contiguous-regions error.
* elf32-csky.c (csky_build_one_stub): Likewise.
* elf32-hppa.c (hppa_build_one_stub): Likewise.
* elf32-m68hc11.c (m68hc11_elf_build_one_stub): Likewise.
* elf32-m68hc12.c (m68hc12_elf_build_one_stub): Likewise.
* elf32-metag.c (metag_build_one_stub): Likewise.
* elf32-nios2.c (nios2_build_one_stub): Likewise.
* elfnn-aarch64.c (aarch64_build_one_stub): Likewise.
* xcofflink.c (xcoff_build_one_stub): Likewise.
* elf64-ppc.c (ppc_size_one_stub): Likewise.
(ppc_build_one_stub): Delete dead code.
ld/
* ldlang.c (lang_add_section): Use consistent style in
--enable-non-contiguous-regions warnings.
(size_input_section): Likewise.
(warn_non_contiguous_discards): New function.
(lang_process): Call it.
* testsuite/ld-arm/non-contiguous-arm.d: Update.
* testsuite/ld-arm/non-contiguous-arm4.d: Update.
* testsuite/ld-arm/non-contiguous-arm7.d: Add
--enable-non-contiguous-regions-warnings.
* testsuite/ld-arm/non-contiguous-arm7.err: New.
* testsuite/ld-powerpc/non-contiguous-powerpc.d: Update.
* testsuite/ld-powerpc/non-contiguous-powerpc64.d: Update.

23 months agoPR29922, SHT_NOBITS section avoids section size sanity check
Alan Modra [Tue, 20 Dec 2022 13:17:03 +0000 (23:47 +1030)]
PR29922, SHT_NOBITS section avoids section size sanity check

PR 29922
* dwarf2.c (find_debug_info): Ignore sections without
SEC_HAS_CONTENTS.

23 months agosim: fully merge sim_cpu_base into sim_cpu
Mike Frysinger [Mon, 31 Oct 2022 17:56:10 +0000 (23:41 +0545)]
sim: fully merge sim_cpu_base into sim_cpu

Now that all ports have migrated to the new framework, drop support
for the old sim_cpu_base layout.  There's a lot of noise here, so
it's been split into a dedicated commit.

23 months agosim: enable common sim_cpu usage everywhere
Mike Frysinger [Mon, 31 Oct 2022 17:54:51 +0000 (23:39 +0545)]
sim: enable common sim_cpu usage everywhere

All ports should be migrated now.  Drop the SIM_HAVE_COMMON_SIM_CPU
knob and require it be used everywhere now.

23 months agosim: or1k: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: or1k: invert sim_cpu storage

The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: m32r: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: m32r: invert sim_cpu storage

The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: lm32: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: lm32: invert sim_cpu storage

The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: iq2000: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: iq2000: invert sim_cpu storage

The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: frv: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: frv: invert sim_cpu storage

The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: cris: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: cris: invert sim_cpu storage

The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: bpf: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: bpf: invert sim_cpu storage

The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.

23 months agosim: cgen: prep for inverting sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 13:04:48 +0000 (18:49 +0545)]
sim: cgen: prep for inverting sim_cpu storage

Some common cgen code changes to allow cgen ports to invert their
sim_cpu storage one-by-one.

23 months agosim: riscv: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 06:15:34 +0000 (12:00 +0545)]
sim: riscv: invert sim_cpu storage

23 months agosim: pru: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 06:08:01 +0000 (11:53 +0545)]
sim: pru: invert sim_cpu storage

23 months agosim: example-synacor: invert sim_cpu storage
Mike Frysinger [Tue, 1 Nov 2022 05:57:11 +0000 (11:42 +0545)]
sim: example-synacor: invert sim_cpu storage

23 months agosim: h8300: invert sim_cpu storage
Mike Frysinger [Wed, 17 Aug 2016 02:50:25 +0000 (19:50 -0700)]
sim: h8300: invert sim_cpu storage

23 months agosim: m68hc11: invert sim_cpu storage
Mike Frysinger [Sat, 13 Aug 2016 18:40:31 +0000 (11:40 -0700)]
sim: m68hc11: invert sim_cpu storage

23 months agosim: mips: invert sim_cpu storage
Mike Frysinger [Sat, 13 Aug 2016 08:30:58 +0000 (01:30 -0700)]
sim: mips: invert sim_cpu storage

23 months agosim: v850: invert sim_cpu storage
Mike Frysinger [Sat, 13 Aug 2016 07:09:31 +0000 (15:09 +0800)]
sim: v850: invert sim_cpu storage

23 months agosim: mcore: invert sim_cpu storage
Mike Frysinger [Sat, 13 Aug 2016 07:00:33 +0000 (15:00 +0800)]
sim: mcore: invert sim_cpu storage

23 months agosim: aarch64: invert sim_cpu storage
Mike Frysinger [Sat, 13 Aug 2016 03:10:55 +0000 (11:10 +0800)]
sim: aarch64: invert sim_cpu storage

23 months agosim: microblaze: invert sim_cpu storage
Mike Frysinger [Sat, 13 Aug 2016 02:10:49 +0000 (10:10 +0800)]
sim: microblaze: invert sim_cpu storage

23 months agosim: avr: invert sim_cpu storage
Mike Frysinger [Fri, 12 Aug 2016 16:43:58 +0000 (00:43 +0800)]
sim: avr: invert sim_cpu storage

23 months agosim: moxie: invert sim_cpu storage
Mike Frysinger [Fri, 12 Aug 2016 16:37:34 +0000 (00:37 +0800)]
sim: moxie: invert sim_cpu storage

23 months agosim: msp430: invert sim_cpu storage
Mike Frysinger [Fri, 12 Aug 2016 16:28:11 +0000 (00:28 +0800)]
sim: msp430: invert sim_cpu storage

23 months agosim: ft32: invert sim_cpu storage
Mike Frysinger [Fri, 12 Aug 2016 16:07:45 +0000 (00:07 +0800)]
sim: ft32: invert sim_cpu storage

23 months agosim: bfin: invert sim_cpu storage
Mike Frysinger [Fri, 12 Aug 2016 15:43:27 +0000 (23:43 +0800)]
sim: bfin: invert sim_cpu storage

23 months agosim: sim_cpu: invert sim_cpu storage
Mike Frysinger [Fri, 12 Aug 2016 15:43:27 +0000 (23:43 +0800)]
sim: sim_cpu: invert sim_cpu storage

Currently all ports have to declare sim_cpu themselves in their
sim-main.h and then embed the common sim_cpu_base in it.  This
dynamic makes it impossible to share common object code among
multiple ports because the core data structure is always different.

Let's invert this relationship: common code declares sim_cpu, and
the port uses the new arch_data field for its per-cpu state.

This is the first in a series of changes: it adds a define to select
between the old & new layouts, then converts all the ports that don't
need custom state over to the new layout.  This includes mn10300 that,
while it defines custom fields in its cpu struct, never uses them.

23 months agosim: move register headers into sim/ namespace [PR sim/29869]
Mike Frysinger [Sat, 10 Dec 2022 11:33:58 +0000 (06:33 -0500)]
sim: move register headers into sim/ namespace [PR sim/29869]

These headers define the register numbers for each port to implement
the sim_fetch_register & sim_store_register interfaces.  While gdb
uses these, the APIs are part of the sim, not gdb.  Move the headers
out of the gdb/ include namespace and into sim/ instead.

23 months agosim: ppc: drop old dgen.c generator
Mike Frysinger [Wed, 9 Nov 2022 19:52:45 +0000 (02:52 +0700)]
sim: ppc: drop old dgen.c generator

The spreg.[ch] files live in the source tree now and are created
with the dgen.py script, so we don't need this old tool anymore.

23 months agosim: ppc: move spreg.[ch] files to the source tree
Mike Frysinger [Wed, 9 Nov 2022 19:52:45 +0000 (02:52 +0700)]
sim: ppc: move spreg.[ch] files to the source tree

Simplify the build by moving the generation of these files from
build-time (via dgen.c that we have to compile & execute on the
build system) to maintainer/release mode (via spreg-gen.py that
we only ever execute when the spreg table actually changes).  It
speeds up the build process and makes it easier for us to reason
about & review changes to the code generator.

The tool is renamed from "dgen" because it's hardcoded to only
generated spreg files.  It isn't a generalized tool for creating
lookup tables.

23 months agoAutomatic date update in version.in
GDB Administrator [Wed, 21 Dec 2022 00:00:53 +0000 (00:00 +0000)]
Automatic date update in version.in