yosys.git
4 years agoBump ABC for upstream fix
Eddie Hung [Wed, 18 Dec 2019 00:11:37 +0000 (16:11 -0800)]
Bump ABC for upstream fix

4 years agoUse pool<> instead of std::set<> to preserver ordering
Eddie Hung [Wed, 18 Dec 2019 00:10:40 +0000 (16:10 -0800)]
Use pool<> instead of std::set<> to preserver ordering

4 years agoaiger frontend to user shorter, $-prefixed, names
Eddie Hung [Tue, 17 Dec 2019 23:50:01 +0000 (15:50 -0800)]
aiger frontend to user shorter, $-prefixed, names

4 years agoCleanup xaiger, remove unnecessary complexity with inout
Eddie Hung [Tue, 17 Dec 2019 23:44:35 +0000 (15:44 -0800)]
Cleanup xaiger, remove unnecessary complexity with inout

4 years agoread_xaiger to cope with optional '\n' after 'c'
Eddie Hung [Tue, 17 Dec 2019 23:43:21 +0000 (15:43 -0800)]
read_xaiger to cope with optional '\n' after 'c'

4 years agoDo not sigmap
Eddie Hung [Tue, 17 Dec 2019 08:03:03 +0000 (00:03 -0800)]
Do not sigmap

4 years agoRevert "Use sigmap signal"
Eddie Hung [Tue, 17 Dec 2019 08:00:07 +0000 (00:00 -0800)]
Revert "Use sigmap signal"

This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907.

4 years agoabc9 needs a clean afterwards
Eddie Hung [Tue, 17 Dec 2019 02:41:56 +0000 (18:41 -0800)]
abc9 needs a clean afterwards

4 years agoPut $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
Eddie Hung [Tue, 17 Dec 2019 00:48:31 +0000 (16:48 -0800)]
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop

4 years agoUse sigmap signal
Eddie Hung [Tue, 17 Dec 2019 00:40:52 +0000 (16:40 -0800)]
Use sigmap signal

4 years agoSkip $inout transformation if not a PI
Eddie Hung [Mon, 16 Dec 2019 22:39:13 +0000 (14:39 -0800)]
Skip $inout transformation if not a PI

4 years agoRevert "write_xaiger: use sigmap bits more consistently"
Eddie Hung [Mon, 16 Dec 2019 22:35:35 +0000 (14:35 -0800)]
Revert "write_xaiger: use sigmap bits more consistently"

This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.

4 years agowrite_xaiger: use sigmap bits more consistently
Eddie Hung [Mon, 16 Dec 2019 18:21:08 +0000 (10:21 -0800)]
write_xaiger: use sigmap bits more consistently

4 years agoName inputs/outputs of aiger 'i%d' and 'o%d'
Eddie Hung [Sat, 14 Dec 2019 00:21:09 +0000 (16:21 -0800)]
Name inputs/outputs of aiger 'i%d' and 'o%d'

4 years agoRemove 'clkpart' entry in CHANGELOG
Eddie Hung [Thu, 12 Dec 2019 23:02:46 +0000 (15:02 -0800)]
Remove 'clkpart' entry in CHANGELOG

4 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Thu, 12 Dec 2019 22:57:17 +0000 (14:57 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff

4 years agoabc9_map.v: fix Xilinx LUTRAM
Eddie Hung [Thu, 12 Dec 2019 22:56:15 +0000 (14:56 -0800)]
abc9_map.v: fix Xilinx LUTRAM

4 years agoabc9_map.v: fix Xilinx LUTRAM
Eddie Hung [Thu, 12 Dec 2019 22:56:15 +0000 (14:56 -0800)]
abc9_map.v: fix Xilinx LUTRAM

4 years agoUpdate README.md :: abc_ -> abc9_
Eddie Hung [Thu, 12 Dec 2019 00:38:43 +0000 (16:38 -0800)]
Update README.md :: abc_ -> abc9_

4 years agoFix bitwidth mismatch; suppresses iverilog warning
Eddie Hung [Wed, 11 Dec 2019 21:02:07 +0000 (13:02 -0800)]
Fix bitwidth mismatch; suppresses iverilog warning

4 years agoMerge pull request #1564 from ZirconiumX/intel_housekeeping
David Shah [Wed, 11 Dec 2019 08:46:10 +0000 (08:46 +0000)]
Merge pull request #1564 from ZirconiumX/intel_housekeeping

Intel housekeeping

4 years agosynth_intel: a10gx -> arria10gx
Dan Ravensloft [Tue, 10 Dec 2019 13:40:32 +0000 (13:40 +0000)]
synth_intel: a10gx -> arria10gx

4 years agosynth_intel: cyclone10 -> cyclone10lp
Dan Ravensloft [Tue, 10 Dec 2019 13:31:45 +0000 (13:31 +0000)]
synth_intel: cyclone10 -> cyclone10lp

4 years agoMerge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Eddie Hung [Tue, 10 Dec 2019 01:38:48 +0000 (17:38 -0800)]
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr

Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER

4 years agoFix comment
Eddie Hung [Mon, 9 Dec 2019 23:44:19 +0000 (15:44 -0800)]
Fix comment

4 years agoice40_opt to restore attributes/name when unwrapping
Eddie Hung [Mon, 9 Dec 2019 22:29:29 +0000 (14:29 -0800)]
ice40_opt to restore attributes/name when unwrapping

4 years agoice40_wrapcarry -unwrap to preserve 'src' attribute
Eddie Hung [Mon, 9 Dec 2019 22:28:54 +0000 (14:28 -0800)]
ice40_wrapcarry -unwrap to preserve 'src' attribute

4 years agounmap $__ICE40_CARRY_WRAPPER in test
Eddie Hung [Mon, 9 Dec 2019 22:20:35 +0000 (14:20 -0800)]
unmap $__ICE40_CARRY_WRAPPER in test

4 years ago-unwrap to create $lut not SB_LUT4 for opt_lut
Eddie Hung [Mon, 9 Dec 2019 21:27:09 +0000 (13:27 -0800)]
-unwrap to create $lut not SB_LUT4 for opt_lut

4 years agoSensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
Eddie Hung [Mon, 9 Dec 2019 20:45:22 +0000 (12:45 -0800)]
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4

4 years agoice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung [Mon, 9 Dec 2019 19:48:28 +0000 (11:48 -0800)]
ice40_wrapcarry to really preserve attributes via -unwrap option

4 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Sat, 7 Dec 2019 07:22:52 +0000 (23:22 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff

4 years agoMerge pull request #1555 from antmicro/fix-macc-xilinx-test
Eddie Hung [Sat, 7 Dec 2019 07:04:04 +0000 (23:04 -0800)]
Merge pull request #1555 from antmicro/fix-macc-xilinx-test

tests: arch: xilinx: Change order of arguments in macc.sh

4 years agoDrop keep=0 attributes on SB_CARRY
Eddie Hung [Sat, 7 Dec 2019 01:27:47 +0000 (17:27 -0800)]
Drop keep=0 attributes on SB_CARRY

4 years agoCall abc9 with "&write -n", and parse_xaiger() to cope
Eddie Hung [Sat, 7 Dec 2019 00:35:57 +0000 (16:35 -0800)]
Call abc9 with "&write -n", and parse_xaiger() to cope

4 years agoRemove creation of $abc9_control_wire
Eddie Hung [Sat, 7 Dec 2019 00:23:09 +0000 (16:23 -0800)]
Remove creation of $abc9_control_wire

4 years agoDo not connect undriven POs to 1'bx
Eddie Hung [Sat, 7 Dec 2019 00:21:06 +0000 (16:21 -0800)]
Do not connect undriven POs to 1'bx

4 years agoFix abc9 re-integration, remove abc9_control_wire, use cell->type as
Eddie Hung [Sat, 7 Dec 2019 00:20:18 +0000 (16:20 -0800)]
Fix abc9 re-integration, remove abc9_control_wire, use cell->type as

as part of clock domain for mergeability class

4 years agoFix writing non-whole modules, including inouts and keeps
Eddie Hung [Sat, 7 Dec 2019 00:19:10 +0000 (16:19 -0800)]
Fix writing non-whole modules, including inouts and keeps

4 years agotests: arch: xilinx: Change order of arguments in macc.sh
Jan Kowalewski [Fri, 6 Dec 2019 08:01:16 +0000 (09:01 +0100)]
tests: arch: xilinx: Change order of arguments in macc.sh

4 years agoabc9 to use mergeability class to differentiate sync/async
Eddie Hung [Fri, 6 Dec 2019 07:18:27 +0000 (23:18 -0800)]
abc9 to use mergeability class to differentiate sync/async

4 years agowrite_xaiger to support part-selected modules again
Eddie Hung [Fri, 6 Dec 2019 01:54:43 +0000 (17:54 -0800)]
write_xaiger to support part-selected modules again

4 years agoabc9 to do clock partitioning again
Eddie Hung [Fri, 6 Dec 2019 01:26:22 +0000 (17:26 -0800)]
abc9 to do clock partitioning again

4 years agoRemove clkpart
Eddie Hung [Fri, 6 Dec 2019 01:25:26 +0000 (17:25 -0800)]
Remove clkpart

4 years agoRevert "Special abc9_clock wire to contain only clock signal"
Eddie Hung [Thu, 5 Dec 2019 19:11:53 +0000 (11:11 -0800)]
Revert "Special abc9_clock wire to contain only clock signal"

This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.

4 years agoMerge pull request #1551 from whitequark/manual-cell-operands
Clifford Wolf [Thu, 5 Dec 2019 16:24:24 +0000 (08:24 -0800)]
Merge pull request #1551 from whitequark/manual-cell-operands

Clarify semantics of comb cells, in particular shifts

4 years agoMerge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
Eddie Hung [Thu, 5 Dec 2019 15:01:18 +0000 (07:01 -0800)]
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER

4 years agoAdd WIP test for unwrapping $__ICE40_CARRY_WRAPPER
Eddie Hung [Thu, 5 Dec 2019 15:01:02 +0000 (07:01 -0800)]
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER

4 years agoMissing wire declaration
Eddie Hung [Thu, 5 Dec 2019 07:04:40 +0000 (23:04 -0800)]
Missing wire declaration

4 years agoabc9_map.v to transform INIT=1 to INIT=0
Eddie Hung [Thu, 5 Dec 2019 05:36:41 +0000 (21:36 -0800)]
abc9_map.v to transform INIT=1 to INIT=0

4 years agoOh deary me
Eddie Hung [Thu, 5 Dec 2019 04:33:24 +0000 (20:33 -0800)]
Oh deary me

4 years agoBump ABC to get "&verify -s" fix
Eddie Hung [Thu, 5 Dec 2019 00:37:56 +0000 (16:37 -0800)]
Bump ABC to get "&verify -s" fix

4 years agooutput reg Q -> output Q to suppress warning
Eddie Hung [Thu, 5 Dec 2019 00:34:34 +0000 (16:34 -0800)]
output reg Q -> output Q to suppress warning

4 years agoabc9_map.v to do `zinit' and make INIT = 1'b0
Eddie Hung [Thu, 5 Dec 2019 00:11:02 +0000 (16:11 -0800)]
abc9_map.v to do `zinit' and make INIT = 1'b0

4 years agokernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
whitequark [Wed, 4 Dec 2019 11:59:36 +0000 (11:59 +0000)]
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.

Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.

4 years agomanual: document behavior of many comb cells more precisely.
whitequark [Wed, 4 Dec 2019 11:06:05 +0000 (11:06 +0000)]
manual: document behavior of many comb cells more precisely.

4 years agoxilinx: Add tristate buffer mapping. (#1528)
Marcin Kościelnicki [Wed, 4 Dec 2019 08:44:00 +0000 (09:44 +0100)]
xilinx: Add tristate buffer mapping. (#1528)

Fixes #1225.

4 years agoiopadmap: Refactor and fix tristate buffer mapping. (#1527)
Marcin Kościelnicki [Wed, 4 Dec 2019 07:44:08 +0000 (08:44 +0100)]
iopadmap: Refactor and fix tristate buffer mapping. (#1527)

The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).

4 years agoxilinx: Add models for LUTRAM cells. (#1537)
Marcin Kościelnicki [Wed, 4 Dec 2019 05:31:09 +0000 (06:31 +0100)]
xilinx: Add models for LUTRAM cells. (#1537)

4 years agoCleanup
Eddie Hung [Wed, 4 Dec 2019 03:21:47 +0000 (19:21 -0800)]
Cleanup

4 years agoAdd assertion
Eddie Hung [Wed, 4 Dec 2019 03:21:42 +0000 (19:21 -0800)]
Add assertion

4 years agowrite_xaiger to consume abc9_init attribute for abc9_flops
Eddie Hung [Wed, 4 Dec 2019 02:47:44 +0000 (18:47 -0800)]
write_xaiger to consume abc9_init attribute for abc9_flops

4 years agoAdd abc9_init wire, attach to abc9_flop cell
Eddie Hung [Wed, 4 Dec 2019 02:47:09 +0000 (18:47 -0800)]
Add abc9_init wire, attach to abc9_flop cell

4 years agoRevert "Add INIT value to abc9_control"
Eddie Hung [Tue, 3 Dec 2019 23:40:44 +0000 (15:40 -0800)]
Revert "Add INIT value to abc9_control"

This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22.

4 years agoUpdate ABCREV for upstream bugfix
Eddie Hung [Tue, 3 Dec 2019 23:09:33 +0000 (15:09 -0800)]
Update ABCREV for upstream bugfix

4 years agoCheck SB_CARRY name also preserved
Eddie Hung [Tue, 3 Dec 2019 22:51:39 +0000 (14:51 -0800)]
Check SB_CARRY name also preserved

4 years ago$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve
Eddie Hung [Tue, 3 Dec 2019 22:49:10 +0000 (14:49 -0800)]
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve

name and attr

4 years agoice40_opt to ignore (* keep *) -ed cells
Eddie Hung [Tue, 3 Dec 2019 22:48:39 +0000 (14:48 -0800)]
ice40_opt to ignore (* keep *) -ed cells

4 years agoice40_wrapcarry to preserve SB_CARRY's attributes
Eddie Hung [Tue, 3 Dec 2019 22:48:11 +0000 (14:48 -0800)]
ice40_wrapcarry to preserve SB_CARRY's attributes

4 years agoAdd testcase
Eddie Hung [Tue, 3 Dec 2019 22:48:00 +0000 (14:48 -0800)]
Add testcase

4 years agotechmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung [Tue, 3 Dec 2019 22:27:45 +0000 (14:27 -0800)]
techmap abc_unmap.v before xilinx_srl -fixed

4 years agoMerge pull request #1524 from pepijndevos/gowindffinit
Clifford Wolf [Tue, 3 Dec 2019 16:43:18 +0000 (08:43 -0800)]
Merge pull request #1524 from pepijndevos/gowindffinit

Gowin: add and test DFF init values

4 years agoupdate test
Pepijn de Vos [Tue, 3 Dec 2019 15:56:15 +0000 (16:56 +0100)]
update test

4 years agoUse -match-init to not synth contradicting init values
Pepijn de Vos [Tue, 3 Dec 2019 14:12:25 +0000 (15:12 +0100)]
Use -match-init to not synth contradicting init values

4 years agoAdd INIT value to abc9_control
Eddie Hung [Mon, 2 Dec 2019 22:17:06 +0000 (14:17 -0800)]
Add INIT value to abc9_control

4 years agoMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix
David Shah [Mon, 2 Dec 2019 10:20:21 +0000 (10:20 +0000)]
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix

abc9: Fix breaking of SCCs

4 years agoCleanup
Eddie Hung [Mon, 2 Dec 2019 07:43:28 +0000 (23:43 -0800)]
Cleanup

4 years agoUse pool instead of std::set for determinism
Eddie Hung [Mon, 2 Dec 2019 07:26:17 +0000 (23:26 -0800)]
Use pool instead of std::set for determinism

4 years agoUse pool<> not std::set<> for determinism
Eddie Hung [Mon, 2 Dec 2019 07:19:32 +0000 (23:19 -0800)]
Use pool<> not std::set<> for determinism

4 years agoMerge pull request #1539 from YosysHQ/mwk/ilang-bounds-check
Clifford Wolf [Mon, 2 Dec 2019 00:30:48 +0000 (16:30 -0800)]
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check

read_ilang: do bounds checking on bit indices

4 years agoabc9: Fix breaking of SCCs
David Shah [Sun, 1 Dec 2019 20:44:56 +0000 (20:44 +0000)]
abc9: Fix breaking of SCCs

Signed-off-by: David Shah <dave@ds0.me>
4 years agoMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
Miodrag Milanović [Fri, 29 Nov 2019 16:33:41 +0000 (17:33 +0100)]
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll

xilinx: Add missing blackbox cell for BUFPLL.

4 years agoxilinx: Add missing blackbox cell for BUFPLL.
Marcin Kościelnicki [Fri, 29 Nov 2019 15:55:29 +0000 (15:55 +0000)]
xilinx: Add missing blackbox cell for BUFPLL.

4 years agoclkpart -unpart into 'finalize'
Eddie Hung [Thu, 28 Nov 2019 20:59:43 +0000 (12:59 -0800)]
clkpart -unpart into 'finalize'

4 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Thu, 28 Nov 2019 20:58:30 +0000 (12:58 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

4 years agoMove \init signal for non-port signals as long as internally driven
Eddie Hung [Thu, 28 Nov 2019 20:57:36 +0000 (12:57 -0800)]
Move \init signal for non-port signals as long as internally driven

4 years agoRevert "Fold loop"
Eddie Hung [Thu, 28 Nov 2019 05:55:56 +0000 (21:55 -0800)]
Revert "Fold loop"

This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35.

4 years agoread_ilang: do bounds checking on bit indices
Marcin Kościelnicki [Wed, 27 Nov 2019 21:24:39 +0000 (22:24 +0100)]
read_ilang: do bounds checking on bit indices

4 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 21:24:03 +0000 (13:24 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

4 years agoFix multiple driver issue
Eddie Hung [Wed, 27 Nov 2019 21:21:59 +0000 (13:21 -0800)]
Fix multiple driver issue

4 years agoAdd multiple driver testcase
Eddie Hung [Wed, 27 Nov 2019 21:22:26 +0000 (13:22 -0800)]
Add multiple driver testcase

4 years agoFix multiple driver issue
Eddie Hung [Wed, 27 Nov 2019 21:21:59 +0000 (13:21 -0800)]
Fix multiple driver issue

4 years agoAdd comment, use sigmap
Eddie Hung [Wed, 27 Nov 2019 21:20:12 +0000 (13:20 -0800)]
Add comment, use sigmap

4 years agoRevert "Fold loop"
Eddie Hung [Wed, 27 Nov 2019 20:35:25 +0000 (12:35 -0800)]
Revert "Fold loop"

This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.

4 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 18:17:10 +0000 (10:17 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff

4 years agoean call after abc{,9}
Eddie Hung [Wed, 27 Nov 2019 17:10:34 +0000 (09:10 -0800)]
ean call after abc{,9}

4 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 16:19:13 +0000 (08:19 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

4 years agoDo not replace constants with same wire
Eddie Hung [Wed, 27 Nov 2019 16:18:41 +0000 (08:18 -0800)]
Do not replace constants with same wire

4 years agoMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
Eddie Hung [Wed, 27 Nov 2019 16:00:22 +0000 (08:00 -0800)]
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd

xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder

4 years agoMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
Clifford Wolf [Wed, 27 Nov 2019 10:25:23 +0000 (11:25 +0100)]
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr

memory_collect: Copy attr from RTLIL::Memory to  cell