yosys.git
5 years agoopt and wreduce necessary for -dsp
Eddie Hung [Mon, 22 Jul 2019 20:48:33 +0000 (13:48 -0700)]
opt and wreduce necessary for -dsp

5 years agoPack adders not just accumulators
Eddie Hung [Mon, 22 Jul 2019 20:01:49 +0000 (13:01 -0700)]
Pack adders not just accumulators

5 years agoUse minimum sized width wires
Eddie Hung [Mon, 22 Jul 2019 20:01:26 +0000 (13:01 -0700)]
Use minimum sized width wires

5 years agoRestore old ffY behaviour
Eddie Hung [Sat, 20 Jul 2019 05:47:08 +0000 (22:47 -0700)]
Restore old ffY behaviour

5 years agoCleanup
Eddie Hung [Sat, 20 Jul 2019 03:25:28 +0000 (20:25 -0700)]
Cleanup

5 years agoIndirection via $__soft_mul
Eddie Hung [Sat, 20 Jul 2019 03:20:33 +0000 (20:20 -0700)]
Indirection via $__soft_mul

5 years agoDo not do sign extension in techmap; let packer do it
Eddie Hung [Fri, 19 Jul 2019 22:50:13 +0000 (15:50 -0700)]
Do not do sign extension in techmap; let packer do it

5 years agoMerge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 21:03:34 +0000 (14:03 -0700)]
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp

5 years agoAdd another test
Eddie Hung [Fri, 19 Jul 2019 21:02:46 +0000 (14:02 -0700)]
Add another test

5 years agoDo not access beyond bounds
Eddie Hung [Fri, 19 Jul 2019 20:58:50 +0000 (13:58 -0700)]
Do not access beyond bounds

5 years agoAdd an SigSpec::at(offset, defval) convenience method
Eddie Hung [Fri, 19 Jul 2019 20:54:57 +0000 (13:54 -0700)]
Add an SigSpec::at(offset, defval) convenience method

5 years agoWrap A and B in sigmap
Eddie Hung [Fri, 19 Jul 2019 20:23:07 +0000 (13:23 -0700)]
Wrap A and B in sigmap

5 years agoRemove "top" from message
Eddie Hung [Fri, 19 Jul 2019 20:20:45 +0000 (13:20 -0700)]
Remove "top" from message

5 years agoMerge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 20:18:20 +0000 (13:18 -0700)]
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp

5 years agoAlso optimise MSB of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:48 +0000 (13:11 -0700)]
Also optimise MSB of $sub

5 years agoAdd one more test with trimming Y_WIDTH of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:30 +0000 (13:11 -0700)]
Add one more test with trimming Y_WIDTH of $sub

5 years agoBe more explicit
Eddie Hung [Fri, 19 Jul 2019 19:53:18 +0000 (12:53 -0700)]
Be more explicit

5 years agowreduce for $sub
Eddie Hung [Fri, 19 Jul 2019 19:50:21 +0000 (12:50 -0700)]
wreduce for $sub

5 years agoAdd tests for sub too
Eddie Hung [Fri, 19 Jul 2019 19:50:11 +0000 (12:50 -0700)]
Add tests for sub too

5 years agoAdd test
Eddie Hung [Fri, 19 Jul 2019 19:43:02 +0000 (12:43 -0700)]
Add test

5 years agoSigSpec::extract to take negative lengths
Eddie Hung [Fri, 19 Jul 2019 19:34:04 +0000 (12:34 -0700)]
SigSpec::extract to take negative lengths

5 years agoDo not $mul -> $__mul if A and B are less than maxwidth
Eddie Hung [Fri, 19 Jul 2019 18:54:26 +0000 (11:54 -0700)]
Do not $mul -> $__mul if A and B are less than maxwidth

5 years agoAdd DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold
Eddie Hung [Fri, 19 Jul 2019 18:41:00 +0000 (11:41 -0700)]
Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold

5 years agoAdd a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
Eddie Hung [Fri, 19 Jul 2019 18:39:24 +0000 (11:39 -0700)]
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too

5 years agoFine tune ice40_dsp.pmg, add support for packing subsets of registers
Eddie Hung [Fri, 19 Jul 2019 17:57:32 +0000 (10:57 -0700)]
Fine tune ice40_dsp.pmg, add support for packing subsets of registers

5 years agoAdd support for ice40 signed multipliers
Eddie Hung [Fri, 19 Jul 2019 17:38:13 +0000 (10:38 -0700)]
Add support for ice40 signed multipliers

5 years agoMerge branch 'xc7dsp' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 17:28:38 +0000 (10:28 -0700)]
Merge branch 'xc7dsp' into ice40dsp

5 years agoFix typo in B
Eddie Hung [Fri, 19 Jul 2019 17:27:44 +0000 (10:27 -0700)]
Fix typo in B

5 years agoMerge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 16:40:47 +0000 (09:40 -0700)]
Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp

5 years agoice40: Fix test_dsp_model.sh
David Shah [Fri, 19 Jul 2019 16:33:57 +0000 (17:33 +0100)]
ice40: Fix test_dsp_model.sh

Signed-off-by: David Shah <dave@ds0.me>
5 years agoice40/cells_sim.v: Fix sign of J and K partial products
David Shah [Fri, 19 Jul 2019 16:33:41 +0000 (17:33 +0100)]
ice40/cells_sim.v: Fix sign of J and K partial products

Signed-off-by: David Shah <dave@ds0.me>
5 years agoUse sign_headroom instead
Eddie Hung [Fri, 19 Jul 2019 16:16:13 +0000 (09:16 -0700)]
Use sign_headroom instead

5 years agoice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
David Shah [Fri, 19 Jul 2019 16:13:34 +0000 (17:13 +0100)]
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd tests for all combinations of A and B signedness for comb mul
Eddie Hung [Fri, 19 Jul 2019 15:52:49 +0000 (08:52 -0700)]
Add tests for all combinations of A and B signedness for comb mul

5 years agoDon't copy ref if exists already
Eddie Hung [Fri, 19 Jul 2019 15:45:35 +0000 (08:45 -0700)]
Don't copy ref if exists already

5 years agoFix SB_MAC sim model -- do not sign extend internal products?
Eddie Hung [Fri, 19 Jul 2019 04:03:54 +0000 (21:03 -0700)]
Fix SB_MAC sim model -- do not sign extend internal products?

5 years agoAdd params
Eddie Hung [Fri, 19 Jul 2019 04:02:49 +0000 (21:02 -0700)]
Add params

5 years agoMerge remote-tracking branch 'origin/master' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 03:37:39 +0000 (20:37 -0700)]
Merge remote-tracking branch 'origin/master' into ice40dsp

5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Fri, 19 Jul 2019 03:36:48 +0000 (20:36 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoDo not define `DSP_SIGNEDONLY macro if no exists
Eddie Hung [Thu, 18 Jul 2019 23:04:58 +0000 (16:04 -0700)]
Do not define `DSP_SIGNEDONLY macro if no exists

5 years agoMerge remote-tracking branch 'origin/master' into ice40dsp
Eddie Hung [Thu, 18 Jul 2019 22:45:25 +0000 (15:45 -0700)]
Merge remote-tracking branch 'origin/master' into ice40dsp

5 years agoice40_dsp to accept $__MUL16X16 too
Eddie Hung [Thu, 18 Jul 2019 22:38:28 +0000 (15:38 -0700)]
ice40_dsp to accept $__MUL16X16 too

5 years agosynth_ice40 to decompose into 16x16
Eddie Hung [Thu, 18 Jul 2019 22:38:09 +0000 (15:38 -0700)]
synth_ice40 to decompose into 16x16

5 years agomul2dsp to create cells that can be interchanged with $mul
Eddie Hung [Thu, 18 Jul 2019 22:37:35 +0000 (15:37 -0700)]
mul2dsp to create cells that can be interchanged with $mul

5 years agoCheck if RHS is empty first
Eddie Hung [Thu, 18 Jul 2019 22:22:00 +0000 (15:22 -0700)]
Check if RHS is empty first

5 years agoMake consistent
Eddie Hung [Thu, 18 Jul 2019 22:21:23 +0000 (15:21 -0700)]
Make consistent

5 years agoDo not autoremove ffP aor muxP
Eddie Hung [Thu, 18 Jul 2019 22:02:41 +0000 (15:02 -0700)]
Do not autoremove ffP aor muxP

5 years agoImprove pattern matcher to match subsets of $dffe? cells
Eddie Hung [Thu, 18 Jul 2019 21:08:18 +0000 (14:08 -0700)]
Improve pattern matcher to match subsets of $dffe? cells

5 years agoImprove A/B reg packing
Eddie Hung [Thu, 18 Jul 2019 20:30:35 +0000 (13:30 -0700)]
Improve A/B reg packing

5 years agoDo not autoremove A/B registers since they might have other consumers
Eddie Hung [Thu, 18 Jul 2019 20:22:22 +0000 (13:22 -0700)]
Do not autoremove A/B registers since they might have other consumers

5 years agoFix xilinx_dsp index cast
Eddie Hung [Thu, 18 Jul 2019 20:18:04 +0000 (13:18 -0700)]
Fix xilinx_dsp index cast

5 years agoFix signed multiplier decomposition
Eddie Hung [Thu, 18 Jul 2019 20:11:26 +0000 (13:11 -0700)]
Fix signed multiplier decomposition

5 years agoUse single DSP_SIGNEDONLY macro
Eddie Hung [Thu, 18 Jul 2019 20:09:55 +0000 (13:09 -0700)]
Use single DSP_SIGNEDONLY macro

5 years agoMerge pull request #1208 from ZirconiumX/intel_cleanups
David Shah [Thu, 18 Jul 2019 18:04:28 +0000 (19:04 +0100)]
Merge pull request #1208 from ZirconiumX/intel_cleanups

Assorted synth_intel cleanups from @bwidawsk

5 years agosynth_intel: Use stringf
Dan Ravensloft [Thu, 18 Jul 2019 17:41:34 +0000 (18:41 +0100)]
synth_intel: Use stringf

5 years agoWorking for unsigned
Eddie Hung [Thu, 18 Jul 2019 17:53:18 +0000 (10:53 -0700)]
Working for unsigned

5 years agoMerge pull request #1207 from ZirconiumX/intel_new_pass_names
David Shah [Thu, 18 Jul 2019 16:34:55 +0000 (17:34 +0100)]
Merge pull request #1207 from ZirconiumX/intel_new_pass_names

synth_intel: rename for consistency with #1184

5 years agosynth_intel: s/not family/no family/
Dan Ravensloft [Thu, 18 Jul 2019 16:28:21 +0000 (17:28 +0100)]
synth_intel: s/not family/no family/

5 years agoCleanup
Eddie Hung [Thu, 18 Jul 2019 16:20:48 +0000 (09:20 -0700)]
Cleanup

5 years agosynth_intel: revert change to run_max10
Dan Ravensloft [Thu, 18 Jul 2019 16:08:52 +0000 (17:08 +0100)]
synth_intel: revert change to run_max10

5 years agointel_synth: Fix help message
Ben Widawsky [Mon, 8 Jul 2019 19:41:22 +0000 (12:41 -0700)]
intel_synth: Fix help message

cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agointel_synth: Small code cleanup to remove if ladder
Ben Widawsky [Mon, 8 Jul 2019 19:37:24 +0000 (12:37 -0700)]
intel_synth: Small code cleanup to remove if ladder

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agointel_synth: Make family explicit and match
Ben Widawsky [Mon, 8 Jul 2019 19:24:24 +0000 (12:24 -0700)]
intel_synth: Make family explicit and match

The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agointel_synth: Minor code cleanups
Ben Widawsky [Mon, 8 Jul 2019 19:03:00 +0000 (12:03 -0700)]
intel_synth: Minor code cleanups

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agosynth_intel: rename for consistency with #1184
Dan Ravensloft [Thu, 18 Jul 2019 15:46:21 +0000 (16:46 +0100)]
synth_intel: rename for consistency with #1184

Also fix a typo in the help message.

5 years agoWrong wildcard symbol
Eddie Hung [Thu, 18 Jul 2019 15:14:58 +0000 (08:14 -0700)]
Wrong wildcard symbol

5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung [Thu, 18 Jul 2019 15:11:33 +0000 (08:11 -0700)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoMerge pull request #1184 from whitequark/synth-better-labels
Clifford Wolf [Thu, 18 Jul 2019 13:34:28 +0000 (15:34 +0200)]
Merge pull request #1184 from whitequark/synth-better-labels

synth_{ice40,ecp5}: more sensible pass label naming

5 years agoMerge pull request #1203 from whitequark/write_verilog-zero-width-values
Clifford Wolf [Thu, 18 Jul 2019 13:31:27 +0000 (15:31 +0200)]
Merge pull request #1203 from whitequark/write_verilog-zero-width-values

write_verilog: dump zero width constants correctly

5 years agomul2dsp: Lower partial products always have unsigned inputs
David Shah [Thu, 18 Jul 2019 10:33:37 +0000 (11:33 +0100)]
mul2dsp: Lower partial products always have unsigned inputs

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMake all operands signed
Eddie Hung [Wed, 17 Jul 2019 21:25:40 +0000 (14:25 -0700)]
Make all operands signed

5 years agoUpdate comment
Eddie Hung [Wed, 17 Jul 2019 20:26:17 +0000 (13:26 -0700)]
Update comment

5 years agoPattern matcher to check pool of bits, not exactly
Eddie Hung [Wed, 17 Jul 2019 19:45:25 +0000 (12:45 -0700)]
Pattern matcher to check pool of bits, not exactly

5 years agoFix mul2dsp signedness
Eddie Hung [Wed, 17 Jul 2019 19:44:52 +0000 (12:44 -0700)]
Fix mul2dsp signedness

5 years agoA_SIGNED == B_SIGNED so flip both
Eddie Hung [Wed, 17 Jul 2019 18:34:18 +0000 (11:34 -0700)]
A_SIGNED == B_SIGNED so flip both

5 years agoSigSpec::remove_const() to return SigSpec&
Eddie Hung [Wed, 17 Jul 2019 17:44:11 +0000 (10:44 -0700)]
SigSpec::remove_const() to return SigSpec&

5 years agoRemove old $pmux_safe code from write_verilog
Clifford Wolf [Wed, 17 Jul 2019 09:49:04 +0000 (11:49 +0200)]
Remove old $pmux_safe code from write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1204 from smunaut/fix_1187
David Shah [Wed, 17 Jul 2019 06:55:26 +0000 (07:55 +0100)]
Merge pull request #1204 from smunaut/fix_1187

ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map

5 years agoAdd DSP_{A,B}_SIGNEDONLY macro
Eddie Hung [Tue, 16 Jul 2019 22:55:13 +0000 (15:55 -0700)]
Add DSP_{A,B}_SIGNEDONLY macro

5 years agoSignedness
Eddie Hung [Tue, 16 Jul 2019 22:54:27 +0000 (15:54 -0700)]
Signedness

5 years agoSigned extension
Eddie Hung [Tue, 16 Jul 2019 22:54:07 +0000 (15:54 -0700)]
Signed extension

5 years agoice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
Sylvain Munaut [Tue, 16 Jul 2019 21:57:15 +0000 (23:57 +0200)]
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map

The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
5 years agoRevert drop down to 24x16 multipliers for all
Eddie Hung [Tue, 16 Jul 2019 21:30:25 +0000 (14:30 -0700)]
Revert drop down to 24x16 multipliers for all

5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung [Tue, 16 Jul 2019 21:18:36 +0000 (14:18 -0700)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoAdd support {A,B,P}REG packing
Eddie Hung [Tue, 16 Jul 2019 21:06:32 +0000 (14:06 -0700)]
Add support {A,B,P}REG packing

5 years agoSigSpec::extract to allow negative length
Eddie Hung [Tue, 16 Jul 2019 21:06:07 +0000 (14:06 -0700)]
SigSpec::extract to allow negative length

5 years agoAdd support for {A,B,P}REG in DSP48E1
Eddie Hung [Tue, 16 Jul 2019 21:05:50 +0000 (14:05 -0700)]
Add support for {A,B,P}REG in DSP48E1

5 years agowrite_verilog: dump zero width constants correctly.
whitequark [Tue, 16 Jul 2019 20:57:05 +0000 (20:57 +0000)]
write_verilog: dump zero width constants correctly.

Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).

5 years agoMerge pull request #1202 from YosysHQ/cmp2lut_lut6
Eddie Hung [Tue, 16 Jul 2019 20:52:43 +0000 (13:52 -0700)]
Merge pull request #1202 from YosysHQ/cmp2lut_lut6

cmp2lut transformation to support >32 bit LUT masks

5 years agosynth_ecp5: rename dram to lutram everywhere.
whitequark [Tue, 16 Jul 2019 20:44:55 +0000 (20:44 +0000)]
synth_ecp5: rename dram to lutram everywhere.

5 years agosynth_{ice40,ecp5}: more sensible pass label naming.
whitequark [Thu, 11 Jul 2019 10:56:59 +0000 (10:56 +0000)]
synth_{ice40,ecp5}: more sensible pass label naming.

5 years agogen_lut to return correctly sized LUT mask
Eddie Hung [Tue, 16 Jul 2019 19:45:29 +0000 (12:45 -0700)]
gen_lut to return correctly sized LUT mask

5 years agoForgot to commit
Eddie Hung [Tue, 16 Jul 2019 19:44:26 +0000 (12:44 -0700)]
Forgot to commit

5 years agoAdd tests for cmp2lut on LUT6
Eddie Hung [Tue, 16 Jul 2019 19:11:59 +0000 (12:11 -0700)]
Add tests for cmp2lut on LUT6

5 years agoxilinx: Add correct signed behaviour to DSP48E1 model
David Shah [Tue, 16 Jul 2019 16:53:08 +0000 (17:53 +0100)]
xilinx: Add correct signed behaviour to DSP48E1 model

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
Eddie Hung [Tue, 16 Jul 2019 15:53:47 +0000 (08:53 -0700)]
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters

abc9: push inverters driving box inputs (comb outputs) through $lut soft logic

5 years agoMerge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
Eddie Hung [Tue, 16 Jul 2019 15:52:14 +0000 (08:52 -0700)]
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix

abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box

5 years agoxilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
David Shah [Tue, 16 Jul 2019 15:46:41 +0000 (16:46 +0100)]
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)

Signed-off-by: David Shah <dave@ds0.me>
5 years agomul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
David Shah [Tue, 16 Jul 2019 15:44:40 +0000 (16:44 +0100)]
mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH

Signed-off-by: David Shah <dave@ds0.me>
5 years agomul2dsp: Fix indentation
David Shah [Tue, 16 Jul 2019 15:19:32 +0000 (16:19 +0100)]
mul2dsp: Fix indentation

Signed-off-by: David Shah <dave@ds0.me>