Clifford Wolf [Thu, 28 Feb 2019 20:08:01 +0000 (12:08 -0800)]
Merge pull request #832 from YosysHQ/supercover
Add "supercover" pass
Clifford Wolf [Wed, 27 Feb 2019 19:45:13 +0000 (11:45 -0800)]
Improvements in "supercover" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 27 Feb 2019 19:37:08 +0000 (11:37 -0800)]
Add "supercover" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Larry Doolittle [Mon, 25 Feb 2019 06:09:54 +0000 (22:09 -0800)]
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
Larry Doolittle [Mon, 25 Feb 2019 06:08:52 +0000 (22:08 -0800)]
Clean up some whitepsace outliers
Clifford Wolf [Sun, 24 Feb 2019 19:41:36 +0000 (20:41 +0100)]
Minor changes ontop of
71bcc4c: Remove hierarchy warning that is redundant to -check
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 24 Feb 2019 19:39:13 +0000 (11:39 -0800)]
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
Define basic_cell_type() function and use it to derive the cell type …
Clifford Wolf [Sun, 24 Feb 2019 19:34:23 +0000 (20:34 +0100)]
Cleanups in ARST handling in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 24 Feb 2019 19:29:14 +0000 (11:29 -0800)]
Merge pull request #824 from litghost/fix_reduce_on_ff
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Clifford Wolf [Sun, 24 Feb 2019 19:09:41 +0000 (20:09 +0100)]
Fix handling of defparam for when default_nettype is none
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 24 Feb 2019 18:51:30 +0000 (19:51 +0100)]
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Jim Lawson [Sat, 23 Feb 2019 00:06:10 +0000 (16:06 -0800)]
Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
Keith Rothman [Fri, 22 Feb 2019 18:28:28 +0000 (10:28 -0800)]
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Adds test case that fails without code change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 22 Feb 2019 05:55:48 +0000 (06:55 +0100)]
Merge pull request #819 from YosysHQ/clifford/optd
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
Clifford Wolf [Fri, 22 Feb 2019 05:54:48 +0000 (06:54 +0100)]
Merge pull request #820 from YosysHQ/clifford/fix810
Fix #810 and fix #814
Clifford Wolf [Fri, 22 Feb 2019 00:16:34 +0000 (01:16 +0100)]
Merge pull request #740 from daveshah1/improve_dress
Improve ABC netname preservation
Clifford Wolf [Thu, 21 Feb 2019 22:13:14 +0000 (23:13 +0100)]
Fix Travis
It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 18:27:23 +0000 (19:27 +0100)]
Hotfix for
4c82ddf
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 18:24:16 +0000 (19:24 +0100)]
Merge pull request #822 from litghost/expand_setundef
Add -params mode to force undef parameters in selected cells.
Keith Rothman [Thu, 21 Feb 2019 18:16:38 +0000 (10:16 -0800)]
Add -params mode to force undef parameters in selected cells.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Thu, 21 Feb 2019 17:58:44 +0000 (18:58 +0100)]
Merge pull request #818 from YosysHQ/clifford/dffsrfix
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Clifford Wolf [Thu, 21 Feb 2019 17:56:01 +0000 (18:56 +0100)]
Merge pull request #786 from YosysHQ/pmgen
Pattern Matcher Generator and iCE40 DSP Mapper
Clifford Wolf [Thu, 21 Feb 2019 17:50:02 +0000 (18:50 +0100)]
Fix typo in passes/pmgen/README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 17:46:58 +0000 (18:46 +0100)]
Merge pull request #821 from eddiehung/dff_init
Revert "Add -B option to autotest.sh to append to backend_opts"
Clifford Wolf [Thu, 21 Feb 2019 17:40:11 +0000 (18:40 +0100)]
Fixes related to handling of autowires and upto-ranges, fixes #814
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 21 Feb 2019 17:22:29 +0000 (09:22 -0800)]
Revert "Add -B option to autotest.sh to append to backend_opts"
This reverts commit
281f2aadcab01465f83a3f3a697eec42503e9f8b.
Clifford Wolf [Thu, 21 Feb 2019 16:55:33 +0000 (17:55 +0100)]
Fix handling of expression width in $past, fixes #810
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 16:36:51 +0000 (17:36 +0100)]
Fix segfault in printing of some internal error messages
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 14:51:59 +0000 (15:51 +0100)]
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 13:27:46 +0000 (14:27 +0100)]
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 12:48:23 +0000 (13:48 +0100)]
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 21 Feb 2019 12:28:46 +0000 (13:28 +0100)]
Bugfix in ice40_dsp
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 21 Feb 2019 01:26:56 +0000 (17:26 -0800)]
Merge pull request #817 from eddiehung/dff_init
Cleanup #805
Eddie Hung [Wed, 20 Feb 2019 23:45:45 +0000 (15:45 -0800)]
Remove simple_defparam tests
Clifford Wolf [Wed, 20 Feb 2019 16:18:59 +0000 (17:18 +0100)]
Add ice40 test_dsp_map test case generator
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Feb 2019 15:42:27 +0000 (16:42 +0100)]
Add "synth_ice40 -dsp"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Feb 2019 15:36:42 +0000 (16:36 +0100)]
Add FF support to wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Feb 2019 11:55:20 +0000 (12:55 +0100)]
Improve iCE40 SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Feb 2019 10:18:19 +0000 (11:18 +0100)]
Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Jim Lawson [Tue, 19 Feb 2019 22:35:15 +0000 (14:35 -0800)]
Fix normal (non-array) hierarchy -auto-top.
Add simple test.
Eddie Hung [Tue, 19 Feb 2019 20:32:40 +0000 (12:32 -0800)]
Merge pull request #805 from eddiehung/dff_init
write_verilog to write initial statement for initial flop state
Clifford Wolf [Tue, 19 Feb 2019 12:42:21 +0000 (13:42 +0100)]
Add first draft of functional SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Sun, 17 Feb 2019 20:18:12 +0000 (12:18 -0800)]
Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf
Eddie Hung [Sun, 17 Feb 2019 20:11:52 +0000 (12:11 -0800)]
Revert "Add INIT parameter to all ff/latch cells"
This reverts commit
742b4e01b498ae2e735d40565f43607d69a015d8.
Eddie Hung [Sun, 17 Feb 2019 19:49:06 +0000 (11:49 -0800)]
Merge https://github.com/YosysHQ/yosys into dff_init
Clifford Wolf [Sun, 17 Feb 2019 14:35:48 +0000 (15:35 +0100)]
Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 17 Feb 2019 11:10:19 +0000 (12:10 +0100)]
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Clifford Wolf [Sun, 17 Feb 2019 10:39:14 +0000 (11:39 +0100)]
Merge pull request #811 from ucb-bar/firrtlfixes
Update cells supported for verilog to FIRRTL conversion.
Jim Lawson [Fri, 15 Feb 2019 20:00:28 +0000 (12:00 -0800)]
Removed unused variables, functions.
Jim Lawson [Fri, 15 Feb 2019 19:56:51 +0000 (11:56 -0800)]
Append (instead of over-writing) EXTRA_FLAGS
Jim Lawson [Fri, 15 Feb 2019 19:31:37 +0000 (11:31 -0800)]
Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code).
Jim Lawson [Fri, 15 Feb 2019 19:14:17 +0000 (11:14 -0800)]
Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
Clifford Wolf [Wed, 13 Feb 2019 11:36:47 +0000 (12:36 +0100)]
Fix sign handling of real constants
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)]
Merge pull request #802 from whitequark/write_verilog_async_mem_ports
write_verilog: correctly emit asynchronous transparent ports
Clifford Wolf [Tue, 12 Feb 2019 13:39:39 +0000 (14:39 +0100)]
Merge pull request #806 from daveshah1/fsm_opt_no_reset
fsm_opt: Fix runtime error for FSMs without a reset state
David Shah [Thu, 7 Feb 2019 10:35:36 +0000 (10:35 +0000)]
fsm_opt: Fix runtime error for FSMs without a reset state
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Wed, 6 Feb 2019 23:51:12 +0000 (15:51 -0800)]
Cope WIDTH of ff/latch cells is default of zero
Eddie Hung [Wed, 6 Feb 2019 22:53:40 +0000 (14:53 -0800)]
Remove check for cell->name[0] == '$'
Eddie Hung [Wed, 6 Feb 2019 22:28:44 +0000 (14:28 -0800)]
Refactor
Eddie Hung [Wed, 6 Feb 2019 22:17:09 +0000 (14:17 -0800)]
write_verilog to cope with init attr on q when -noexpr
Eddie Hung [Wed, 6 Feb 2019 22:16:26 +0000 (14:16 -0800)]
Add INIT parameter to all ff/latch cells
Eddie Hung [Wed, 6 Feb 2019 22:15:17 +0000 (14:15 -0800)]
Add tests for simple cases using defparam
Eddie Hung [Wed, 6 Feb 2019 22:14:55 +0000 (14:14 -0800)]
Add -B option to autotest.sh to append to backend_opts
Eddie Hung [Wed, 6 Feb 2019 22:02:11 +0000 (14:02 -0800)]
Extend testcase
David Shah [Wed, 6 Feb 2019 21:20:39 +0000 (22:20 +0100)]
ecp5: Use abc -dress
Signed-off-by: David Shah <davey1576@gmail.com>
David Shah [Sun, 16 Dec 2018 17:44:37 +0000 (17:44 +0000)]
abc: Improved recovered netnames, also preserve src on nets with dress
Signed-off-by: David Shah <davey1576@gmail.com>
David Shah [Sun, 16 Dec 2018 17:43:57 +0000 (17:43 +0000)]
ice40: Use abc -dress in synth_ice40
Signed-off-by: David Shah <davey1576@gmail.com>
David Shah [Tue, 4 Dec 2018 14:17:47 +0000 (14:17 +0000)]
abc: Preserve naming through ABC using 'dress' command
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Wed, 6 Feb 2019 20:49:30 +0000 (12:49 -0800)]
Add testcase
Clifford Wolf [Wed, 6 Feb 2019 15:35:59 +0000 (16:35 +0100)]
Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Tue, 29 Jan 2019 02:24:00 +0000 (02:24 +0000)]
write_verilog: correctly emit asynchronous transparent ports.
This commit fixes two related issues:
* For asynchronous ports, clock is no longer added to domain list.
(This would lead to absurd constructs like `always @(posedge 0)`.
* The logic to distinguish synchronous and asynchronous ports is
changed to correctly use or avoid clock in all cases.
Before this commit, the following RTLIL snippet (after memory_collect)
cell $memrd $2
parameter \MEMID "\\mem"
parameter \ABITS 2
parameter \WIDTH 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 1
parameter \TRANSPARENT 1
connect \CLK 1'0
connect \EN 1'1
connect \ADDR \mem_r_addr
connect \DATA \mem_r_data
end
would lead to invalid Verilog:
reg [1:0] _0_;
always @(posedge 1'h0) begin
_0_ <= mem_r_addr;
end
assign mem_r_data = mem[_0_];
Note that there are two potential pitfalls remaining after this
change:
* For asynchronous ports, the \EN input and \TRANSPARENT parameter
are silently ignored. (Per discussion in #760 this is the correct
behavior.)
* For synchronous transparent ports, the \EN input is ignored. This
matches the behavior of the $mem simulation cell. Again, see #760.
Clifford Wolf [Sun, 27 Jan 2019 08:25:18 +0000 (09:25 +0100)]
Merge pull request #798 from mmicko/master
Fixed Anlogic simulation model
Clifford Wolf [Sun, 27 Jan 2019 08:23:41 +0000 (09:23 +0100)]
Merge pull request #800 from whitequark/write_verilog_tribuf
write_verilog: write $tribuf cell as ternary
Clifford Wolf [Sun, 27 Jan 2019 08:17:29 +0000 (09:17 +0100)]
Merge branch 'whitequark-write_verilog_keyword'
Clifford Wolf [Sun, 27 Jan 2019 08:17:02 +0000 (09:17 +0100)]
Remove asicworld tests for (unsupported) switch-level modelling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Sun, 27 Jan 2019 00:21:31 +0000 (00:21 +0000)]
write_verilog: write $tribuf cell as ternary.
whitequark [Sat, 26 Jan 2019 23:55:46 +0000 (23:55 +0000)]
write_verilog: escape names that match SystemVerilog keywords.
David Shah [Fri, 25 Jan 2019 21:33:06 +0000 (21:33 +0000)]
Merge pull request #796 from whitequark/proc_clean_typo
proc_clean: fix critical typo
Miodrag Milanovic [Fri, 25 Jan 2019 18:25:25 +0000 (19:25 +0100)]
Fixed Anlogic simulation model
whitequark [Wed, 23 Jan 2019 22:08:38 +0000 (22:08 +0000)]
proc_clean: fix critical typo.
Clifford Wolf [Sat, 19 Jan 2019 08:31:17 +0000 (09:31 +0100)]
Merge pull request #793 from whitequark/proc_clean_fix_fully_def
proc_clean: fix fully def check to consider compare/signal length
whitequark [Fri, 18 Jan 2019 23:22:02 +0000 (23:22 +0000)]
proc_clean: fix fully def check to consider compare/signal length.
Fixes #790.
Clifford Wolf [Thu, 17 Jan 2019 13:54:04 +0000 (14:54 +0100)]
Cleanups in igloo2 example design
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 17 Jan 2019 13:38:37 +0000 (14:38 +0100)]
Add SF2 IO buffer insertion
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 17 Jan 2019 12:35:52 +0000 (13:35 +0100)]
Improve Igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 17 Jan 2019 12:33:45 +0000 (13:33 +0100)]
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 17 Jan 2019 12:33:11 +0000 (13:33 +0100)]
Add "write_edif -gndvccy"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 14 Jan 2019 12:42:42 +0000 (13:42 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 14 Jan 2019 12:29:27 +0000 (13:29 +0100)]
Progress in pmgen, add pmgen README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 16:15:40 +0000 (17:15 +0100)]
Fix pmgen "reject" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 16:03:58 +0000 (17:03 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 11:53:13 +0000 (12:53 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 09:57:11 +0000 (10:57 +0100)]
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 11 Jan 2019 13:02:16 +0000 (14:02 +0100)]
Add mockup .pmg (pattern matcher generator) file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 Jan 2019 16:00:58 +0000 (17:00 +0100)]
Add optional nullstr argument to log_id()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 Jan 2019 09:55:27 +0000 (10:55 +0100)]
Fix handling of $shiftx in Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 Jan 2019 08:52:01 +0000 (09:52 +0100)]
Merge pull request #788 from whitequark/master
Document $tribuf and some gates
Clifford Wolf [Tue, 15 Jan 2019 08:50:58 +0000 (09:50 +0100)]
Merge pull request #787 from whitequark/flowmap_relax
flowmap: implement depth relaxation
whitequark [Mon, 14 Jan 2019 16:17:25 +0000 (16:17 +0000)]
manual: document some gates.
whitequark [Mon, 14 Jan 2019 16:08:58 +0000 (16:08 +0000)]
manual: explain $tribuf cell.