nmigen.git
2 years agoback.rtlil: do not squash empty modules.
whitequark [Wed, 26 Aug 2020 22:45:19 +0000 (22:45 +0000)]
back.rtlil: do not squash empty modules.

In commit 9faa1d37, the RTLIL backend was changed to ignore modules
without ports completely, since Yosys would recognize empty modules
as black boxes without explicit `write_verilog -noblackbox` and break
the design. That change had many flaws:
  * It removed instances without ports, which are used in e.g. SoC
    FPGAs to instantiate a dummy CPU.
  * It removed fragments without ports, which can appear in e.g. SoC
    FPGAs in case the fabric is not connected to any I/O ports.
  * Finally, it was just conceptually unjustified.

This commit changes the logic to actually check for empty fragments,
and instead of removing them, it adds a dummy wire inside. It would
be possible to use the Yosys-specific (*noblackbox*) attribute.
However, it would be necessary to strip it for most targets right
away, and also the wire doubles as documentation.

Fixes #441.

2 years agoback.verilog: omit Verilog initial trigger only if Yosys adds it.
whitequark [Wed, 26 Aug 2020 09:01:57 +0000 (09:01 +0000)]
back.verilog: omit Verilog initial trigger only if Yosys adds it.

Verilog has an edge case where an `always @*` process, which is used
to describe a combinatorial function procedurally, may not execute
at time zero because none of the signals in its implicit sensitivity
list change, i.e. when the process doesn't read any signals. This
causes the wires driven by the process to stay undefined.

The workaround to this problem (assuming SystemVerilog `always_comb`
is not available) is to introduce a dummy signal that changes only
at time zero and is optimized out during synthesis. nMigen has had
its own workaround, `$verilog_initial_trigger`, for a while. However,
`proc_prune`, while increasing readability, pulls references to this
signal out of the process. Because of this, a similar workaround was
implemented in Yosys' `write_verilog` itself.

This commit ensures we use our workaround on versions of Yosys
without the updated `write_verilog`, and Yosys' workaround on later
versions.

Fixes #418.

2 years agovendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.
whitequark [Wed, 26 Aug 2020 10:18:02 +0000 (10:18 +0000)]
vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.

Fixes #438 (again).

2 years agovendor.xilinx_7series: unbreak.
whitequark [Wed, 26 Aug 2020 14:57:31 +0000 (14:57 +0000)]
vendor.xilinx_7series: unbreak.

This commit fixes a series of typos introduced in commit 4e208b0a.

2 years agosim._pyrtl: optimize uses of reflexive operators.
whitequark [Wed, 26 Aug 2020 13:26:38 +0000 (13:26 +0000)]
sim._pyrtl: optimize uses of reflexive operators.

When a literal is used on the left-hand side of a numeric operator,
Python is able to constant-fold some expressions:

    >>> dis.dis(lambda x: 0 + 0 + x)
      1           0 LOAD_CONST               1 (0)
                  2 LOAD_FAST                0 (x)
                  4 BINARY_ADD
                  6 RETURN_VALUE

If a literal is used on the right-hand side such that the left-hand
side is variable, this doesn't happen:

    >>> dis.dis(lambda x: x + 0 + 0)
      1           0 LOAD_FAST                0 (x)
                  2 LOAD_CONST               1 (0)
                  4 BINARY_ADD
                  6 LOAD_CONST               1 (0)
                  8 BINARY_ADD
                 10 RETURN_VALUE

PyRTL generates fairly redundant code due to the pervasive masking,
and because of that, transforming expressions into the former form,
where possible, improves runtime by about 10% on Minerva SRAM SoC.

2 years agoback.cxxrtl: actualize Yosys version requirement.
whitequark [Wed, 26 Aug 2020 09:16:46 +0000 (09:16 +0000)]
back.cxxrtl: actualize Yosys version requirement.

2 years agohdl.ast: avoid unnecessary sign padding in ArrayProxy.
whitequark [Wed, 26 Aug 2020 06:58:22 +0000 (06:58 +0000)]
hdl.ast: avoid unnecessary sign padding in ArrayProxy.

Before this commit, ArrayProxy would add sign padding (an extra bit)
a homogeneous array of signed values, or an array where all unsigned
values are smaller than the largest signed one. After this commit,
ArrayProxy would only add padding in arrays with mixed signedness
where all signed values are smaller or equal in size to the largest
unsigned value.

Fixes #476.

Co-authored-by: Pepijn de Vos <pepijndevos@gmail.com>
2 years agosim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()).
whitequark [Wed, 26 Aug 2020 04:15:26 +0000 (04:15 +0000)]
sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()).

Fixes #473.

2 years agolib.cdc: in AsyncFFSynchronizer(), rename domain= to
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 15:03:02 +0000 (15:03 +0000)]
lib.cdc: in AsyncFFSynchronizer(), rename domain= to
 o_domain=.

This is for consistency with other synchronizers.

Fixes #467.

2 years agovendor.lattice_machxo_2_3l: add SRAM svf generation
Robin Ole Heinemann [Tue, 4 Aug 2020 15:30:18 +0000 (17:30 +0200)]
vendor.lattice_machxo_2_3l: add SRAM svf generation

2 years agovendor: Add initial support for Symbiflow for Xilinx 7-series
Mariusz Glebocki [Sun, 2 Aug 2020 16:48:26 +0000 (18:48 +0200)]
vendor: Add initial support for Symbiflow for Xilinx 7-series

2 years agovendor.xilinx_7series: add `_part` property getter
Mariusz Glebocki [Mon, 24 Aug 2020 11:03:59 +0000 (13:03 +0200)]
vendor.xilinx_7series: add `_part` property getter

2 years agocli: Improve help texts
Xiretza [Sat, 22 Aug 2020 13:46:58 +0000 (15:46 +0200)]
cli: Improve help texts

545e49c2 added the option to export as CXXRTL, but the help texts for
the CLI options don't reflect this yet.

2 years agodocs/lang: use less confusing placeholder variable names.
whitequark [Sat, 15 Aug 2020 13:00:50 +0000 (13:00 +0000)]
docs/lang: use less confusing placeholder variable names.

Fixes #474.

2 years agolib.fifo: add `r_level` and `w_level` to all FIFOs
awygle [Sat, 15 Aug 2020 08:40:56 +0000 (01:40 -0700)]
lib.fifo: add `r_level` and `w_level` to all FIFOs

2 years agoAdd Linguist tags to .gitattributes.
whitequark [Thu, 13 Aug 2020 03:10:17 +0000 (03:10 +0000)]
Add Linguist tags to .gitattributes.

This should make it possible to navigate to nmigen/vendor/*.py using
GitHub's file finder.

2 years agovendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir correctly
Robin Ole Heinemann [Mon, 10 Aug 2020 15:23:29 +0000 (17:23 +0200)]
vendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir correctly

2 years agobuild,vendor: never carry around parts of differential signals.
whitequark [Fri, 31 Jul 2020 13:17:39 +0000 (13:17 +0000)]
build,vendor: never carry around parts of differential signals.

When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
2 years agovendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather than BUFGCE.
whitequark [Fri, 31 Jul 2020 14:45:38 +0000 (14:45 +0000)]
vendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather than BUFGCE.

Fixes #438 (again).

2 years agohdl.mem: cast reset value for transparent read ports to integer.
Adam Greig [Thu, 30 Jul 2020 07:05:18 +0000 (08:05 +0100)]
hdl.mem: cast reset value for transparent read ports to integer.

2 years agonmigen.lib.scheduler: add RoundRobin.
Jean THOMAS [Tue, 28 Jul 2020 21:02:01 +0000 (23:02 +0200)]
nmigen.lib.scheduler: add RoundRobin.

2 years agotests: fix remove unnecessary workaround for some unittest assertions.
Jacob Graves [Tue, 28 Jul 2020 19:35:25 +0000 (13:35 -0600)]
tests: fix remove unnecessary workaround for some unittest assertions.

2 years agovendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter.
whitequark [Wed, 22 Jul 2020 02:13:10 +0000 (02:13 +0000)]
vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter.

The parameter defaults to "ULTRASCALE", even when synthesizing for
7-series devices. This could lead to a simulation/synthesis mismatch,
and causes a warning.

Fixes #438.

2 years agovendor.lattice_ecp5: add missing differential IO types.
Jean THOMAS [Thu, 23 Jul 2020 12:24:31 +0000 (14:24 +0200)]
vendor.lattice_ecp5: add missing differential IO types.

2 years agoback.rtlil: lower maximum accepted wire size.
whitequark [Wed, 22 Jul 2020 14:43:44 +0000 (14:43 +0000)]
back.rtlil: lower maximum accepted wire size.

In practice wires of just 100000 bits sometimes have unacceptable
performance with Yosys, so stick to Verilog's minimum limit of 65536
bits.

2 years agosim._pycoro: avoid spurious wakeups.
whitequark [Wed, 22 Jul 2020 14:32:45 +0000 (14:32 +0000)]
sim._pycoro: avoid spurious wakeups.

This bug was introduced in commit e435a217.

2 years agoCI: replace Travis with GitHub Actions.
whitequark [Wed, 22 Jul 2020 08:11:59 +0000 (08:11 +0000)]
CI: replace Travis with GitHub Actions.

Fixes #445.

2 years agocompat.fhdl.bitcontainer: fix value_bits_sign().
whitequark [Tue, 21 Jul 2020 02:53:29 +0000 (02:53 +0000)]
compat.fhdl.bitcontainer: fix value_bits_sign().

This function was broken in commit 659b0e81; some downstream code
expects bits_sign to be e.g. indexable.

2 years agoCI: use WASM yosys instead of building our own.
whitequark [Thu, 16 Jul 2020 08:00:10 +0000 (08:00 +0000)]
CI: use WASM yosys instead of building our own.

Fixes #434.

2 years agoback.rtlil: fix guard for division by zero.
whitequark [Wed, 15 Jul 2020 04:09:58 +0000 (04:09 +0000)]
back.rtlil: fix guard for division by zero.

Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.

2 years agodocs: add install instructions for arch
Filipe Laíns [Mon, 13 Jul 2020 23:42:02 +0000 (00:42 +0100)]
docs: add install instructions for arch

Signed-off-by: Filipe Laíns <lains@archlinux.org>
2 years agoCI: run on pull requests as well, not just pushes.
whitequark [Tue, 14 Jul 2020 00:25:11 +0000 (00:25 +0000)]
CI: run on pull requests as well, not just pushes.

2 years agolib.cdc: fix typo.
whitequark [Mon, 13 Jul 2020 23:16:27 +0000 (23:16 +0000)]
lib.cdc: fix typo.

Co-authored-by: @ECP5-PCIe
2 years agosim.pysim: write the next, not curr signal value to the VCD file
Jacob Lifshay [Mon, 13 Jul 2020 02:10:01 +0000 (19:10 -0700)]
sim.pysim: write the next, not curr signal value to the VCD file

This is a temporary fix for #429.

2 years agosim.pysim: use VCD aliases to reduce space and time overhead.
whitequark [Sat, 11 Jul 2020 12:25:31 +0000 (12:25 +0000)]
sim.pysim: use VCD aliases to reduce space and time overhead.

On Minerva SoC, this reduces VCD file size by about 35%, and reduces
runtime overhead of writing VCDs by 10% or less.

2 years agoadd dummy extras_require to setup.py
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:51:56 +0000 (14:51 +0000)]
add dummy extras_require to setup.py

2 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:51:02 +0000 (14:51 +0000)]
whitespace

2 years agosim: simplify. NFC.
whitequark [Wed, 8 Jul 2020 17:30:06 +0000 (17:30 +0000)]
sim: simplify. NFC.

2 years agoback.pysim→sim.pysim; split into more manageable parts.
whitequark [Wed, 8 Jul 2020 12:49:38 +0000 (12:49 +0000)]
back.pysim→sim.pysim; split into more manageable parts.

This is necessary to add cxxrtl as an alternate simulation engine.

2 years agovendor.xilinx_{7series,ultrascale}: remove `grade` property.
whitequark [Wed, 8 Jul 2020 09:08:00 +0000 (09:08 +0000)]
vendor.xilinx_{7series,ultrascale}: remove `grade` property.

This was added in commit bfd4538d based on a misunderstanding of how
Xilinx part numbers work.
 * non-ultrascale 7-series parts don't have temperature grades;
 * ultrascale parts have temperature grade as a part of speed grade.

2 years agoback.pysim: only extract signal names if VCD is requested.
whitequark [Wed, 8 Jul 2020 08:29:20 +0000 (08:29 +0000)]
back.pysim: only extract signal names if VCD is requested.

This commit also fixes an issue introduced in 2606ee33 that regressed
simulator startup time and bloated VCD files. (It's actually about
10% faster now than *before* the regression was introduced.)

2 years agoback.pysim: reset timeline as well.
whitequark [Wed, 8 Jul 2020 07:12:00 +0000 (07:12 +0000)]
back.pysim: reset timeline as well.

This is a bug that was introduced in 94faf497b.

2 years agoback.pysim: simplify. NFC.
whitequark [Wed, 8 Jul 2020 06:29:34 +0000 (06:29 +0000)]
back.pysim: simplify. NFC.

2 years agoback.pysim: extract timeline handling to class _Timeline. NFC.
whitequark [Wed, 8 Jul 2020 06:04:50 +0000 (06:04 +0000)]
back.pysim: extract timeline handling to class _Timeline. NFC.

2 years agoback.pysim: extract simulator commands to sim._cmds. NFC.
whitequark [Wed, 8 Jul 2020 05:42:33 +0000 (05:42 +0000)]
back.pysim: extract simulator commands to sim._cmds. NFC.

2 years agoback.pysim: simplify. NFC.
whitequark [Wed, 8 Jul 2020 03:55:09 +0000 (03:55 +0000)]
back.pysim: simplify. NFC.

2 years agohdl.ast: don't inherit Shape from NamedTuple.
awygle [Tue, 7 Jul 2020 05:17:03 +0000 (22:17 -0700)]
hdl.ast: don't inherit Shape from NamedTuple.

Fixes #421.

2 years agoback.pysim: simplify.
whitequark [Tue, 7 Jul 2020 04:29:13 +0000 (04:29 +0000)]
back.pysim: simplify.

Compiled process names were never particularly useful (comments in
the source would make more sense for debugging), and coroutine
process names were actually source locations.

2 years agoback.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 04:19:05 +0000 (04:19 +0000)]
back.pysim: simplify. NFC.

2 years agoback.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 04:09:10 +0000 (04:09 +0000)]
back.pysim: simplify. NFC.

2 years agoback.pysim: synchronize waveform writing with cxxrtl.
whitequark [Tue, 7 Jul 2020 04:06:06 +0000 (04:06 +0000)]
back.pysim: synchronize waveform writing with cxxrtl.

2 years agoback.pysim: synchronize terms with cxxrtl. NFC.
whitequark [Tue, 7 Jul 2020 02:35:04 +0000 (02:35 +0000)]
back.pysim: synchronize terms with cxxrtl. NFC.

2 years agoback.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 02:14:06 +0000 (02:14 +0000)]
back.pysim: simplify. NFC.

2 years agoback.pysim: simplify. NFC.
whitequark [Tue, 7 Jul 2020 01:59:25 +0000 (01:59 +0000)]
back.pysim: simplify. NFC.

2 years agoRemove everything deprecated in nmigen 0.2.
whitequark [Mon, 6 Jul 2020 16:01:49 +0000 (16:01 +0000)]
Remove everything deprecated in nmigen 0.2.

2 years agoUpdate license and copyright info
Alan Green [Wed, 1 Jul 2020 21:29:30 +0000 (17:29 -0400)]
Update license and copyright info

Remove non-license explanatory text from LICENSE.txt.

Create CONTRIBUTING file with instructions and notes for contributors.

This change relates to issue #412

2 years agovendor.lattice_ecp5: Add support for io with xdr=7
Konrad Beckmann [Mon, 6 Jul 2020 14:04:24 +0000 (16:04 +0200)]
vendor.lattice_ecp5: Add support for io with xdr=7

This adds support for IOs with xdr=7 using the
IODDR71B and ODDR71B primitives.

2 years agovendor.lattice_ecp5: Add support for io with xdr=4
Konrad Beckmann [Mon, 6 Jul 2020 14:01:19 +0000 (16:01 +0200)]
vendor.lattice_ecp5: Add support for io with xdr=4

This adds support for IOs with xdr=4 using the
IDDRX2F and ODDRX2F primitives.

2 years agodocs: use working sphinxcontrib-platformpicker.
whitequark [Sun, 5 Jul 2020 23:51:14 +0000 (23:51 +0000)]
docs: use working sphinxcontrib-platformpicker.

2 years agodocs: use sphinxcontrib-platformpicker.
whitequark [Sun, 5 Jul 2020 23:39:47 +0000 (23:39 +0000)]
docs: use sphinxcontrib-platformpicker.

Fixes #416.

2 years agodocs: link to community tutorials until we have an official one.
whitequark [Sat, 4 Jul 2020 02:09:35 +0000 (02:09 +0000)]
docs: link to community tutorials until we have an official one.

2 years agodocs/lang: document constshifts.
whitequark [Thu, 2 Jul 2020 23:11:35 +0000 (23:11 +0000)]
docs/lang: document constshifts.

2 years agodocs/index: rename to "Language & toolchain".
whitequark [Thu, 2 Jul 2020 23:08:10 +0000 (23:08 +0000)]
docs/index: rename to "Language & toolchain".

2 years agotest: remove FHDLTestCase.assertRaisesRegex.
whitequark [Thu, 2 Jul 2020 22:49:04 +0000 (22:49 +0000)]
test: remove FHDLTestCase.assertRaisesRegex.

This method is only there because I misunderstood the documentation
of unittest.

2 years agocompat.fhdl.specials: fix handling of tristate (i=None) pins.
whitequark [Thu, 2 Jul 2020 22:22:44 +0000 (22:22 +0000)]
compat.fhdl.specials: fix handling of tristate (i=None) pins.

Fixes #406.

2 years ago_yosys→_toolchain.yosys
whitequark [Thu, 2 Jul 2020 18:26:08 +0000 (18:26 +0000)]
_yosys→_toolchain.yosys

2 years agovendor: `yosys` is not a required tool for proprietary toolchains.
whitequark [Thu, 2 Jul 2020 18:13:54 +0000 (18:13 +0000)]
vendor: `yosys` is not a required tool for proprietary toolchains.

Since commit b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.

Fixes #419.

2 years agoadd wheel as setup dependency
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:40:50 +0000 (14:40 +0000)]
add wheel as setup dependency

2 years agodocs/install: use pip/pip3 more consistently.
whitequark [Wed, 1 Jul 2020 08:58:36 +0000 (08:58 +0000)]
docs/install: use pip/pip3 more consistently.

2 years agodocs: clarify naming.
whitequark [Wed, 1 Jul 2020 08:53:52 +0000 (08:53 +0000)]
docs: clarify naming.

2 years agore-add setutools and setuptools_scm
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:34:49 +0000 (14:34 +0000)]
re-add setutools and setuptools_scm

2 years agoRevert "Add PEP 518 `pyproject.toml`."
whitequark [Wed, 1 Jul 2020 08:16:28 +0000 (08:16 +0000)]
Revert "Add PEP 518 `pyproject.toml`."

This reverts commit 7fca037f9c14974f499195171bb84c38ebddc1e1.

This broke editable installs and has to be reverted due to a number
of pip issues:
  * pypa/pip#6375
  * pypa/pip#6434
  * pypa/pip#6438

We can put this back once PEP 517/518 support editable installs.
Until then the legacy behavior will suffice, and we should just teach
people to install the dependencies in virtualenvs or something...

2 years agodocs: add a crude approximation of intersphinx toctrees.
whitequark [Wed, 1 Jul 2020 08:03:57 +0000 (08:03 +0000)]
docs: add a crude approximation of intersphinx toctrees.

This is a pretty awful hack. We could do this properly after one of
the following issues is fixed:
  * sphinx-doc/sphinx#701
  * sphinx-doc/sphinx#1836

2 years agoGracefully handle missing dependencies.
whitequark [Wed, 1 Jul 2020 07:00:02 +0000 (07:00 +0000)]
Gracefully handle missing dependencies.

Some people's workflows involve not using `pip`. This is not
a recommended way to use nMigen, but is prevalent enough for good
enough reason that we try to keep them working anyway.

2 years agodocs/install: fix dead link.
whitequark [Wed, 1 Jul 2020 06:33:03 +0000 (06:33 +0000)]
docs/install: fix dead link.

2 years agodocs/install: quote special chars to avoid issues with extended glob.
whitequark [Wed, 1 Jul 2020 06:32:15 +0000 (06:32 +0000)]
docs/install: quote special chars to avoid issues with extended glob.

2 years agodocs/install: explain how to install non-editable snapshot from git.
whitequark [Wed, 1 Jul 2020 06:15:16 +0000 (06:15 +0000)]
docs/install: explain how to install non-editable snapshot from git.

2 years agomanually remove setuptools and setuptools_scm, moved
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:31:28 +0000 (14:31 +0000)]
manually remove setuptools and setuptools_scm, moved
to pyproject.toml

2 years agoAdd PEP 518 `pyproject.toml`.
whitequark [Wed, 1 Jul 2020 05:58:05 +0000 (05:58 +0000)]
Add PEP 518 `pyproject.toml`.

This is necessary to be able to install nMigen into a virtualenv that
does not have `wheel` installed in certain cases.

See #349.

2 years agodocs/install: use `pip install --user` on *nix.
whitequark [Wed, 1 Jul 2020 05:06:20 +0000 (05:06 +0000)]
docs/install: use `pip install --user` on *nix.

2 years agodocs/install: reduce repetition.
whitequark [Wed, 1 Jul 2020 04:11:51 +0000 (04:11 +0000)]
docs/install: reduce repetition.

2 years agodocs: reword slightly.
whitequark [Wed, 1 Jul 2020 03:59:16 +0000 (03:59 +0000)]
docs: reword slightly.

2 years agodocs: explain how to install GTKWave on Windows.
whitequark [Wed, 1 Jul 2020 03:46:59 +0000 (03:46 +0000)]
docs: explain how to install GTKWave on Windows.

2 years agoCI: build docs on all pushes, update only on master.
whitequark [Wed, 1 Jul 2020 03:37:29 +0000 (03:37 +0000)]
CI: build docs on all pushes, update only on 

2 years agodocs: rewrite install instructions to be easier to understand.
whitequark [Wed, 1 Jul 2020 03:32:17 +0000 (03:32 +0000)]
docs: rewrite install instructions to be easier to understand.

2 years agodocs: fix syntax.
whitequark [Tue, 30 Jun 2020 22:29:43 +0000 (22:29 +0000)]
docs: fix syntax.

2 years agodocs: fix CI workflow.
whitequark [Tue, 30 Jun 2020 22:28:12 +0000 (22:28 +0000)]
docs: fix CI workflow.

2 years agodocs: explain that `pip3 install -e` should be run after pulling.
whitequark [Tue, 30 Jun 2020 22:26:54 +0000 (22:26 +0000)]
docs: explain that `pip3 install -e` should be run after pulling.

2 years agoAdd (heavily work in progress) documentation.
whitequark [Mon, 27 Apr 2020 07:21:31 +0000 (07:21 +0000)]
Add (heavily work in progress) documentation.

To render correctly, the docs require:
 * pygments/pygments#1441

2 years agomanually add import_metadata, import_resources
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:16:18 +0000 (14:16 +0000)]
manually add import_metadata, import_resources

2 years agoDon't use pkg_resources.
whitequark [Tue, 30 Jun 2020 22:08:59 +0000 (22:08 +0000)]
Don't use pkg_resources.

This package is deprecated and introduces a massive amount of startup
latency. On my machine with 264 installed Python packages, it reduces
the time required to `import nmigen` from ~100ms to ~200ms.

2 years agolib.cdc: update PulseSynchronizer to follow conventions.
whitequark [Sun, 28 Jun 2020 05:17:33 +0000 (05:17 +0000)]
lib.cdc: update PulseSynchronizer to follow conventions.

Fixes #370.

2 years agoback.pysim: simplify.
whitequark [Sun, 28 Jun 2020 05:04:16 +0000 (05:04 +0000)]
back.pysim: simplify.

Remove _EvalContext, which was a level of indirection serving almost
no purpose. (The only case where it would be useful is repeatedly
resetting a simulation that, each time it is reset, would create new
signals to communicate with between coroutine processes. In that case
the signal states would not be persisted in _SimulatorState, but
would be removed with the _EvalContext that is recreated each time
the simulation is reset. But this could be solved with a weak map
instead.)

This regresses simulator startup time by 10-15% for unknown reasons
but is necessary to align pysim and future cxxsim.

2 years ago_yosys: handle unparseable versions
Alan Green [Tue, 23 Jun 2020 12:12:02 +0000 (22:12 +1000)]
_yosys: handle unparseable versions

Do not use yosys binaries with unparseable version numbers. This ensures
that nmigen always knows what version of yosys it is generating RTLIL
for.

The effect of this change is that if the version number of the system
yosys is unparsable, nmigen will attempt to fallback to the builtin
Yosys.

Fixes #409.

2 years agovendor.lattice_machxo2: add back as a compatibility shim.
whitequark [Sun, 21 Jun 2020 17:28:01 +0000 (17:28 +0000)]
vendor.lattice_machxo2: add back as a compatibility shim.

2 years agovendor.lattice_machxo*: add MachXO3L support.
Gwenhael Goavec-Merou [Sun, 21 Jun 2020 17:24:47 +0000 (19:24 +0200)]
vendor.lattice_machxo*: add MachXO3L support.

2 years agoback.verilog: refactor Yosys script generation. NFCI.
whitequark [Sun, 14 Jun 2020 09:38:32 +0000 (09:38 +0000)]
back.verilog: refactor Yosys script generation. NFCI.

In commit 5f30bcbb, back.cxxsim gained a nicer way to generate
a script; this commit brings it to back.verilog too.

2 years agoback.cxxrtl: allow injecting black boxes.
whitequark [Sun, 14 Jun 2020 09:25:54 +0000 (09:25 +0000)]
back.cxxrtl: allow injecting black boxes.

2 years ago_yosys: add a way to retrieve Yosys data directory.
whitequark [Sun, 14 Jun 2020 00:04:18 +0000 (00:04 +0000)]
_yosys: add a way to retrieve Yosys data directory.

This is important for CXXRTL, since that's where its include files
are located.

2 years ago_yosys: fix typo in error message.
whitequark [Sun, 14 Jun 2020 00:03:36 +0000 (00:03 +0000)]
_yosys: fix typo in error message.