yosys.git
2 years agopast_ad initial value setting
Miodrag Milanovic [Sat, 2 Apr 2022 08:59:15 +0000 (10:59 +0200)]
past_ad initial value setting

2 years agosetInitState can be only one altering values
Miodrag Milanovic [Sat, 2 Apr 2022 08:34:11 +0000 (10:34 +0200)]
setInitState can be only one altering values

2 years agoSet past_d value for init state
Miodrag Milanovic [Sat, 2 Apr 2022 08:33:41 +0000 (10:33 +0200)]
Set past_d value for init state

2 years agoMerge pull request #3264 from jix/invalid_ff_dcinit_merge
Jannis Harder [Sat, 2 Apr 2022 10:41:28 +0000 (12:41 +0200)]
Merge pull request #3264 from jix/invalid_ff_dcinit_merge

opt_merge: Add `-keepdc` option required for formal verification

2 years agoBump version
github-actions[bot] [Sat, 2 Apr 2022 00:13:41 +0000 (00:13 +0000)]
Bump version

2 years agoopt_merge: Add `-keepdc` option required for formal verification
Jannis Harder [Fri, 1 Apr 2022 19:03:20 +0000 (21:03 +0200)]
opt_merge: Add `-keepdc` option required for formal verification

The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.

The keepdc option of `opt` is passed along to `opt_merge` now.

2 years agoMerge pull request #3263 from YosysHQ/micko/clk2ff_init
Miodrag Milanović [Fri, 1 Apr 2022 17:37:02 +0000 (19:37 +0200)]
Merge pull request #3263 from YosysHQ/micko/clk2ff_init

Set init values for wrapped  async control signals

2 years agoSet init values for wrapped async control signals
Miodrag Milanovic [Fri, 1 Apr 2022 15:44:00 +0000 (17:44 +0200)]
Set init values for wrapped async control signals

2 years agoMerge pull request #3262 from YosysHQ/micko/verific_hiernet
Miodrag Milanović [Fri, 1 Apr 2022 10:58:09 +0000 (12:58 +0200)]
Merge pull request #3262 from YosysHQ/micko/verific_hiernet

Preserve internal wires for external nets

2 years agoPreserve internal wires for external nets
Miodrag Milanovic [Fri, 1 Apr 2022 10:07:15 +0000 (12:07 +0200)]
Preserve internal wires for external nets

2 years agoBump version
github-actions[bot] [Fri, 1 Apr 2022 01:25:19 +0000 (01:25 +0000)]
Bump version

2 years agoMerge pull request #3256 from YosysHQ/micko/aiw_multiclock
Miodrag Milanović [Thu, 31 Mar 2022 13:45:30 +0000 (15:45 +0200)]
Merge pull request #3256 from YosysHQ/micko/aiw_multiclock

Support memories in aiw and multiclock

2 years ago Support memories in aiw and multiclock
Miodrag Milanovic [Thu, 31 Mar 2022 11:10:13 +0000 (13:10 +0200)]
 Support memories in aiw and multiclock

2 years agoBump version
github-actions[bot] [Thu, 31 Mar 2022 01:15:49 +0000 (01:15 +0000)]
Bump version

2 years agoMerge pull request #3259 from YosysHQ/micko/verific_valgrind
Miodrag Milanović [Wed, 30 Mar 2022 15:29:40 +0000 (17:29 +0200)]
Merge pull request #3259 from YosysHQ/micko/verific_valgrind

Fix valgrind tests when using verific

2 years agoFix valgrind tests when using verific
Miodrag Milanovic [Wed, 30 Mar 2022 15:25:53 +0000 (17:25 +0200)]
Fix valgrind tests when using verific

2 years agoMerge pull request #3260 from YosysHQ/micko/proper_scopename
Miodrag Milanović [Wed, 30 Mar 2022 14:51:27 +0000 (16:51 +0200)]
Merge pull request #3260 from YosysHQ/micko/proper_scopename

Proper scope naming from FST

2 years agoProper scope naming from FST
Miodrag Milanovic [Wed, 30 Mar 2022 13:55:15 +0000 (15:55 +0200)]
Proper scope naming from FST

2 years agoMerge pull request #3250 from YosysHQ/micko/verific_consistent
Miodrag Milanović [Wed, 30 Mar 2022 09:03:14 +0000 (11:03 +0200)]
Merge pull request #3250 from YosysHQ/micko/verific_consistent

Import Verific netlist in consistent order

2 years agoBump version
github-actions[bot] [Wed, 30 Mar 2022 01:17:20 +0000 (01:17 +0000)]
Bump version

2 years agoMerge pull request #3258 from jix/fix-no-assertions
Miodrag Milanović [Tue, 29 Mar 2022 19:20:07 +0000 (21:20 +0200)]
Merge pull request #3258 from jix/fix-no-assertions

smtbmc: fix bmc with no assertions

2 years agosmtbmc: fix bmc with no assertions
Jannis Harder [Tue, 29 Mar 2022 18:41:50 +0000 (20:41 +0200)]
smtbmc: fix bmc with no assertions

this was broken by the `--keep-going` changes

2 years agoBump version
github-actions[bot] [Tue, 29 Mar 2022 00:16:12 +0000 (00:16 +0000)]
Bump version

2 years agokernel/mem: Only use FF init in read-first emu for mem with init
Marcelina Kościelnicka [Mon, 28 Mar 2022 14:14:56 +0000 (16:14 +0200)]
kernel/mem: Only use FF init in read-first emu for mem with init

2 years agoMerge pull request #3253 from jix/smtbmc-nodeepcopy
Jannis Harder [Mon, 28 Mar 2022 14:59:26 +0000 (16:59 +0200)]
Merge pull request #3253 from jix/smtbmc-nodeepcopy

smtbmc: Avoid unnecessary deep copies during unrolling

2 years agoMerge pull request #3247 from jix/smtbmc-keepgoing
Jannis Harder [Mon, 28 Mar 2022 14:58:41 +0000 (16:58 +0200)]
Merge pull request #3247 from jix/smtbmc-keepgoing

smtbmc `--keep-going`

2 years agoMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
Lofty [Mon, 28 Mar 2022 14:51:04 +0000 (15:51 +0100)]
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs

abc9: add flow3mfs script

2 years agoMerge pull request #3246 from YosysHQ/gatecat/timing-derive-fix
Lofty [Mon, 28 Mar 2022 14:50:53 +0000 (15:50 +0100)]
Merge pull request #3246 from YosysHQ/gatecat/timing-derive-fix

abc9_ops: Also derive blackboxes with timing info

2 years agogowin: Add oscillator primitives
Tim Pambor [Sun, 27 Mar 2022 15:18:13 +0000 (17:18 +0200)]
gowin: Add oscillator primitives

2 years agosmtbmc: Avoid unnecessary deep copies during unrolling
Jannis Harder [Mon, 28 Mar 2022 10:37:11 +0000 (12:37 +0200)]
smtbmc: Avoid unnecessary deep copies during unrolling

2 years agoUpdate URL to zlib
Miodrag Milanović [Mon, 28 Mar 2022 09:05:30 +0000 (11:05 +0200)]
Update URL to zlib

2 years agoProperly mark modules imported
Miodrag Milanovic [Sat, 26 Mar 2022 08:43:51 +0000 (09:43 +0100)]
Properly mark modules imported

2 years agoBump version
github-actions[bot] [Sat, 26 Mar 2022 00:13:30 +0000 (00:13 +0000)]
Bump version

2 years agoAdd some more reserve calls to RTLIL::Const
NotAFile [Fri, 25 Mar 2022 17:46:34 +0000 (18:46 +0100)]
Add some more reserve calls to RTLIL::Const

This results in a slight ~0.22% total speedup synthesizing vexriscv

2 years agoMerge pull request #3249 from YosysHQ/micko/no_startoffset
Miodrag Milanović [Fri, 25 Mar 2022 13:29:21 +0000 (14:29 +0100)]
Merge pull request #3249 from YosysHQ/micko/no_startoffset

Add -no-startoffset option to write_aiger

2 years agoImport verific netlist in consistent order
Miodrag Milanovic [Fri, 25 Mar 2022 12:44:16 +0000 (13:44 +0100)]
Import verific netlist in consistent order

2 years agoAdd -no-startoffset option to write_aiger
Miodrag Milanovic [Fri, 25 Mar 2022 07:44:45 +0000 (08:44 +0100)]
Add -no-startoffset option to write_aiger

2 years agoBump version
github-actions[bot] [Fri, 25 Mar 2022 00:13:36 +0000 (00:13 +0000)]
Bump version

2 years agoMerge pull request #3243 from nakengelhardt/fix_aiw_comment
Miodrag Milanović [Thu, 24 Mar 2022 16:25:09 +0000 (17:25 +0100)]
Merge pull request #3243 from nakengelhardt/fix_aiw_comment

smtbmc: ignore # comment lines

2 years agoyosys-smtbmc: Option to keep going after failed assertions in BMC mode
Jannis Harder [Mon, 21 Mar 2022 17:26:27 +0000 (18:26 +0100)]
yosys-smtbmc: Option to keep going after failed assertions in BMC mode

2 years agoyosys-smtbmc: Fix typo in help text, remove trailing whitespace
Jannis Harder [Mon, 21 Mar 2022 17:27:05 +0000 (18:27 +0100)]
yosys-smtbmc: Fix typo in help text, remove trailing whitespace

2 years agoabc9_ops: Also derive blackboxes with timing info
gatecat [Thu, 24 Mar 2022 14:34:34 +0000 (14:34 +0000)]
abc9_ops: Also derive blackboxes with timing info

Signed-off-by: gatecat <gatecat@ds0.me>
2 years agoignore # comment lines
N. Engelhardt [Thu, 24 Mar 2022 09:19:17 +0000 (10:19 +0100)]
ignore # comment lines

2 years agoBump version
github-actions[bot] [Wed, 23 Mar 2022 00:14:55 +0000 (00:14 +0000)]
Bump version

2 years agoUpdate abc with latest fix
Miodrag Milanovic [Tue, 22 Mar 2022 17:47:48 +0000 (18:47 +0100)]
Update abc with latest fix

2 years agoProper SigBit forming in sim
Miodrag Milanovic [Tue, 22 Mar 2022 13:43:18 +0000 (14:43 +0100)]
Proper SigBit forming in sim

2 years agoProper SigBit forming in sim
Miodrag Milanovic [Tue, 22 Mar 2022 13:22:32 +0000 (14:22 +0100)]
Proper SigBit forming in sim

2 years agoBump version
github-actions[bot] [Tue, 22 Mar 2022 00:15:19 +0000 (00:15 +0000)]
Bump version

2 years agoxilinx: Add RAMB4* blackboxes
Marcelina Kościelnicka [Mon, 21 Mar 2022 10:38:21 +0000 (11:38 +0100)]
xilinx: Add RAMB4* blackboxes

2 years agoBump version
github-actions[bot] [Sat, 19 Mar 2022 00:12:57 +0000 (00:12 +0000)]
Bump version

2 years agoMore verbose warnings
Miodrag Milanovic [Fri, 18 Mar 2022 13:47:35 +0000 (14:47 +0100)]
More verbose warnings

2 years agoMerge pull request #3236 from YosysHQ/micko/tb_initial
Miodrag Milanović [Thu, 17 Mar 2022 16:15:36 +0000 (17:15 +0100)]
Merge pull request #3236 from YosysHQ/micko/tb_initial

Recognize registers and set initial state for them in tb

2 years agoBump version
github-actions[bot] [Thu, 17 Mar 2022 00:13:12 +0000 (00:13 +0000)]
Bump version

2 years agoRecognize registers and set initial state for them in tb
Miodrag Milanovic [Wed, 16 Mar 2022 13:35:39 +0000 (14:35 +0100)]
Recognize registers and set initial state for them in tb

2 years agoUpdate sim help message.
Miodrag Milanovic [Wed, 16 Mar 2022 06:55:57 +0000 (07:55 +0100)]
Update sim help message.

2 years agoBump version
github-actions[bot] [Tue, 15 Mar 2022 01:09:43 +0000 (01:09 +0000)]
Bump version

2 years agogowin: add support for Double Data Rate primitives
YRabbit [Mon, 14 Mar 2022 21:41:30 +0000 (07:41 +1000)]
gowin: add support for Double Data Rate primitives

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2 years agoMerge pull request #3232 from YosysHQ/micko/fst2tb
Miodrag Milanović [Mon, 14 Mar 2022 19:01:55 +0000 (20:01 +0100)]
Merge pull request #3232 from YosysHQ/micko/fst2tb

Added fst2tb pass for generating testbench

2 years agoAdded fst2tb pass for generating testbench
Miodrag Milanovic [Mon, 14 Mar 2022 18:06:29 +0000 (19:06 +0100)]
Added fst2tb pass for generating testbench

2 years agoMerge pull request #3213 from antonblanchard/abc-typo
Claire Xen [Mon, 14 Mar 2022 15:05:23 +0000 (16:05 +0100)]
Merge pull request #3213 from antonblanchard/abc-typo

abc: Fix {I} and {P} substitution

2 years agoProper example code
Miodrag Milanovic [Mon, 14 Mar 2022 14:39:11 +0000 (15:39 +0100)]
Proper example code

2 years agoBump version
github-actions[bot] [Sat, 12 Mar 2022 01:02:32 +0000 (01:02 +0000)]
Bump version

2 years agoMerge pull request #3229 from YosysHQ/micko/sim_date
Miodrag Milanović [Fri, 11 Mar 2022 18:02:57 +0000 (19:02 +0100)]
Merge pull request #3229 from YosysHQ/micko/sim_date

Add date parameter to enable full date/time and version info

2 years agoMerge pull request #3222 from zachjs/prune-linux-ci
Miodrag Milanović [Fri, 11 Mar 2022 18:02:37 +0000 (19:02 +0100)]
Merge pull request #3222 from zachjs/prune-linux-ci

Prune Linux CI builds

2 years agoMerge pull request #3228 from YosysHQ/micko/disable_tests
Miodrag Milanović [Fri, 11 Mar 2022 18:02:19 +0000 (19:02 +0100)]
Merge pull request #3228 from YosysHQ/micko/disable_tests

Disable tests on most of platforms

2 years agoAdd "sim -q" option
Claire Xenia Wolf [Fri, 11 Mar 2022 15:26:11 +0000 (16:26 +0100)]
Add "sim -q" option

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2 years agoAdd date parameter to enable full date/time and version info
Miodrag Milanovic [Fri, 11 Mar 2022 15:01:59 +0000 (16:01 +0100)]
Add date parameter to enable full date/time and version info

2 years agoSmall fix in "sim" help message
Claire Xenia Wolf [Fri, 11 Mar 2022 14:36:23 +0000 (15:36 +0100)]
Small fix in "sim" help message

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2 years agoMerge pull request #3226 from YosysHQ/micko/btor2witness
Miodrag Milanović [Fri, 11 Mar 2022 14:29:34 +0000 (15:29 +0100)]
Merge pull request #3226 from YosysHQ/micko/btor2witness

Sim support for btor2 witness files

2 years agoFstData already do conversion to VCD
Miodrag Milanovic [Fri, 11 Mar 2022 14:21:36 +0000 (15:21 +0100)]
FstData already do conversion to VCD

2 years agoSupport cell name in btor witness file
Miodrag Milanovic [Fri, 11 Mar 2022 14:11:14 +0000 (15:11 +0100)]
Support cell name in btor witness file

2 years agoFix handling of some formal cells in btor back-end
Claire Xenia Wolf [Fri, 11 Mar 2022 13:21:12 +0000 (14:21 +0100)]
Fix handling of some formal cells in btor back-end

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2 years agohandle state names of $anyconst and $anyseq
Miodrag Milanovic [Fri, 11 Mar 2022 13:04:02 +0000 (14:04 +0100)]
handle state names of $anyconst and $anyseq

2 years agoPrune Linux CI builds
Zachary Snow [Tue, 1 Mar 2022 09:20:59 +0000 (10:20 +0100)]
Prune Linux CI builds

2 years agoProper write of memory data
Miodrag Milanovic [Fri, 11 Mar 2022 10:19:53 +0000 (11:19 +0100)]
Proper write of memory data

2 years agoDisable tests on most of platforms
Miodrag Milanovic [Thu, 10 Mar 2022 10:05:00 +0000 (11:05 +0100)]
Disable tests on most of platforms

2 years agoBump version
github-actions[bot] [Thu, 10 Mar 2022 01:11:52 +0000 (01:11 +0000)]
Bump version

2 years agointel_alm: M10K write-enable is negative-true
Lofty [Wed, 9 Mar 2022 16:40:32 +0000 (16:40 +0000)]
intel_alm: M10K write-enable is negative-true

2 years agoStart work on memory init
Miodrag Milanovic [Wed, 9 Mar 2022 17:34:02 +0000 (18:34 +0100)]
Start work on memory init

2 years agoFixes and error check
Miodrag Milanovic [Wed, 9 Mar 2022 08:48:29 +0000 (09:48 +0100)]
Fixes and error check

2 years agocleanup
Miodrag Milanovic [Mon, 7 Mar 2022 15:32:32 +0000 (16:32 +0100)]
cleanup

2 years agoError checks for aiger witness
Miodrag Milanovic [Mon, 7 Mar 2022 14:00:14 +0000 (15:00 +0100)]
Error checks for aiger witness

2 years agobtor2 witness co-simulation
Miodrag Milanovic [Mon, 7 Mar 2022 12:59:36 +0000 (13:59 +0100)]
btor2 witness co-simulation

2 years agoMerge pull request #3210 from rqou/json-signed
Miodrag Milanović [Mon, 7 Mar 2022 08:41:25 +0000 (09:41 +0100)]
Merge pull request #3210 from rqou/json-signed

json: Add help message for `signed` field

2 years agoBump version
github-actions[bot] [Sat, 5 Mar 2022 01:06:31 +0000 (01:06 +0000)]
Bump version

2 years agoMerge pull request #3186 from nakengelhardt/smtbmc_sby_print_id
Miodrag Milanović [Fri, 4 Mar 2022 15:39:12 +0000 (16:39 +0100)]
Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id

add argument for printing cell names in yosys-smtbmc

2 years agoMerge pull request #3206 from YosysHQ/micko/quote_remove
Miodrag Milanović [Fri, 4 Mar 2022 15:39:01 +0000 (16:39 +0100)]
Merge pull request #3206 from YosysHQ/micko/quote_remove

Remove quotes if any from attribute

2 years agoMerge pull request #3207 from nakengelhardt/json_escape_quotes
Miodrag Milanović [Fri, 4 Mar 2022 12:57:32 +0000 (13:57 +0100)]
Merge pull request #3207 from nakengelhardt/json_escape_quotes

fix handling of escaped chars in json backend and frontend (mostly)

2 years agoNext dev cycle
Miodrag Milanovic [Fri, 4 Mar 2022 10:37:18 +0000 (11:37 +0100)]
Next dev cycle

2 years agoRelease version 0.15 yosys-0.15
Miodrag Milanovic [Fri, 4 Mar 2022 10:36:03 +0000 (11:36 +0100)]
Release version 0.15

2 years agoUpdate ABC
Miodrag Milanovic [Fri, 4 Mar 2022 10:32:15 +0000 (11:32 +0100)]
Update ABC

2 years agoUpdate documentation
Miodrag Milanovic [Fri, 4 Mar 2022 09:56:33 +0000 (10:56 +0100)]
Update documentation

2 years agoMerge pull request #3219 from YosysHQ/micko/quick_vcd
Miodrag Milanović [Fri, 4 Mar 2022 09:42:14 +0000 (10:42 +0100)]
Merge pull request #3219 from YosysHQ/micko/quick_vcd

VCD reader support by using external tool

2 years agoMerge pull request #3220 from YosysHQ/claire/simstuff
Miodrag Milanović [Fri, 4 Mar 2022 09:41:02 +0000 (10:41 +0100)]
Merge pull request #3220 from YosysHQ/claire/simstuff

Add writing of aiw files to "sim" command

2 years agoBump version
github-actions[bot] [Thu, 3 Mar 2022 01:08:21 +0000 (01:08 +0000)]
Bump version

2 years agoAdd option to ignore X only signals in output
Miodrag Milanovic [Wed, 2 Mar 2022 15:02:13 +0000 (16:02 +0100)]
Add option to ignore X only signals in output

2 years agoWrite simulation files after simulation is performed
Miodrag Milanovic [Wed, 2 Mar 2022 14:23:07 +0000 (15:23 +0100)]
Write simulation files after simulation is performed

2 years agoUpdate CHANGELOG
Miodrag Milanovic [Wed, 2 Mar 2022 13:26:15 +0000 (14:26 +0100)]
Update CHANGELOG

2 years agoMerge pull request #3224 from YosysHQ/micko/refactor
Claire Xen [Wed, 2 Mar 2022 12:52:18 +0000 (13:52 +0100)]
Merge pull request #3224 from YosysHQ/micko/refactor

Micko/refactor

2 years agoCleanup
Miodrag Milanovic [Wed, 2 Mar 2022 08:39:22 +0000 (09:39 +0100)]
Cleanup