nmigen.git
5 years agohdl, back: add and use SignalSet/SignalDict.
whitequark [Mon, 17 Dec 2018 17:21:12 +0000 (17:21 +0000)]
hdl, back: add and use SignalSet/SignalDict.

5 years agohdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
whitequark [Mon, 17 Dec 2018 17:13:08 +0000 (17:13 +0000)]
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.

5 years agoback.rtlil: update for Yosys master.
whitequark [Mon, 17 Dec 2018 15:50:43 +0000 (15:50 +0000)]
back.rtlil: update for Yosys master.

5 years agoback.rtlil: implement Array.
whitequark [Mon, 17 Dec 2018 01:15:23 +0000 (01:15 +0000)]
back.rtlil: implement Array.

5 years agoback.rtlil: implement Part.
whitequark [Mon, 17 Dec 2018 01:05:08 +0000 (01:05 +0000)]
back.rtlil: implement Part.

5 years agoback.rtlil: handle reset_less domains.
whitequark [Sun, 16 Dec 2018 23:52:47 +0000 (23:52 +0000)]
back.rtlil: handle reset_less domains.

5 years agohdl.dsl: add clock domain support.
whitequark [Sun, 16 Dec 2018 23:51:24 +0000 (23:51 +0000)]
hdl.dsl: add clock domain support.

5 years agohdl.dsl: cleanup. NFC.
whitequark [Sun, 16 Dec 2018 23:44:00 +0000 (23:44 +0000)]
hdl.dsl: cleanup. NFC.

5 years agoback.rtlil: extract _StatementCompiler. NFC.
whitequark [Sun, 16 Dec 2018 22:26:58 +0000 (22:26 +0000)]
back.rtlil: extract _StatementCompiler. NFC.

5 years agoback.rtlil: simplify. NFC.
whitequark [Sun, 16 Dec 2018 21:00:00 +0000 (21:00 +0000)]
back.rtlil: simplify. NFC.

5 years agoback.rtlil: properly escape strings in attributes.
whitequark [Sun, 16 Dec 2018 20:27:15 +0000 (20:27 +0000)]
back.rtlil: properly escape strings in attributes.

5 years agoREADME: mention Yosys requirement.
whitequark [Sun, 16 Dec 2018 18:09:01 +0000 (18:09 +0000)]
README: mention Yosys requirement.

5 years agoback.rtlil: prepare for Yosys sigspec slicing improvements.
whitequark [Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)]
back.rtlil: prepare for Yosys sigspec slicing improvements.

See YosysHQ/yosys#741.

5 years agocompat.fhdl.structure: only convert to bool in If/Elif if necessary.
whitequark [Sun, 16 Dec 2018 17:41:42 +0000 (17:41 +0000)]
compat.fhdl.structure: only convert to bool in If/Elif if necessary.

5 years agoback.rtlil: avoid illegal slices.
whitequark [Sun, 16 Dec 2018 17:41:11 +0000 (17:41 +0000)]
back.rtlil: avoid illegal slices.

Not sure what to do with {} [] on LHS yet--fix Yosys?

5 years agoback.rtlil: use slicing to match shape when reducing width.
whitequark [Sun, 16 Dec 2018 16:20:45 +0000 (16:20 +0000)]
back.rtlil: use slicing to match shape when reducing width.

5 years agoback.rtlil: don't emit a slice if all bits are used.
whitequark [Sun, 16 Dec 2018 16:05:38 +0000 (16:05 +0000)]
back.rtlil: don't emit a slice if all bits are used.

5 years agoback.rtlil: reorganize value compiler into LHS/RHS.
whitequark [Sun, 16 Dec 2018 13:30:20 +0000 (13:30 +0000)]
back.rtlil: reorganize value compiler into LHS/RHS.

This also implements Cat on LHS.

5 years agoback.rtlil: fix naming. NFC.
whitequark [Sun, 16 Dec 2018 11:26:31 +0000 (11:26 +0000)]
back.rtlil: fix naming. NFC.

5 years agohdl.xfrm: separate AST traversal from AST identity mapping.
whitequark [Sun, 16 Dec 2018 11:24:23 +0000 (11:24 +0000)]
hdl.xfrm: separate AST traversal from AST identity mapping.

This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.

5 years agocompat.fhdl: reexport Array.
whitequark [Sun, 16 Dec 2018 10:38:25 +0000 (10:38 +0000)]
compat.fhdl: reexport Array.

5 years agoback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
whitequark [Sun, 16 Dec 2018 10:31:42 +0000 (10:31 +0000)]
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.

5 years agotest.sim: generalize assertOperator. NFC.
whitequark [Sat, 15 Dec 2018 21:08:29 +0000 (21:08 +0000)]
test.sim: generalize assertOperator. NFC.

5 years agoback.pysim: add (stub) LHSValueCompiler.
whitequark [Sat, 15 Dec 2018 21:01:38 +0000 (21:01 +0000)]
back.pysim: add (stub) LHSValueCompiler.

5 years agoback.pysim: implement Part.
whitequark [Sat, 15 Dec 2018 20:58:06 +0000 (20:58 +0000)]
back.pysim: implement Part.

5 years agoexamples: rename clkdiv/ctrl to ctr/ctr_ce.
whitequark [Sat, 15 Dec 2018 20:42:52 +0000 (20:42 +0000)]
examples: rename clkdiv/ctrl to ctr/ctr_ce.

5 years agodoc: update COMPAT_SUMMARY.
whitequark [Sat, 15 Dec 2018 20:40:51 +0000 (20:40 +0000)]
doc: update COMPAT_SUMMARY.

5 years agoback.pysim: implement ArrayProxy.
whitequark [Sat, 15 Dec 2018 19:37:36 +0000 (19:37 +0000)]
back.pysim: implement ArrayProxy.

5 years agohdl.ast: implement Array and ArrayProxy.
whitequark [Sat, 15 Dec 2018 17:16:22 +0000 (17:16 +0000)]
hdl.ast: implement Array and ArrayProxy.

5 years agoLower Python version requirement to 3.6.
whitequark [Sat, 15 Dec 2018 17:03:23 +0000 (17:03 +0000)]
Lower Python version requirement to 3.6.

5 years agohdl: appropriately rename tests. NFC.
whitequark [Sat, 15 Dec 2018 16:13:53 +0000 (16:13 +0000)]
hdl: appropriately rename tests. NFC.

5 years agohdl.ast: improve ClockSignal, ResetSignal documentation.
whitequark [Sat, 15 Dec 2018 14:58:31 +0000 (14:58 +0000)]
hdl.ast: improve ClockSignal, ResetSignal documentation.

5 years agoRename fhdl→hdl, genlib→lib.
whitequark [Sat, 15 Dec 2018 14:23:42 +0000 (14:23 +0000)]
Rename fhdl→hdl, genlib→lib.

5 years agoMove star imports to make `from nmigen import *` usable.
whitequark [Sat, 15 Dec 2018 14:20:10 +0000 (14:20 +0000)]
Move star imports to make `from nmigen import *` usable.

5 years agodoc: fix some Markdown awkwardness.
whitequark [Sat, 15 Dec 2018 12:07:56 +0000 (12:07 +0000)]
doc: fix some Markdown awkwardness.

5 years agodoc: update COMPAT_SUMMARY to reflect actual status.
whitequark [Sat, 15 Dec 2018 12:04:52 +0000 (12:04 +0000)]
doc: update COMPAT_SUMMARY to reflect actual status.

5 years agoDetermine Migen's API surface and document compatibility summary.
whitequark [Sat, 15 Dec 2018 11:51:09 +0000 (11:51 +0000)]
Determine Migen's API surface and document compatibility summary.

This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.

5 years agopyback.sim: test Slice, Cat, Repl.
whitequark [Sat, 15 Dec 2018 10:09:14 +0000 (10:09 +0000)]
pyback.sim: test Slice, Cat, Repl.

5 years agofhdl.ast, back.pysim: implement shifts.
whitequark [Sat, 15 Dec 2018 09:58:30 +0000 (09:58 +0000)]
fhdl.ast, back.pysim: implement shifts.

5 years agofhdl.ast: refactor Operator.shape(). NFC.
whitequark [Sat, 15 Dec 2018 09:46:20 +0000 (09:46 +0000)]
fhdl.ast: refactor Operator.shape(). NFC.

5 years agoConsistently use '{!r}' in and only in TypeError messages.
whitequark [Sat, 15 Dec 2018 09:31:58 +0000 (09:31 +0000)]
Consistently use '{!r}' in and only in TypeError messages.

5 years agofhdl.ir: test iter_comb(), iter_sync() and iter_signals().
whitequark [Sat, 15 Dec 2018 09:26:36 +0000 (09:26 +0000)]
fhdl.ir: test iter_comb(), iter_sync() and iter_signals().

5 years agofhdl.ir: fix incorrect uses of positive to say non-negative.
whitequark [Sat, 15 Dec 2018 09:19:26 +0000 (09:19 +0000)]
fhdl.ir: fix incorrect uses of positive to say non-negative.

Also test Part and Slice properly.

5 years agocompat.fhdl.structure: handle If/Elif with multi-bit condition.
whitequark [Sat, 15 Dec 2018 00:10:54 +0000 (00:10 +0000)]
compat.fhdl.structure: handle If/Elif with multi-bit condition.

5 years agocompat.fhdl.module: allow adding native submodules to compat modules.
whitequark [Fri, 14 Dec 2018 23:40:15 +0000 (23:40 +0000)]
compat.fhdl.module: allow adding native submodules to compat modules.

5 years agoFix deprecations in Python 3.7.
whitequark [Fri, 14 Dec 2018 23:56:26 +0000 (23:56 +0000)]
Fix deprecations in Python 3.7.

5 years agoback.pysim: preserve process locations through add_sync_process().
whitequark [Fri, 14 Dec 2018 23:27:36 +0000 (23:27 +0000)]
back.pysim: preserve process locations through add_sync_process().

5 years agofhdl.ast: clean up stub error messages. NFC.
whitequark [Fri, 14 Dec 2018 22:54:07 +0000 (22:54 +0000)]
fhdl.ast: clean up stub error messages. NFC.

5 years agofhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
whitequark [Fri, 14 Dec 2018 22:47:58 +0000 (22:47 +0000)]
fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.

Fixes #5.

5 years agofhdl.ir: Fragment.{drive→add_driver}
whitequark [Fri, 14 Dec 2018 20:58:29 +0000 (20:58 +0000)]
fhdl.ir: Fragment.{drive→add_driver}

5 years agoback.pysim: count delta cycles separately to avoid clock drift.
whitequark [Fri, 14 Dec 2018 20:52:41 +0000 (20:52 +0000)]
back.pysim: count delta cycles separately to avoid clock drift.

5 years agoback.pysim: simplify.
whitequark [Fri, 14 Dec 2018 20:26:52 +0000 (20:26 +0000)]
back.pysim: simplify.

5 years agoback.pysim: revert 70ebc6f2.
whitequark [Fri, 14 Dec 2018 19:46:08 +0000 (19:46 +0000)]
back.pysim: revert 70ebc6f2.

5 years agoback.pysim: fix implicit boolean conversion.
whitequark [Fri, 14 Dec 2018 19:08:06 +0000 (19:08 +0000)]
back.pysim: fix implicit boolean conversion.

5 years agoback.pysim: squash one level of hierarchy.
whitequark [Fri, 14 Dec 2018 18:53:21 +0000 (18:53 +0000)]
back.pysim: squash one level of hierarchy.

There's really no point in the "top" node.

5 years agoback.pysim: implement blocking assignment semantics correctly.
whitequark [Fri, 14 Dec 2018 18:47:12 +0000 (18:47 +0000)]
back.pysim: implement blocking assignment semantics correctly.

5 years agoback.pysim: undriven sync signals should return to previous value.
whitequark [Fri, 14 Dec 2018 17:25:48 +0000 (17:25 +0000)]
back.pysim: undriven sync signals should return to previous value.

5 years agoback.pysim: in simulator sync processes, start by waiting for a tick.
whitequark [Fri, 14 Dec 2018 17:05:11 +0000 (17:05 +0000)]
back.pysim: in simulator sync processes, start by waiting for a tick.

This matches Migen behavior and also makes more sense.

5 years agoback.pysim: make initial phase configurable.
whitequark [Fri, 14 Dec 2018 16:46:16 +0000 (16:46 +0000)]
back.pysim: make initial phase configurable.

5 years agocompat.sim: match clock period.
whitequark [Fri, 14 Dec 2018 16:39:52 +0000 (16:39 +0000)]
compat.sim: match clock period.

5 years agocompat: add run_simulation shim.
whitequark [Fri, 14 Dec 2018 16:22:18 +0000 (16:22 +0000)]
compat: add run_simulation shim.

5 years agopysim.back: fix add_sync_process wrapper to handle signals correctly.
whitequark [Fri, 14 Dec 2018 16:21:53 +0000 (16:21 +0000)]
pysim.back: fix add_sync_process wrapper to handle signals correctly.

5 years agocompat.fhdl.module: fix specials.
whitequark [Fri, 14 Dec 2018 16:14:08 +0000 (16:14 +0000)]
compat.fhdl.module: fix specials.

5 years agocompat: add fhdl.specials.TSTriple shim.
whitequark [Fri, 14 Dec 2018 16:00:10 +0000 (16:00 +0000)]
compat: add fhdl.specials.TSTriple shim.

5 years agogenlib.io: import TSTriple from Migen.
whitequark [Fri, 14 Dec 2018 16:09:26 +0000 (16:09 +0000)]
genlib.io: import TSTriple from Migen.

5 years agofhdl.ast: fix Switch with constant test.
whitequark [Fri, 14 Dec 2018 16:07:25 +0000 (16:07 +0000)]
fhdl.ast: fix Switch with constant test.

5 years agocompat: add genlib.cdc.MultiReg shim.
whitequark [Fri, 14 Dec 2018 15:59:49 +0000 (15:59 +0000)]
compat: add genlib.cdc.MultiReg shim.

5 years agocompat.fhdl.module: update deprecation messages.
whitequark [Fri, 14 Dec 2018 16:00:31 +0000 (16:00 +0000)]
compat.fhdl.module: update deprecation messages.

5 years agoback.pysim: Simulator({gtkw_signals→traces}=).
whitequark [Fri, 14 Dec 2018 15:23:22 +0000 (15:23 +0000)]
back.pysim: Simulator({gtkw_signals→traces}=).

5 years agoback.pysim: better naming. NFC.
whitequark [Fri, 14 Dec 2018 15:21:13 +0000 (15:21 +0000)]
back.pysim: better naming. NFC.

5 years agoTravis: install pyvcd.
whitequark [Fri, 14 Dec 2018 14:47:03 +0000 (14:47 +0000)]
Travis: install pyvcd.

5 years agoback.pysim: implement most operators and add tests.
whitequark [Fri, 14 Dec 2018 14:21:22 +0000 (14:21 +0000)]
back.pysim: implement most operators and add tests.

5 years agoback.pysim: close .vcd/.gtkw files on context manager exit.
whitequark [Fri, 14 Dec 2018 13:59:03 +0000 (13:59 +0000)]
back.pysim: close .vcd/.gtkw files on context manager exit.

5 years agoback.pysim: show more legible names for processes in errors.
whitequark [Fri, 14 Dec 2018 13:50:19 +0000 (13:50 +0000)]
back.pysim: show more legible names for processes in errors.

5 years agoback.pysim: throw exceptions back at processes.
whitequark [Fri, 14 Dec 2018 13:43:25 +0000 (13:43 +0000)]
back.pysim: throw exceptions back at processes.

5 years agoback.pysim: add gtkw traces even more robustly.
whitequark [Fri, 14 Dec 2018 13:43:08 +0000 (13:43 +0000)]
back.pysim: add gtkw traces even more robustly.

5 years agoback.pysim: accept (and evaluate) generator functions.
whitequark [Fri, 14 Dec 2018 13:30:09 +0000 (13:30 +0000)]
back.pysim: accept (and evaluate) generator functions.

5 years agoback.pysim: skip VCD signal population if VCD is not requested.
whitequark [Fri, 14 Dec 2018 13:25:51 +0000 (13:25 +0000)]
back.pysim: skip VCD signal population if VCD is not requested.

5 years agoback.pysim: allow processes to evaluate expressions.
whitequark [Fri, 14 Dec 2018 13:21:58 +0000 (13:21 +0000)]
back.pysim: allow processes to evaluate expressions.

5 years agofhdl.ir: oops, we defined DomainError twice.
whitequark [Fri, 14 Dec 2018 12:59:54 +0000 (12:59 +0000)]
fhdl.ir: oops, we defined DomainError twice.

5 years agoback.pysim: more general clean-up.
whitequark [Fri, 14 Dec 2018 12:42:39 +0000 (12:42 +0000)]
back.pysim: more general clean-up.

5 years agoback.pysim: general clean-up.
whitequark [Fri, 14 Dec 2018 12:21:48 +0000 (12:21 +0000)]
back.pysim: general clean-up.

5 years agoback.pysim: accept any valid assignments from processes.
whitequark [Fri, 14 Dec 2018 12:18:41 +0000 (12:18 +0000)]
back.pysim: accept any valid assignments from processes.

5 years agoback.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
whitequark [Fri, 14 Dec 2018 10:57:13 +0000 (10:57 +0000)]
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.

5 years agofhdl.xfrm: implement DomainLowerer.
whitequark [Fri, 14 Dec 2018 10:56:53 +0000 (10:56 +0000)]
fhdl.xfrm: implement DomainLowerer.

5 years agoback.pysim: undriven comb signals should return to reset value.
whitequark [Fri, 14 Dec 2018 09:12:38 +0000 (09:12 +0000)]
back.pysim: undriven comb signals should return to reset value.

5 years agoast, back.pysim: allow specifying user-defined decoders for signals.
whitequark [Fri, 14 Dec 2018 09:02:29 +0000 (09:02 +0000)]
ast, back.pysim: allow specifying user-defined decoders for signals.

5 years agoback.pysim: fix completely broken codegen for Switch.
whitequark [Fri, 14 Dec 2018 08:51:36 +0000 (08:51 +0000)]
back.pysim: fix completely broken codegen for Switch.

5 years agoback.pysim: raise an exception if delta cycles blow a process deadline.
whitequark [Fri, 14 Dec 2018 08:10:21 +0000 (08:10 +0000)]
back.pysim: raise an exception if delta cycles blow a process deadline.

5 years agoback.pysim: if requested, write a gtkw file with a useful preset.
whitequark [Fri, 14 Dec 2018 08:04:29 +0000 (08:04 +0000)]
back.pysim: if requested, write a gtkw file with a useful preset.

5 years agoback.pysim: explain how delta cycles work.
whitequark [Fri, 14 Dec 2018 07:26:26 +0000 (07:26 +0000)]
back.pysim: explain how delta cycles work.

5 years agoback.pysim: delay clock processes by one half period.
whitequark [Fri, 14 Dec 2018 05:17:43 +0000 (05:17 +0000)]
back.pysim: delay clock processes by one half period.

Makes it easier to see initial delta cycles.

5 years agoback.pysim: implement "sync processes", like migen.sim generators.
whitequark [Fri, 14 Dec 2018 05:13:58 +0000 (05:13 +0000)]
back.pysim: implement "sync processes", like migen.sim generators.

5 years agoback.pysim: allow suspending processes until a tick in a domain.
whitequark [Fri, 14 Dec 2018 04:33:06 +0000 (04:33 +0000)]
back.pysim: allow suspending processes until a tick in a domain.

5 years agoback.pysim: use bare ints for signal values (-5% runtime).
whitequark [Fri, 14 Dec 2018 03:05:57 +0000 (03:05 +0000)]
back.pysim: use bare ints for signal values (-5% runtime).

5 years agosetup: add missing import.
whitequark [Fri, 14 Dec 2018 02:32:37 +0000 (02:32 +0000)]
setup: add missing import.

5 years agoback.pysim: collect handlers before running (-5% runtime).
whitequark [Thu, 13 Dec 2018 18:34:44 +0000 (18:34 +0000)]
back.pysim: collect handlers before running (-5% runtime).

5 years agoback.pysim: allow multiple registered handlers per signal.
whitequark [Thu, 13 Dec 2018 18:28:11 +0000 (18:28 +0000)]
back.pysim: allow multiple registered handlers per signal.

5 years agoback.pysim: fix handling of process termination.
whitequark [Thu, 13 Dec 2018 18:17:58 +0000 (18:17 +0000)]
back.pysim: fix handling of process termination.

5 years agoback.pysim: new simulator backend (WIP).
whitequark [Thu, 13 Dec 2018 18:00:05 +0000 (18:00 +0000)]
back.pysim: new simulator backend (WIP).