intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.

v2: Introduce extra tgl_swsb_sbid() constructor (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/fs/gen12: Add codegen support for the SYNC instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/ir/gen12: Add SYNC hardware instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Don't set thread control, it's gone.

An effect similar to the one formerly provided by setting thread
control to "switch" can be achieved now by setting a RegDist of 1 on
the SWSB field.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Don't set DD control, it's gone.

A future lowering pass will simulate the same behavior originally
provided by NoDDChk/NoDDClr at the IR level by using appropriate SWSB
annotations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Use SEND instruction for split sends.

The new SEND instruction behaves like the former SENDS instruction.
The original single-payload SEND instruction is gone.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen SEND descriptor regions correctly.

The SEND instruction is now four-source.  The descriptor is no longer
part of source 1, so avoid touching it to avoid corruption while
initializing the descriptor.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen pathological SEND source and destination regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen control flow instructions correctly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen three-source instruction source and destination regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Fix codegen of immediate source regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Add Gen12 opcode descriptions to the table.

Quite a lot of churn because the encoding of most hardware opcodes has
changed unfortunately.

v2: Split dot-product description fixes to separate patch (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen11+: Mark dot product opcodes as unsupported on opcode_descs table.

These instructions have been removed from the hardware.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/eu/gen12: Implement datatype binary encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement immediate 64 bit constant encoding.

On Gen12, 64 bit immediate constants are loaded in reverse order. Lower
32 bit gets loaded from bit 96-127 and higher 32 bits from 64-95 in
instruction encoding.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/gen12: Implement compact instruction binary encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/gen12: Implement indirect region binary encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/gen12: Implement SEND instruction binary encoding.

v2: Fix off-by-one upper GET_BITS() bound, combine 25-29 and 30-31
    descriptor fields (Ken).  Shorten name of GEN12_MD() macro, drop
    some removed TS message descriptor fields (Jordan).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement control flow instruction binary encoding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement three-source instruction binary encoding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement basic instruction binary encoding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_bits().

These caught a few bugs during the development of this series.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.

The encoding of almost every instruction field has changed in Gen12,
so this involves adding a Gen12+ bitfield spec to every brw_inst
macro.  In addition some new macros are required to handle certain
discontiguous and variable-length fields.

This commit doesn't actually include the Gen12 updated bitfield specs,
only the macros are extended here for reviewability.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Rename FDC() to FFDC() and FDC1() to FDC() for consistency with
    the existing F() and FF() macros.

intel/ir: Represent physical edge of unconditional CONTINUE instruction.

This edge doesn't exist in the original scalar program, but it
represents a potential control flow path the EU will take in cases
where control flow isn't uniform across channels of the same SIMD
thread.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Represent physical edge of ELSE instruction.

This edge doesn't exist in the original scalar program, but it
represents a potential control flow path the EU will take in cases
where the condition isn't uniform across channels of the same SIMD
thread.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Represent logical edge of BREAK instruction.

Currently only the physical back-edge is represented, which
incidentally also leads to the exit block of the loop, but we need the
direct logical edge in addition for our logical CFG representation to
be complete.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Add helper function to push block onto CFG analysis stack.

Requested-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Represent physical and logical subsets of the CFG.

This represents two control flow graphs in the same cfg_t data
structure: The physical CFG that will include all possible control
flow paths the EU can physically take, and the logical CFG restricted
to the control flow paths that exist in the original scalar program.
The latter is a subset of the former because in case of divergence the
SIMD vectorized program will take control flow paths that aren't part
of the original scalar program.

The bblock_link constructor and bblock_t::add_successor() now take a
"kind" parameter that specifies whether the edge is purely physical or
whether it's part of both the logical and physical CFGs (a logical
edge is of course always guaranteed to be in the physical CFG as
well).  bblock_t::is_predecessor_of() and ::is_successor_of() also
take a kind parameter specifying which CFG is being queried.  The '~>'
notation will be used now in order to represent purely physical edges
in IR dumps.

This commit doesn't actually add nor remove any edges from the CFG
(the only edges marked as purely physical here are the two WHILE loop
ones that already existed).  Optimization passes should continue using
the same (incomplete) physical CFG they were using before until
they're fixed to do something smarter in a later commit, so this
shouldn't lead to any functional changes.

v2: Remove tabs from lines changed in this file (Caio).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Drop hard-coded correspondence between IR and HW opcodes.

Having the IR opcodes locked to their hardware representation is risky
because it causes opcodes as different as BRC and IFF to compare equal
at the IR level (luckily the back-end only ever uses one opcode from
each group, right now), and it prevents us from supporting
instructions that change their hardware representation across
generations, which will become a problem on Gen12+ platforms.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.

Change brw_inst_set_opcode() and brw_inst_opcode() to call
brw_opcode_encode/decode() transparently in order to translate between
hardware and IR opcodes, and update the EU compaction code in order to
do the same as needed, so we can eventually drop the one-to-one
correspondence between hardware and IR opcodes.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.

This rewrites the current opcode description tables as a more compact
flat data structure.  The purpose is to allow efficient constant-time
look-up by either HW or IR opcode, which will allow us to drop the
hard-coded correspondence between HW and IR opcodes -- See the next
commits for the rationale.

brw_eu.c is now built as C++ source so we can take advantage of
pointers to member in order to make the look-up function work
regardless of the opcode_desc member used as look-up key.

v2: Optimize devinfo struct comparison (Caio)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).

The brw_inst opcode accessors are going away in one of the following
commits.  We could potentially replace them with the new helpers that
do opcode remapping, but that would lead to a circular dependency
between brw_inst.h and brw_eu.h.  This way we also avoid ordering
issues that can cause the semantics of the ex_desc accessors to change
depending on whether the ex_desc field is set after or before the
opcode instruction field.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Fix constness of implied_mrf_writes() argument.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Define is_send() convenience IR helper.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Define is_payload() method of the IR instruction class.

This is required because SEND message payload sources are fetched
asynchronously by the hardware, which can lead to WaR data corruption
on Gen12+ platforms if not handled specially by the compiler to
guarantee proper synchronization.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Teach fs_inst::is_send_from_grf() about some missing send-like instructions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

nir/dead_cf: Remove dead control flow after infinite loops.

And after discard-only loops. Otherwise we end up with dead code
which confuses nir_repair_ssa into adding a whole bunch of uses
of undefined. However, for derefs, we sometimes always expect to
get a variable instead of undefined.

Fixes dEQP-VK.graphicsfuzz.write-red-in-loop-nest on radv.

Fixes: c832820ce95 "nir/dead_cf: Repair SSA if the pass makes progress"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1928
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

aco: don't use p_as_uniform for vgpr sampler/image indices

p_as_uniform can get CSE'd, which can be incorrect and break some
dEQP-VK.descriptor_indexing.* tests.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: implement divergent vulkan_resource_index

Fixes the UBO/SSBO dEQP-VK.descriptor_indexing.* tests

v2: remove bld.copy() usage

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: readfirstlane vgpr pointers in convert_pointer_to_64_bit()

This can happen when bcsel is used between the results of two
vulkan_resource_index. It's also probably needed for non-uniform
descriptor indexing

Fixes dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.compute.reads_opselect_two_buffers

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: use can_accept_constant in valu_can_accept_literal

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: don't apply sgprs/constants to read/write lane instructions

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

nir/lower_input_attachments: pass on non-uniform access flag

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_non_uniform: lower image/texture instructions taking derefs

v2: always assert on the texture/sampler handle's num_components
v3: replicate the deref inside the loop
v4: remove a case of useless line wrapping

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

etnaviv: rework etna_resource_create tiling choice

Now that the base resource is allowed to be incompatible with PE, we can
make a smarter choice of tiling mode to avoid allocating a PE compatible
base that is never used for regular textures. This affects GPUs like GC2000
where there is no tiling compatible with both PE and TE.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: rework compatible render base

For PE-incompatible layouts, use a mechanism similar to what texture does
to create a compatible base resource.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: get addressing mode from tiling layout

Remove the "addressing_mode" state, which is currently set incorrectly, and
instead deduce the addressing mode from the tiling layout.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: clear texture cache and flush ts when texture is modified

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: output the same shader-db format as freedreno, v3d and intel

This lets us reuse their report.py.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

etnaviv: nir: start to make use of compile_error(..)

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

gitlab-ci: Disable meson-mingw32-x86_64 job again for now

The wrapdb.mesonbuild.com SSL certificate expired, causing the job to
fail: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/731864

Switching to http:// doesn't avoid it:
https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/732043

gitlab-ci: Add .use-debian-10 template

It simplifies the definitions of jobs using the Debian 10 image.

The needs: was previously missing from the llvmpipe/softpipe test jobs,
so they could spuriously run if the debian-10 job failed or was
cancelled.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

gitlab-ci: Remove redundant .meson-cross template script

It was identical to the one inherited from the .meson-build template.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

gallivm: fix coroutines on aarch64 with llvm 8

The coroutine split pass is missing a dependency before LLVM 9.0,
and fails to initialise properly if the CallGraphWrapperPass hasn't
be initialised earlier (x86 does it due to some of it's passes
requiring it).

This is a workaround for llvm 8 (coroutines are only supported in 8
and higher). It adds another pass that has a dependency on the pass
the coroutines split requires. This pass shouldn't have any raal
effects.

Fixes: d32690b43c9 (gallivm: add coroutine pass manager support)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe: add support for tg4 component selection.

This is needed as part of GLES3.1 and helps for ARB_gpu_shader5.

Fixes: KHR-GLES31.core.texture_gather.* cases
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/glsl: add support for alternate TG4 encoding.

This will encode the component selection value (0, 1, 2, 3) into
the X swizzle of the sampler, if the driver requests it.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add a a new cap for changing the TGSI TG4 instruction encoding

Accessing the TG4 component via immediates in the llvmpipe backend is quite
messy (like really messy). Roland suggested we change the instruction encoding,
so introduce a cap to allow the component to be selected to be store in the
sampler swizzle, which should be otherwise unused.

I could probably switch all drivers over, but virgl would need some work that
I'd prefer not to rush it.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm/sample: add gather component selection to the key.

This allows for component selection to work as per ARB_gpu_shader5/GLES3.1

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe: increase max texture size to 2GB

The 1GB limit was arbitrary, increase this to 2GB (which is the max
possible without code changes).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gitlab-ci: Add a mingw x86_64 job

Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

appveyor: Add support for meson as well as scons on windows

This job uses the vs2017 backend of meson (msbuild) as opposed to the
ninja backend used on MacOS and Linux.

v7: - rebase on master
    - remove llvm (we'll add that back later)
    - remove cygwin (we'll add that back later too)
v6: - rebase on master, including the addition of cygwin
    - consolidate 3 appveyor patches into this one patch
v5  - use the new b_vscrt option instead of manually specifying the crt
v4: - rebase on python3 generators
    - cache meson wraps
    - Build x86 instead of x86_64, since that's what the pre-built LLVM
      is
    - update to vs2017 from vs2015
    - set the default-library to static
    - use the new vscrt override
    - add the /m switch to msbuild to make the build somewhat faster

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

docs: update meson docs for windows

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

glsl/tests: Handle no-exec errors

Currently meson doesn't correctly handle passing compiled binaries to
scripts in tests. This patch looks to the future (0.53) when meson will
have this functionality, but also immediately it fixes these tests in
cross compiles by causing them to return 77, which meson interprets as
skip.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson/util: Don't run string_buffer tests on mingw

They succeed with MSVC but not with MinGW. I don't understand why they
fail.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: glcpp tests are expected to fail on windows

v2: - Exclude the tests rather than xfail them

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: only build timspec test if timespec is available

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: don't error on formaters with mingw

MSVC is generally happy, but mingw errors. I've spent as much time
(several days) trying to squash all of these warnings and I'm done with
it, just leave them as warnings with MinGW.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: add msvc compat args to swr

This has always been present in the scons build, so it should be in
the meson build as well.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: maintain names of shared API libraries

Mesa uses the lib prefix, and doesn't use a version for it's dynamic
libraries, which meson defaults to.

v2: - this patch

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: don't build or run mesa-sha1 test on windows

It crashes hard (pop-up window and all).

v2: - Change comment to FIXME

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: disable graw tests on mingw

I can't figure out why symbols are being exposed that shouldn't.

v2: - change comment to FIXME

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: don't build gallium trivial tests on windows

They require the pipe-loaders, which require xmlconfig, which doesn't
build with msvc.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Set visibility and compat args for graw

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Add msvc compat args to util/tests

To keep this building with msvc

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Add idep_getopt for tests

There are quite a few tests that require getopt, when using MSVC we need
to use the bundled version of getopt since there isn't a system version.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: don't define USE_ELF_TLS for windows

Because the macros for exporting dll symbols and using TLS are mutually
exclusive.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: add switches for SWR with MSVC

This makes two changes for SWR,

The first is that it reorders the arguments to try to put the ICL ones
first. This is required to support older versions of meson that don't
add enough "error in this case" switches to ICL, which causes it to
happy accept -mavx (for example) even though it doesn't support them,
resulting in compilation failures.

The second is to fix the names of the libraries, setting the soversion
to '' will result in <lib>.dll, instead of <lib>-0.dll. Since these are
not versioned dll's, but implement an internal API we should communicate
that. It's also what scons does.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: disable sse4.1 optimizations with msvc

There isn't an obvious command line switch here, /arch:AVX *might* be
the right thing, but meson doesn't know what to do here either and
leaves the -msse4.1 and -mstackrealign.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: force inclusion of inttypes.h for glcpp with msvc

Because we provide a copy if MSVC doesn't, and we need it to make flex
do what we want.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Add support for using win_flex and win_bison on windows

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: don't look for rt on windows

v6: - Minor refactor

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: fix pipe-loader compilation for windows

v2: - Add missing D to pound define
    - Simply define the variable rather than set it to 1 (mirrors
      android.mk not scons)

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

util/xmlconfig: include strndup.h for windows

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Don't check for posix_memalign on windows

There's a mingw bug for this, it exports __builtin_posix_memalign but
not posix_memalign, so the check will succeed, but compiling will fail.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: fix gallium-osmesa to build for windows

v2: - set so_version to '' (only affects windows)
    - always set lib prefix to 'lib', even on msvc
v5: - key NO_EXPORTS on shared glapi instead of gles.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: build graw-gdi target

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: build libgl-gdi target

v4: - Fix check for broken mingw (should be for x86 not x86_64)
    - Add comment about why check is needed

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: build wgl state tracker

v4: - Handle enable gles properly
    - Add comments about what various #defines do
v5: - key NO_EXPORTS on shared glapi instead of gles.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: build gallium gdi winsys

v6: - use null_dep instead of []

Reviewed-by: Eric Anholt <eric@anholt.net> (v5)
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Add necessary defines for mesa_gallium on windows

v4: - Retain scons comments for windows specific defines
v5: - key GLAPI_NO_EXPORTS off of shared-glapi instead of gles

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

meson: Add windows defines to glapi

These are needed to control the export or symbols due to differences
between the way windows and *nix handle symbol exports.

Reviewed-by: Eric Anholt <eric@anholt.net> (v2)
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
v5: - key NO_EXPORT off of shared-glapi instead of gles

meson: add windows compiler checks and libraries

v4: - Fix typo in warning code (4246 -> 4267)
    - Copy comments from scons for what MSVC warnings codes do
    - Merge linker argument changes into this commit
v5: - Add /GR- on windows if LLVM is build without rtti (equivalent to
      GCc's -fno-rtti')
    - Add /wd4291, which is catching the same hting that
    -Wno-non-virtual-dtor is on GCC/Clang

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

util: use _WIN32 instead of WIN32

MinGW defines only _WIN32, but doesn't have fcntl, so we need to use the
windows path.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>

freedreno/ir3: handle multi component alu src when propagating shifts

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/ir3: drop unused param

Signed-off-by: Rob Clark <robdclark@chromium.org>

clover: fix the nir_serialize build failure

Fixes: dd4cc56ebd0 "nir: add a strip parameter to nir_serialize"

llvmpipe/draw: handle UBOs that are < 16 bytes.

Not sure if this is a bug in the user or not, but some CTS
tests fail due to using an 8 byte constant buffer.

Fixes: KHR-GLES31.core.layout_binding.block_layout_binding_block_VertexShader
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe/draw: fix image sizes for vertex/geometry shaders.

since images are a single level, minify before passing the w/h
to draw.

Fixes: KHR-GLES31.core.shader_image_size.basic-nonMS-vs-*
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe: make texture buffer offset alignment == 16

Due to use vmovdqa instructions in the asm, which require 16-byte
aligned buffers.

This fixes a crash in
KHR-GLES31.core.texture_buffer.texture_buffer_texture_buffer_range

Reviewed-by: Roland Scheidegger <sroland@vmware.com>