Remove non needed check in bmp_iter_set_init (PR tree-optimization/82669).

2017-11-09  Martin Liska  <mliska@suse.cz>

PR tree-optimization/82669
* sbitmap.h (bmp_iter_set_init): Remove non needed check.

From-SVN: r254567

[multiple changes]

2017-11-09  Jerome Lambourg  <lambourg@adacore.com>

* sigtramp-qnx.c: Fix obvious typo.

2017-11-09  Doug Rupp  <rupp@adacore.com>

* libgnarl/s-taprop__linux.adb (Monotonic_Clock): Minor reformatting.

2017-11-09  Ed Schonberg  <schonberg@adacore.com>

* sem_res.adb (Resolve): If expression is an entity whose type has
implicit dereference, generate reference to it, because no reference is
generated for an overloaded entity during analysis, given that its
identity may not be known.

2017-11-09  Javier Miranda  <miranda@adacore.com>

* exp_disp.adb (Expand_Interface_Thunk): Replace substraction of
offset-to-top field by addition.
(Make_Secondary_DT): Initialize the offset-to-top field with a negative
offset.
* exp_ch3.adb (Build_Offset_To_Top_Function): Build functions that
return a negative offset-to-top value.
(Initialize_Tag): Invoke runtime services Set_Dynamic_Offset_To_Top and
Set_Static_Offset_To_Top passing a negative offet-to-top value;
initialize also the offset-to-top field with a negative offset.
* libgnat/a-tags.adb (Base_Address): Displace the pointer by means of
an addition since the offset-to-top field is now a negative value.
(Displace): Displace the pointer to the object means of a substraction
since it is now a negative value.
(Set_Dynamic_Offset_to_top): Displace the pointer to the object by
means of a substraction since it is now a negative value.

2017-11-09  Eric Botcazou  <ebotcazou@adacore.com>

* gnat1drv.adb (Gnat1drv): Call Errout.Finalize (Last_Call => True)
before Errout.Output_Messages also in the case of compilation errors.

2017-11-09  Javier Miranda  <miranda@adacore.com>

* doc/gnat_ugn/the_gnat_compilation_model.rst (Interfacing with C++ at
the Class Level): Fix error interfacing with C strings.
* gnat_ugn.texi: Regenerate.

2017-11-09  Jerome Lambourg  <lambourg@adacore.com>

* system-qnx-aarch64.ads: Fix the priority constants.
* s-osinte__qnx.ads: Fix constants for handling the locking protocols
and scheduling.
* s-osinte__qnx.adb: New file , prevents the use of priority 0 that
corresponds to an idle priority on QNX.

2017-11-09  Piotr Trojanek  <trojanek@adacore.com>

* sem_prag.adb, sem_util.adb, sem_elab.adb: Fix minor typos in
comments.

From-SVN: r254566

[multiple changes]

2017-11-09  Piotr Trojanek  <trojanek@adacore.com>

* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Ignore loop parameters
in expression funtions that are expanded into variables.

2017-11-09  Piotr Trojanek  <trojanek@adacore.com>

* sem_util.adb: Minor whitespace cleanup.

2017-11-09  Jerome Lambourg  <lambourg@adacore.com>

* libgnarl/s-taprop__qnx.adb: Refine aarch64-qnx. Use the POSIX
s-taprop version rather than a custom one.
* sigtramp-qnx.c (aarch64-qnx): Implement the signal trampoline.

From-SVN: r254563

GCOV: support multiple functions per a line (PR gcov-profile/48463)

2017-11-09  Martin Liska  <mliska@suse.cz>

PR gcov-profile/48463
* coverage.c (coverage_begin_function): Output also end locus
of a function and information whether the function is
artificial.
* gcov-dump.c (tag_function): Parse and print the information.
* gcov.c (INCLUDE_MAP): Add include.
(INCLUDE_SET): Likewise.
(struct line_info): Move earlier in the source file because
of vector<line_info> in function_info structure.
(line_info::line_info): Likewise.
(line_info::has_block): Likewise.
(struct source_info): Add new member index.
(source_info::get_functions_at_location): New function.
(function_info::group_line_p): New function.
(output_intermediate_line): New function.
(output_intermediate_file): Use the mentioned function.
(struct function_start): New.
(struct function_start_pair_hash): Likewise.
(process_file): Add code that identifies group functions.
Assign lines either to global or function scope.
(generate_results): Skip artificial functions.
(find_source): Assign index for each source file.
(read_graph_file): Read new flag artificial and end_line.
(add_line_counts): Assign it either to global of function scope.
(accumulate_line_counts): Isolate core of the function to
accumulate_line_info and call it for both function and global
scope lines.
(accumulate_line_info): New function.
(output_line_beginning): Fix GNU coding style.
(print_source_line): New function.
(output_line_details): Likewise.
(output_function_details): Likewise.
(output_lines): Iterate both source (global) scope and function
scope.
(struct function_line_start_cmp): New class.
* doc/gcov.texi: Reflect changes in documentation.

From-SVN: r254562

re PR debug/82837 (ICE in output_operand: invalid expression as operand)

PR debug/82837
* dwarf2out.c (const_ok_for_output_1): Reject NEG in addition to NOT.
(mem_loc_descriptor): Handle (const (neg (...))) as (neg (const (...)))
and similarly for not instead of neg.

* gcc.dg/debug/dwarf2/pr82837.c: New test.

From-SVN: r254561

Add option to force indirect calls for x86

This patch adds a -mforce-indirect-call option to force all calls
or tail calls on x86_64 between functions to indirect. This is similar to the
large code model, but doesn't affect jumps inside functions, so has much
less run time overhead.

This is useful with Intel Processor Trace (PT). PT has precise timing
for indirect calls/jumps, but not for direct ones. So if we can force
them to indirect it allows to time every function relatively accurately
(minus the overhead of the indirect branch)

Without this short functions often don't see a timing update and cannot
be measured.

The timing requires at least Skylake or Goldmont based CPUs.

I made it an option. Originally I tried to make it a new code model,
but since it can be combined with other code models (medium, pic, kernel
etc.) this turned out to be too many combinations.

For example with gcc. This first column is a ns time stamp for the
functions.

$ perf record -e intel_pt/noretcomp=1,cyc=1,cyc_thresh=1/u ./cc1 -O3 hello.c
$ perf script --itrace=cr -F callindent,time,sym,addr --ns  | sed -n 180000,182000p | less
...
1184596.432756920:                             build_int_cst                        =>           79c9de c_common_nodes_and_builtins
1184596.432756921:                             tree_cons                            =>           ee2080 tree_cons
1184596.432756938:                                 ggc_internal_alloc               =>           80f3e0 ggc_internal_alloc
1184596.432756951:                                     memset@plt                   =>           598af0 memset@plt
1184596.432756967:                                     __memset_avx2_unaligned_erms =>           80f605 ggc_internal_alloc
1184596.432756969:                                 ggc_internal_alloc               =>           ee20a2 tree_cons
1184596.432756973:                             tree_cons                            =>           79c9f4 c_common_nodes_and_builtins
1184596.432756974:                             build_int_cst                        =>           ef9a40 build_int_cst
1184596.432756996:                                 wide_int_to_tree                 =>           ef93a0 wide_int_to_tree
1184596.432757000:                                     wi::force_to_size            =>           f48f70 wi::force_to_size
1184596.432757005:                                     canonize                     =>           ef94de wide_int_to_tree
1184596.432757021:                                     get_int_cst_ext_nunits       =>           ee1960 get_int_cst_ext_nunits
1184596.432757026:                                     get_int_cst_ext_nunits       =>           ef94fe wide_int_to_tree
1184596.432757042:                                     tree_int_cst_elt_check       =>           83e310 tree_int_cst_elt_check
1184596.432757044:                                     tree_int_cst_elt_check       =>           ef9761 wide_int_to_tree
1184596.432757046:                                 wide_int_to_tree                 =>           ef9a9b build_int_cst

gcc/:
2017-11-08  Andi Kleen  <ak@linux.intel.com>

* config/i386/i386.opt: Add -mforce-indirect-call.
* config/i386/predicates.md: Check for flag_force_indirect_call.
* doc/invoke.texi: Document -mforce-indirect-call

gcc/testsuite/:
2017-11-08  Andi Kleen  <ak@linux.intel.com>

* gcc.target/i386/force-indirect-call-1.c: New test.
* gcc.target/i386/force-indirect-call-2.c: New test.
* gcc.target/i386/force-indirect-call-3.c: New test.

From-SVN: r254560

Daily bump.

From-SVN: r254559

re PR fortran/82841 (Segfault in gfc_simplify_transfer)

2017-11-08  Steven G. Kargl  <kargl@kgcc.gnu.org>

PR Fortran/82841
* simplify.c(gfc_simplify_transfer): Do not dereference a NULL pointer.
Unwrap a short line.

2017-11-08  Steven G. Kargl  <kargl@kgcc.gnu.org>

PR Fortran/82841
* gfortran.dg/transfer_simplify_11.f90: new test.

From-SVN: r254555

RISC-V: Fix build error

  - This build error was indroduced by "RISC-V: Implement movmemsi"
    and "RISC-V: Support -mpreferred-stack-boundary flag"

gcc/ChangeLog

2017-11-08  Kito Cheng  <kito.cheng@gmail.com>

        * config/riscv/riscv-protos.h (riscv_slow_unaligned_access_p):
        New extern.
        (MOVE_RATIO): Use riscv_slow_unaligned_access_p.
        config/riscv/riscv.c (predict.h): New include.
        (riscv_slow_unaligned_access_p): No longer static.
        (riscv_block_move_straight): Add require.
        config/riscv/riscv-protos.h (riscv_hard_regno_nregs): Delete.

From-SVN: r254554

re PR fortran/82884 (ICE in gfc_resolve_character_array_constructor, at fortran/array.c:2069)

2017-11-08  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/82884
* arith.c (gfc_hollerith2character): Clear pad.

2017-11-08  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/82884
* gfortran.dg/hollerith_character_array_constructor.f90: New test.

From-SVN: r254553

re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)

PR target/82855
* config/i386/sse.md (<avx512>_eq<mode>3<mask_scalar_merge_name>,
<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Use
nonimmediate_operand predicate for operand 1 instead of
register_operand.

From-SVN: r254552

[AArch64] Add STP pattern to store a vec_concat of two 64-bit registers

On top of the previous vec_merge simplifications [1] we can add this pattern to perform
a store of a vec_concat of two 64-bit values in distinct registers as an STP.
This avoids constructing such a vector explicitly in a register and storing it as
a Q register.
This way for the code in the testcase we can generate:

construct_lane_1:
        ldp     d1, d0, [x0]
        fmov    d3, 1.0e+0
        fmov    d2, 2.0e+0
        fadd    d4, d1, d3
        fadd    d5, d0, d2
        stp     d4, d5, [x1, 32]
        ret

construct_lane_2:
        ldp     x2, x0, [x0]
        add     x3, x2, 1
        add     x4, x0, 2
        stp     x3, x4, [x1, 32]
        ret

instead of the current:
construct_lane_1:
        ldp     d0, d1, [x0]
        fmov    d3, 1.0e+0
        fmov    d2, 2.0e+0
        fadd    d0, d0, d3
        fadd    d1, d1, d2
        dup     v0.2d, v0.d[0]
        ins     v0.d[1], v1.d[0]
        str     q0, [x1, 32]
        ret

construct_lane_2:
        ldp     x2, x3, [x0]
        add     x0, x2, 1
        add     x2, x3, 2
        dup     v0.2d, x0
        ins     v0.d[1], x2
        str     q0, [x1, 32]
        ret

Bootstrapped and tested on aarch64-none-linux-gnu.

[1] https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00272.html
    https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00273.html
    https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00274.html

* config/aarch64/aarch64-simd.md (store_pair_lanes<mode>):
New pattern.
* config/aarch64/constraints.md (Uml): New constraint.
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): New
predicate.

* gcc.target/aarch64/store_v2vec_lanes.c: New test.

From-SVN: r254551

[simplify-rtx] Simplify vec_merge of vec_duplicates into vec_concat

Another vec_merge simplification that's missing from simplify-rtx.c is transforming
a vec_merge of two vec_duplicates. For example:
(set (reg:V2DF 80)
    (vec_merge:V2DF (vec_duplicate:V2DF (reg:DF 84))
        (vec_duplicate:V2DF (reg:DF 81))
        (const_int 2)))

Can be transformed into the simpler:
(set (reg:V2DF 80)
    (vec_concat:V2DF (reg:DF 81)
                (reg:DF 84)))

I believe this should always be beneficial.
I'm still looking into finding a small testcase demonstrating this, but on aarch64 SPEC
I've seen this eliminate some really bizzare codegen where GCC was generating nonsense like:
  ldr q18, [sp, 448]
  ins v18.d[0], v23.d[0]
  ins v18.d[1], v22.d[0]

With q18 being pushed and popped off the stack in the prologue and epilogue of the function!
These are large files from SPEC that I haven't been able to analyse yet as to why GCC even attempts
to do that, but with this patch it doesn't try to load a register and overwrite all its lanes.
This patch shaves off about 5k of code size from zeusmp on aarch64 at -O3, so I believe it's a good
thing to do.

* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
of two vec_duplicates into a vec_concat.

From-SVN: r254550

vec_merge + vec_duplicate + vec_concat simplification

Another vec_merge simplification that's missing is transforming:
(vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N))
into
(vec_concat x z) if N == 1 (0b01) or
(vec_concat y x) if N == 2 (0b10)

For the testcase in this patch on aarch64 this allows us to try matching during combine the pattern:
(set (reg:V2DI 78 [ x ])
    (vec_concat:V2DI
        (mem:DI (reg/v/f:DI 76 [ y ]) [1 *y_4(D)+0 S8 A64])
        (mem:DI (plus:DI (reg/v/f:DI 76 [ y ])
                (const_int 8 [0x8])) [1 MEM[(long long int *)y_4(D) + 8B]+0 S8 A64])))

rather than the more complex:
(set (reg:V2DI 78 [ x ])
    (vec_merge:V2DI (vec_duplicate:V2DI (mem:DI (plus:DI (reg/v/f:DI 76 [ y ])
                    (const_int 8 [0x8])) [1 MEM[(long long int *)y_4(D) + 8B]+0 S8 A64]))
        (vec_duplicate:V2DI (mem:DI (reg/v/f:DI 76 [ y ]) [1 *y_4(D)+0 S8 A64]))
        (const_int 2 [0x2])))

We don't actually have an aarch64 pattern for the simplified version above, but it's a simple enough
form to add, so this patch adds such a pattern that performs a concatenated load of two 64-bit vectors
in adjacent memory locations as a single Q-register LDR. The new aarch64 pattern is needed to demonstrate
the effectiveness of the simplify-rtx change, so I've kept them together as one patch.

Now for the testcase in the patch we can generate:
construct_lanedi:
        ldr     q0, [x0]
        ret

construct_lanedf:
        ldr     q0, [x0]
        ret

instead of:
construct_lanedi:
        ld1r    {v0.2d}, [x0]
        ldr     x0, [x0, 8]
        ins     v0.d[1], x0
        ret

construct_lanedf:
        ld1r    {v0.2d}, [x0]
        ldr     d1, [x0, 8]
        ins     v0.d[1], v1.d[0]
        ret

The new memory constraint Utq is needed because we need to allow only the Q-register addressing modes but
the MEM expressions in the RTL pattern have 64-bit vector modes, and if we don't constrain them they will
allow the D-register addressing modes during register allocation/address mode selection, which will produce
invalid assembly.

Bootstrapped and tested on aarch64-none-linux-gnu.

* simplify-rtx.c (simplify_ternary_operation, VEC_MERGE):
Simplify vec_merge of vec_duplicate and vec_concat.
* config/aarch64/constraints.md (Utq): New constraint.
* config/aarch64/aarch64-simd.md (load_pair_lanes<mode>): New
define_insn.

* gcc.target/aarch64/load_v2vec_lanes_1.c: New test.

From-SVN: r254549

Simplify vec_merge of vec_duplicate with const_vector

I'm trying to improve some of the RTL-level handling of vector lane operations on aarch64 and that
involves dealing with a lot of vec_merge operations. One simplification that I noticed missing
from simplify-rtx are combinations of vec_merge with vec_duplicate.
In this particular case:
(vec_merge (vec_duplicate (X)) (const_vector [A, B]) (const_int N))

which can be replaced with

(vec_concat (X) (B)) if N == 1 (0b01) or
(vec_concat (A) (X)) if N == 2 (0b10).

For the aarch64 testcase in this patch this simplifications allows us to try to combine:
(set (reg:V2DI 77 [ x ])
    (vec_concat:V2DI (mem:DI (reg:DI 0 x0 [ y ]) [1 *y_3(D)+0 S8 A64])
        (const_int 0 [0])))

instead of the more complex:
(set (reg:V2DI 77 [ x ])
    (vec_merge:V2DI (vec_duplicate:V2DI (mem:DI (reg:DI 0 x0 [ y ]) [1 *y_3(D)+0 S8 A64]))
        (const_vector:V2DI [
                (const_int 0 [0])
                (const_int 0 [0])
            ])
        (const_int 1 [0x1])))

For the simplified form above we already have an aarch64 pattern: *aarch64_combinez<mode> which
is missing a DI/DFmode version due to an oversight, so this patch extends that pattern as well to
use the VDC mode iterator that includes DI and DFmode (as well as V2HF which VD_BHSI was missing).
The aarch64 hunk is needed to see the benefit of the simplify-rtx.c hunk, so I didn't split them
into separate patches.

Before this for the testcase we'd generate:
construct_lanedi:
        movi    v0.4s, 0
        ldr     x0, [x0]
        ins     v0.d[0], x0
        ret

construct_lanedf:
        movi    v0.2d, 0
        ldr     d1, [x0]
        ins     v0.d[0], v1.d[0]
        ret

but now we can generate:
construct_lanedi:
        ldr     d0, [x0]
        ret

construct_lanedf:
        ldr     d0, [x0]
        ret

Bootstrapped and tested on aarch64-none-linux-gnu.

* simplify-rtx.c (simplify_ternary_operation, VEC_MERGE):
Simplify vec_merge of vec_duplicate and const_vector.
* config/aarch64/predicates.md (aarch64_simd_or_scalar_imm_zero):
New predicate.
* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Use VDC
mode iterator.  Update predicate on operand 1 to
handle non-const_vec constants.  Delete constraints.
(*aarch64_combinez_be<mode>): Likewise for operand 2.

* gcc.target/aarch64/construct_lane_zero_1.c: New test.

From-SVN: r254548

[multiple changes]

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* lib-xref.ads, lib-xref-spark_specific.adb
(Traverse_Compilation_Unit): Move declaration to package body.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

* exp_spark.adb (Expand_SPARK_N_Object_Renaming_Declaration): Obtain
the type of the renaming from its defining entity, rather then the
subtype mark as there may not be a subtype mark.

2017-11-08  Jerome Lambourg  <lambourg@adacore.com>

* adaint.c, s-oscons-tmplt.c, init.c, libgnat/system-qnx-aarch64.ads,
libgnarl/a-intnam__qnx.ads, libgnarl/s-intman__qnx.adb,
libgnarl/s-osinte__qnx.ads, libgnarl/s-qnx.ads,
libgnarl/s-taprop__qnx.adb, s-oscons-tmplt.c, sigtramp-qnx.c,
terminals.c: Initial port of GNAT for aarch64-qnx

2017-11-08  Elisa Barboni  <barboni@adacore.com>

* exp_util.adb (Find_DIC_Type): Move...
* sem_util.ads, sem_util.adb (Find_DIC_Type): ... here.

2017-11-08  Justin Squirek  <squirek@adacore.com>

* sem_res.adb (Resolve_Allocator): Add info messages corresponding to
the owner and corresponding coextension.

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

* sem_aggr.adb (Resolve_Delta_Aggregate): Divide into the
following separate procedures.
(Resolve_Delta_Array_Aggregate): Previous code form
Resolve_Delta_Aggregate.
(Resolve_Delta_Record_Aggregate): Extend previous code to cover latest
ARG decisions on the legality rules for delta aggregates for records:
in the case of a variant record, components from different variants
cannot be specified in the delta aggregate, and this must be checked
statically.

From-SVN: r254547

[multiple changes]

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_Scope_Record): Remove File_Num component.
* lib-xref-spark_specific.adb (Add_SPARK_Scope): Skip initialization of
removed component.

2017-11-08  Gary Dismukes  <dismukes@adacore.com>

* sem_ch4.adb: Minor typo fix.

From-SVN: r254546

[multiple changes]

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_Scope_Record): Remove Spec_File_Num and
Spec_Scope_Num components.
* spark_xrefs.adb (dspark): Skip pretty-printing to removed components.
* lib-xref-spark_specific.adb (Add_SPARK_Scope): Skip initialization of
removed components.
(Collect_SPARK_Xrefs): Skip setting proper values of removed
components.

2017-11-08  Gary Dismukes  <dismukes@adacore.com>

* exp_ch4.adb (Expand_N_Type_Conversion): Add test that the selector
name is a discriminant in check for unconditional accessibility
violation within instances.

From-SVN: r254545

lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Remove special-case for constants (with variable input).

gcc/ada/

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Remove special-case
for constants (with variable input).
(Is_Constant_Object_Without_Variable_Input): Remove.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

* exp_ch9.adb, sem_disp.adb, sem_util.adb: Minor reformatting.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (Rtype): Remove special-casing of constants for SPARK
cross-references.
(dspark): Remove hardcoded table bound.

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

* sem_ch4.adb (Analyze_Aggregate): For Ada2020 delta aggregates, use
the type of the base of the construct to determine the type (or
candidate interpretations) of the delta aggregate. This allows the
construct to appear in a context that expects a private extension.
* sem_res.adb (Resolve): Handle properly a delta aggregate with an
overloaded base.

gcc/testsuite/

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

* gnat.dg/delta_aggr.adb: New testcase.

From-SVN: r254544

[multiple changes]

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_Xref_Record): Replace file and scope indices
with Entity_Id of the reference.
* spark_xrefs.adb (dspark): Adapt pretty-printing routine.
* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Store Entity_Id of the
reference, not the file and scope indices.

2017-11-08  Arnaud Charlet  <charlet@adacore.com>

* errout.ads (Current_Node): New.
* errout.adb (Error_Msg): Use Current_Node.
* par-ch6.adb, par-ch7.adb, par-ch9.adb, par-util.adb: Set Current_Node
when relevant.
* style.adb: Call Error_Msg_N when possible.

From-SVN: r254543

spark_xrefs.ads (SPARK_Scope_Record): Rename Scope_Id component to Entity.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_Scope_Record): Rename Scope_Id component to
Entity.
* lib-xref-spark_specific.adb, spark_xrefs.adb: Propagate renaming of
the Scope_Id record component.

From-SVN: r254542

spark_xrefs.ads (SPARK_File_Record): Remove string components.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_File_Record): Remove string components.
* spark_xrefs.adb (dspark): Remove pretty-printing of removed
SPARK_File_Record components.
* lib-xref-spark_specific.adb (Add_SPARK_File): Do not store string
representation of files/units.

From-SVN: r254541

lib-xref.ads, [...] (Traverse_Declarations): Remove Inside_Stubs parameter.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* lib-xref.ads, lib-xref-spark_specific.adb (Traverse_Declarations):
Remove Inside_Stubs parameter.

From-SVN: r254540

[multiple changes]

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_Xref_Record): Referenced object is now
represented by Entity_Id.
(SPARK_Scope_Record): Referenced scope (e.g. subprogram) is now
represented by Entity_Id; this information is not repeated as
Scope_Entity.
(Heap): Moved from lib-xref-spark_specific.adb, to reside next to
Name_Of_Heap_Variable.
* spark_xrefs.adb (dspark): Adapt debug routine to above changes in
data types.
* lib-xref-spark_specific.adb: Adapt routines for populating SPARK
scope and xrefs tables to above changes in data types.

2017-11-08  Justin Squirek  <squirek@adacore.com>

* sem_ch8.adb (Mark_Use_Clauses): Add condition to always mark the
primitives of generic actuals.
(Mark_Use_Type): Add recursive call to properly mark class-wide type's
base type clauses as per ARM 8.4 (8.2/3).

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

* sem_ch6.adb (Analyze_Generic_Subprobram_Body): Validate
categorization dependency of the body, as is done for non-generic
units.
(New_Overloaded_Entity, Visible_Part_Type): Remove linear search
through declarations (Simple optimization, no behavior change).

From-SVN: r254539

spark_xrefs.ads (SPARK_Xref_Record): Remove inessential components.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* spark_xrefs.ads (SPARK_Xref_Record): Remove inessential components.
(SPARK_Scope_Record): Remove inessential components.
* spark_xrefs.adb (dspark): Remove pretty-printing of removed record
components.
* lib-xref-spark_specific.adb (Add_SPARK_Scope): Remove setting of
removed record components.
(Add_SPARK_Xrefs): Remove setting of removed record components.

From-SVN: r254538

pr57878.C (__sso_string_base::_M_get_allocator): Return a value.

* g++.dg/pr57878.C (__sso_string_base::_M_get_allocator): Return
a value.

From-SVN: r254537

re PR tree-optimization/78821 (GCC7: Copying whole 32 bits structure field by field not optimised into copying whole 32 bits at once)

PR tree-optimization/78821
* gimple-ssa-store-merging.c (struct store_operand_info): Add bit_not_p
data member.
(store_operand_info::store_operand_info): Initialize it to false.
(pass_store_merging::terminate_all_aliasing_chains): Rewritten to use
ref_maybe_used_by_stmt_p and stmt_may_clobber_ref_p on lhs of each
store in the group, and if chain_info is non-NULL, to ignore altogether
that chain.
(compatible_load_p): Fail if bit_not_p does not match.
(imm_store_chain_info::output_merged_store): Handle bit_not_p loads.
(handled_load): Fill in bit_not_p.  Handle BIT_NOT_EXPR.
(pass_store_merging::process_store): Adjust
terminate_all_aliasing_chains calls to pass NULL in all current spots,
call terminate_all_aliasing_chains newly when adding a store into
a chain with non-NULL chain_info.

* gcc.dg/store_merging_2.c: Expect 3 store mergings instead of 2.
* gcc.dg/store_merging_13.c (f7, f8, f9, f10, f11, f12, f13): New
functions.
(main): Test also those.  Expect 13 store mergings instead of 6.
* gcc.dg/store_merging_14.c (f7, f8, f9): New functions.
(main): Test also those.  Expect 9 store mergings instead of 6.

From-SVN: r254536

lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Remove dead check for empty entities.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Remove dead check for
empty entities.

From-SVN: r254535

[AArch64] Simplify aarch64_can_eliminate

Simplify aarch64_can_eliminate - if we need a frame pointer, we must
eliminate to HARD_FRAME_POINTER_REGNUM.  Rather than hardcoding all
combinations from the ELIMINABLE_REGS list, just do the correct check.

    gcc/
* config/aarch64/aarch64.c (aarch64_can_eliminate): Simplify logic.

From-SVN: r254534

[AArch64] Remove aarch64_frame_pointer_required

To implement -fomit-leaf-frame-pointer, there are 2 places where we need
to check whether we have to use a frame chain (since register allocation
may allocate LR in a leaf function that omits the frame pointer, but if
LR is spilled we must emit a frame chain).  To simplify this do not force
frame_pointer_needed via aarch64_frame_pointer_required, but enable the
frame chain in aarch64_layout_frame.  Now aarch64_frame_pointer_required
can be removed and aarch64_can_eliminate is simplified.

    gcc/
* config/aarch64/aarch64.c (aarch64_frame_pointer_required)
Remove.
(aarch64_layout_frame): Initialise emit_frame_chain.
(aarch64_can_eliminate): Remove omit leaf frame pointer code.
(TARGET_FRAME_POINTER_REQUIRED): Remove define.

    testsuite/
* gcc.target/aarch64/dwarf-cfa-reg.c: Update.

From-SVN: r254533

sem_disp.adb (Is_Inherited_Public_Operation): Extend the functionality of this routine to handle multiple levels of derivations.

gcc/ada/

2017-11-08  Javier Miranda  <miranda@adacore.com>

* sem_disp.adb (Is_Inherited_Public_Operation): Extend the
functionality of this routine to handle multiple levels of derivations.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

* einfo.adb: Elist36 is now used as Nested_Scenarios.
(Nested_Scenarios): New routine.
(Set_Nested_Scenarios): New routine.
(Write_Field36_Name): New routine.
* einfo.ads: Add new attribute Nested_Scenarios along with occurrences
in entities.
(Nested_Scenarios): New routine along with pragma Inline.
(Set_Nested_Scenarios): New routine along with pragma Inline.
* sem_elab.adb (Find_And_Process_Nested_Scenarios): New routine.
(Process_Nested_Scenarios): New routine.
(Traverse_Body): When a subprogram body is traversed for the first
time, find, save, and process all suitable scenarios found within.
Subsequent traversals of the same subprogram body utilize the saved
scenarios.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

* lib-xref-spark_specific.adb (Add_SPARK_Scope): Remove detection of
protected operations.
(Add_SPARK_Xrefs): Simplify detection of empty entities.
* get_spark_xrefs.ads, get_spark_xrefs.adb, put_spark_xrefs.ads,
put_spark_xrefs.adb, spark_xrefs_test.adb: Remove code for writing,
reading and testing SPARK cross-references stored in the ALI files.
* lib-xref.ads (Output_SPARK_Xrefs): Remove.
* lib-writ.adb (Write_ALI): Do not write SPARK cross-references to the
ALI file.
* spark_xrefs.ads, spark_xrefs.adb (pspark): Remove, together
with description of the SPARK xrefs ALI format.
* gcc-interface/Make-lang.in (GNAT_ADA_OBJS): Remove get_spark_refs.o
and put_spark_refs.o.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

* exp_ch4.adb (Apply_Accessibility_Check): Do not finalize the object
when the associated access type is subject to pragma
No_Heap_Finalization.
* exp_intr.adb (Expand_Unc_Deallocation): Use the available view of the
designated type in case it comes from a limited withed unit.

gcc/testsuite/

2017-11-08  Javier Miranda  <miranda@adacore.com>

* gnat.dg/overriding_ops2.adb, gnat.dg/overriding_ops2.ads,
gnat.dg/overriding_ops2_pkg.ads, gnat.dg/overriding_ops2_pkg-high.ads:
New testcase.

From-SVN: r254532

exp_ch3.adb (Expand_N_Object_Declaration): Save and restore relevant SPARK-related flags.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

* exp_ch3.adb (Expand_N_Object_Declaration): Save and restore relevant
SPARK-related flags.  Add ??? comment.
* exp_util.adb (Insert_Actions): Add an entry for node
N_Variable_Reference_Marker.
* sem.adb (Analyze): Add an entry for node N_Variable_Reference_Marker.
* sem_ch8.adb (Find_Direct_Name): Add constant Is_Assignment_LHS. Build
and record a variable reference marker for the current name.
(Find_Expanded_Name): Add constant Is_Assignment_LHS. Build and record
a variable reference marker for the current name.
* sem_elab.adb (Build_Variable_Reference_Marker): New routine.
(Extract_Variable_Reference_Attributes): Reimplemented.
(Info_Scenario): Add output for variable references and remove output
for variable reads.
(Info_Variable_Read): Removed.
(Info_Variable_Reference): New routine.
(Is_Suitable_Scenario): Variable references are now suitable scenarios
while variable reads are not.
(Output_Active_Scenarios): Add output for variable references and
remove output for variable reads.
(Output_Variable_Read): Removed.
(Output_Variable_Reference): New routine.
(Process_Variable_Read): Removed.
(Process_Variable_Reference): New routine.
(Process_Variable_Reference_Read): New routine.
* sem_elab.ads (Build_Variable_Reference_Marker): New routine.
* sem_res.adb (Resolve_Actuals): Build and record a variable reference
marker for the current actual.
* sem_spark.adb (Check_Node): Add an entry for node
N_Variable_Reference_Marker.
* sem_util.adb (Within_Subprogram_Call): Moved to the library level.
* sem_util.ads (Within_Subprogram_Call): Moved to the library level.
* sinfo.adb (Is_Read): New routine.
(Is_Write): New routine.
(Target): Updated to handle variable reference markers.
(Set_Is_Read): New routine.
(Set_Is_Write): New routine.
(Set_Target): Updated to handle variable reference markers.
* sinfo.ads: Add new attributes Is_Read and Is_Write along with
occurrences in nodes. Update attribute Target. Add new node
kind N_Variable_Reference_Marker.
(Is_Read): New routine along with pragma Inline.
(Is_Write): New routine along with pragma Inline.
(Set_Is_Read): New routine along with pragma Inline.
(Set_Is_Write): New routine along with pragma Inline.
* sprint.adb (Sprint_Node_Actual): Add an entry for node
N_Variable_Reference_Marker.

From-SVN: r254531

aarch64-vect-lane-2.c (search_line_fast): Change type to void.

* c-c++-common/torture/aarch64-vect-lane-2.c (search_line_fast):
Change type to void.

From-SVN: r254530

sem_util.adb (Subprogram_Name): Append suffix for overloaded subprograms.

2017-11-08  Arnaud Charlet  <charlet@adacore.com>

* sem_util.adb (Subprogram_Name): Append suffix for overloaded
subprograms.

From-SVN: r254529

[multiple changes]

2017-11-08  Yannick Moy  <moy@adacore.com>

* sem_ch8.adb (Use_One_Type, Update_Use_Clause_Chain): Do not report
about unused use-type or use-package clauses inside inlined bodies.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

* sem_elab.adb (Ensure_Prior_Elaboration): Add new parameter
In_Partial_Fin along with a comment on its usage. Do not guarantee the
prior elaboration of a unit when the need came from a partial
finalization context.
(In_Initialization_Context): Relocated to Process_Call.
(Is_Partial_Finalization_Proc): New routine.
(Process_Access): Add new parameter In_Partial_Fin along with a comment
on its usage.
(Process_Activation_Call): Add new parameter In_Partial_Fin along with
a comment on its usage.
(Process_Activation_Conditional_ABE_Impl): Add new parameter
In_Partial_Fin along with a comment on its usage. Do not emit any ABE
diagnostics when the activation occurs in a partial finalization
context.
(Process_Activation_Guaranteed_ABE_Impl): Add new parameter
In_Partial_Fin along with a comment on its usage.
(Process_Call): Add new parameter In_Partial_Fin along with a comment
on its usage. A call is within a partial finalization context when it
targets a finalizer or primitive [Deep_]Finalize, and the call appears
in initialization actions. Pass this information down to the recursive
steps of the Processing phase.
(Process_Call_Ada): Add new parameter In_Partial_Fin along with a
comment on its usage. Remove the guard which suppresses the generation
of implicit Elaborate[_All] pragmas. This is now done in
Ensure_Prior_Elaboration.
(Process_Call_Conditional_ABE): Add new parameter In_Partial_Fin along
with a comment on its usage. Do not emit any ABE diagnostics when the
call occurs in a partial finalization context.
(Process_Call_SPARK): Add new parameter In_Partial_Fin along with a
comment on its usage.
(Process_Instantiation): Add new parameter In_Partial_Fin along with a
comment on its usage.
(Process_Instantiation_Ada): Add new parameter In_Partial_Fin along
with a comment on its usage.
(Process_Instantiation_Conditional_ABE): Add new parameter
In_Partial_Fin along with a comment on its usage. Do not emit any ABE
diagnostics when the instantiation occurs in a partial finalization
context.
(Process_Instantiation_SPARK): Add new parameter In_Partial_Fin along
with a comment on its usage.
(Process_Scenario): Add new parameter In_Partial_Fin along  with a
comment on its usage.
(Process_Single_Activation): Add new parameter In_Partial_Fin along
with a comment on its usage.
(Traverse_Body): Add new parameter In_Partial_Fin along with a comment
on its usage.

2017-11-08  Arnaud Charlet  <charlet@adacore.com>

* sem_ch13.adb: Add optional parameter to Error_Msg.

2017-11-08  Jerome Lambourg  <lambourg@adacore.com>

* fname.adb (Is_Internal_File_Name): Do not check the 8+3 naming schema
for the Interfaces.* hierarchy as longer unit names are now allowed.

2017-11-08  Arnaud Charlet  <charlet@adacore.com>

* sem_util.adb (Subprogram_Name): Emit sloc for the enclosing
subprogram as well.  Support more cases of entities.
(Append_Entity_Name): Add some defensive code.

From-SVN: r254528

PR 82869 Introduce logical_type_node and use it

Earlier GFortran used to redefine boolean_type_node, which in the rest
of the compiler means the C/C++ _Bool/bool type, to the Fortran
default logical type.  When this redefinition was removed, a few
issues surfaced. Namely,

1) PR 82869, where we created a boolean tmp variable, and passed it to
the runtime library as a Fortran logical variable of a different size.

2) Fortran specifies that logical operations should be done with the
default logical kind, not in any other kind.

3) Using 8-bit variables have some issues, such as
   - on x86, partial register stalls and length prefix changes.
   - s390 has a compare with immediate and jump instruction which
     works with 32-bit but not 8-bit quantities.

This patch addresses these issues by introducing a type
logical_type_node which is a Fortran LOGICAL variable of default
kind. It is then used in places were the Fortran standard mandates, as
well as for compiler generated temporary variables.

For x86-64, using the Polyhedron benchmark suite, no performance or
code size difference worth mentioning was observed.

Regtested on x86_64-pc-linux-gnu.

gcc/fortran/ChangeLog:

2017-11-08  Janne Blomqvist  <jb@gcc.gnu.org>

PR 82869
* convert.c (truthvalue_conversion): Use logical_type_node.
* trans-array.c (gfc_trans_allocate_array_storage): Likewise.
(gfc_trans_create_temp_array): Likewise.
(gfc_trans_array_ctor_element): Likewise.
(gfc_trans_array_constructor_value): Likewise.
(trans_array_constructor): Likewise.
(trans_array_bound_check): Likewise.
(gfc_conv_array_ref): Likewise.
(gfc_trans_scalarized_loop_end): Likewise.
(gfc_conv_array_extent_dim): Likewise.
(gfc_array_init_size): Likewise.
(gfc_array_allocate): Likewise.
(gfc_trans_array_bounds): Likewise.
(gfc_trans_dummy_array_bias): Likewise.
(gfc_conv_array_parameter): Likewise.
(duplicate_allocatable): Likewise.
(duplicate_allocatable_coarray): Likewise.
(structure_alloc_comps): Likewise
(get_std_lbound): Likewise
(gfc_alloc_allocatable_for_assignment): Likewise
* trans-decl.c (add_argument_checking): Likewise
(gfc_generate_function_code): Likewise
* trans-expr.c (gfc_copy_class_to_class): Likewise
(gfc_trans_class_array_init_assign): Likewise
(gfc_trans_class_init_assign): Likewise
(gfc_conv_expr_present): Likewise
(gfc_conv_substring): Likewise
(gfc_conv_cst_int_power): Likewise
(gfc_conv_expr_op): Likewise
(gfc_conv_procedure_call): Likewise
(fill_with_spaces): Likewise
(gfc_trans_string_copy): Likewise
(gfc_trans_alloc_subarray_assign): Likewise
(gfc_trans_pointer_assignment): Likewise
(gfc_trans_scalar_assign): Likewise
(fcncall_realloc_result): Likewise
(alloc_scalar_allocatable_for_assignment): Likewise
(trans_class_assignment): Likewise
(gfc_trans_assignment_1): Likewise
* trans-intrinsic.c (build_fixbound_expr): Likewise
(gfc_conv_intrinsic_aint): Likewise
(gfc_trans_same_strlen_check): Likewise
(conv_caf_send): Likewise
(trans_this_image): Likewise
(conv_intrinsic_image_status): Likewise
(trans_image_index): Likewise
(gfc_conv_intrinsic_bound): Likewise
(conv_intrinsic_cobound): Likewise
(gfc_conv_intrinsic_mod): Likewise
(gfc_conv_intrinsic_dshift): Likewise
(gfc_conv_intrinsic_dim): Likewise
(gfc_conv_intrinsic_sign): Likewise
(gfc_conv_intrinsic_ctime): Likewise
(gfc_conv_intrinsic_fdate): Likewise
(gfc_conv_intrinsic_ttynam): Likewise
(gfc_conv_intrinsic_minmax): Likewise
(gfc_conv_intrinsic_minmax_char): Likewise
(gfc_conv_intrinsic_anyall): Likewise
(gfc_conv_intrinsic_arith): Likewise
(gfc_conv_intrinsic_minmaxloc): Likewise
(gfc_conv_intrinsic_minmaxval): Likewise
(gfc_conv_intrinsic_btest): Likewise
(gfc_conv_intrinsic_bitcomp): Likewise
(gfc_conv_intrinsic_shift): Likewise
(gfc_conv_intrinsic_ishft): Likewise
(gfc_conv_intrinsic_ishftc): Likewise
(gfc_conv_intrinsic_leadz): Likewise
(gfc_conv_intrinsic_trailz): Likewise
(gfc_conv_intrinsic_mask): Likewise
(gfc_conv_intrinsic_spacing): Likewise
(gfc_conv_intrinsic_rrspacing): Likewise
(gfc_conv_intrinsic_size): Likewise
(gfc_conv_intrinsic_sizeof): Likewise
(gfc_conv_intrinsic_transfer): Likewise
(gfc_conv_allocated): Likewise
(gfc_conv_associated): Likewise
(gfc_conv_same_type_as): Likewise
(gfc_conv_intrinsic_trim): Likewise
(gfc_conv_intrinsic_repeat): Likewise
(conv_isocbinding_function): Likewise
(conv_intrinsic_ieee_is_normal): Likewise
(conv_intrinsic_ieee_is_negative): Likewise
(conv_intrinsic_ieee_copy_sign): Likewise
(conv_intrinsic_move_alloc): Likewise
* trans-io.c (set_parameter_value_chk): Likewise
(set_parameter_value_inquire): Likewise
(set_string): Likewise
* trans-openmp.c (gfc_walk_alloc_comps): Likewise
(gfc_omp_clause_default_ctor): Likewise
(gfc_omp_clause_copy_ctor): Likewise
(gfc_omp_clause_assign_op): Likewise
(gfc_omp_clause_dtor): Likewise
(gfc_omp_finish_clause): Likewise
(gfc_trans_omp_clauses): Likewise
(gfc_trans_omp_do): Likewise
* trans-stmt.c (gfc_trans_goto): Likewise
(gfc_trans_sync): Likewise
(gfc_trans_arithmetic_if): Likewise
(gfc_trans_simple_do): Likewise
(gfc_trans_do): Likewise
(gfc_trans_forall_loop): Likewise
(gfc_trans_where_2): Likewise
(gfc_trans_allocate): Likewise
(gfc_trans_deallocate): Likewise
* trans-types.c (gfc_init_types): Initialize logical_type_node and
its true/false trees.
(gfc_get_array_descr_info): Use logical_type_node.
* trans-types.h (logical_type_node): New tree.
(logical_true_node): Likewise.
(logical_false_node): Likewise.
* trans.c (gfc_trans_runtime_check): Use logical_type_node.
(gfc_call_malloc): Likewise
(gfc_allocate_using_malloc): Likewise
(gfc_allocate_allocatable): Likewise
(gfc_add_comp_finalizer_call): Likewise
(gfc_add_finalizer_call): Likewise
(gfc_deallocate_with_status): Likewise
(gfc_deallocate_scalar_with_status): Likewise
(gfc_call_realloc): Likewise

gcc/testsuite/ChangeLog:

2017-11-08  Janne Blomqvist  <jb@gcc.gnu.org>

PR 82869
* gfortran.dg/logical_temp_io.f90: New test.
* gfortran.dg/logical_temp_io_kind8.f90: New test.

From-SVN: r254526

Fix vrp101.c test-case.

2017-11-08  Martin Liska  <mliska@suse.cz>

* gcc.dg/tree-ssa/vrp101.c: Update expected pattern as
frequencies are not longer printed in dump output.

From-SVN: r254525

Simplify call of gimple_call_internal_p.

2017-11-08  Martin Liska  <mliska@suse.cz>

* gimplify.c (expand_FALLTHROUGH_r): Simplify usage
of gimple_call_internal_p.

From-SVN: r254524

* gcc.dg/strlenopt-33g.c: Remove duplicate dg-do command.

From-SVN: r254523

Fix -Wreturn-type fallout in g++.old-deja/g++.brendan/asm-extn1.C

* g++.old-deja/g++.brendan/asm-extn1.C: Accept all sparc* targets.
(main): Add return type.

From-SVN: r254522

[mips] Wrap ASM_OUTPUT_LABELREF in do {} while (0)

2017-11-07  Tom de Vries  <tom@codesourcery.com>

* config/mips/mips.h (ASM_OUTPUT_LABELREF): Wrap in "do {} while (0)".

From-SVN: r254521

[mips] Remove semicolon after do {} while (0) in ASM_OUTPUT_CASE_END

2017-11-07  Tom de Vries  <tom@codesourcery.com>

* config/mips/mips.h (ASM_OUTPUT_CASE_END): Remove semicolon after
"do {} while (0)".

From-SVN: r254520

Fix fallthrough attribute ignorance w/ -fsanitize=address (PR sanitizer/82792).

2017-11-08  Martin Liska  <mliska@suse.cz>

PR sanitizer/82792
* gimplify.c (expand_FALLTHROUGH_r): Skip IFN_ASAN_MARK.
2017-11-08  Martin Liska  <mliska@suse.cz>

PR sanitizer/82792
* g++.dg/asan/pr82792.C: New test.

From-SVN: r254519

re PR bootstrap/82670 (UBSAN bootstrap broken after recent libsanitizer merge)

PR bootstrap/82670
* ubsan/Makefile.am (ubsan_files): Remove ubsan_init_standalone.cc
and ubsan_signals_standalone.cc.
* ubsan/Makefile.in: Regenerated.

From-SVN: r254518

analyze_brprob.py: fix SI units

2017-11-08  Martin Liska  <mliska@suse.cz>

* analyze_brprob.py: Fix abbreviations for SI units.

From-SVN: r254517

Daily bump.

From-SVN: r254516

* gimple-pretty-print.c (dump_profile): Return "" instead of NULL.

From-SVN: r254513

[PATCH] Install cp/operators.def as part of plugin headers

https://gcc.gnu.org/ml/gcc-patches/2017-11/msg00498.html
2017-11-07 Boris Kolpackov  <boris@codesynthesis.com>
* Make-lang.in (CP_PLUGIN_HEADERS): Add operators.def since included
in cp-tree.h.

From-SVN: r254512

re PR c++/82835 (ICE on valid code with -fopenmp)

PR c++/82835
* cp-gimplify.c (cxx_omp_clause_apply_fn): For methods pass i - 1 to
convert_default_arg instead of i.

* testsuite/libgomp.c++/pr82835.C: New test.

From-SVN: r254511

re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)

PR target/82855
* config/i386/i386.md (SWI1248_AVX512BWDQ2_64): New mode iterator.
(*cmp<mode>_ccz_1): New insn with $k alternative.

* gcc.target/i386/avx512dq-pr82855.c: New test.

From-SVN: r254510

re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)

PR target/82855
* config/i386/i386.c (ix86_swap_binary_operands_p): Treat
RTX_COMM_COMPARE as commutative as well.
(ix86_binary_operator_ok): Formatting fix.
* config/i386/sse.md (*mul<mode>3<mask_name><round_name>,
*<code><mode>3<mask_name><round_saeonly_name>,
*<code><mode>3<mask_name>, *<code>tf3, *mul<mode>3<mask_name>,
*<s>mul<mode>3_highpart<mask_name>,
*vec_widen_umult_even_v16si<mask_name>,
*vec_widen_umult_even_v8si<mask_name>,
*vec_widen_umult_even_v4si<mask_name>,
*vec_widen_smult_even_v16si<mask_name>,
*vec_widen_smult_even_v8si<mask_name>, *sse4_1_mulv2siv2di3<mask_name>,
*avx2_pmaddwd, *sse2_pmaddwd, *<sse4_1_avx2>_mul<mode>3<mask_name>,
*avx2_<code><mode>3, *avx512f_<code><mode>3<mask_name>,
*sse4_1_<code><mode>3<mask_name>, *<code>v8hi3,
*sse4_1_<code><mode>3<mask_name>, *<code>v16qi3, *avx2_eq<mode>3,
<avx512>_eq<mode>3<mask_scalar_merge_name>_1, *sse4_1_eqv2di3,
*sse2_eq<mode>3, <mask_codefor><code><mode>3<mask_name>,
*<code><mode>3, *<sse2_avx2>_uavg<mode>3<mask_name>,
*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, *ssse3_pmulhrswv4hi3): Use
!(MEM_P (operands[1]) && MEM_P (operands[2])) condition instead of
ix86_binary_operator_ok.  Formatting fixes.
(*<plusminus_insn><mode>3<mask_name><round_name>,
*<plusminus_insn><mode>3, *<plusminus_insn><mode>3_m): Formatting
fixes.

From-SVN: r254509

rs6000: Use isel for the cstore patterns

We currently generate (sometimes pretty long) sequences of integer
insns to implement the various cstore patterns.  If the CPU has a fast
isel, we can use that at the same latency as of just two integer insns
(you also get a load immediate of 1, and sometimes one of 0 as well,
but those are not in the critical path: they don't depend on any other
instruction).

There are a few patterns that already are implemented with just two
instructions; so don't use isel in that case (I still need to check
all lt/gt/ltu/gtu/le/leu/ge/geu patterns with all SI/DI combinations,
one or two might be better without isel).

This introduces a new GPR2 mode iterator, for those patterns that use
two independent integer modes.

* config/rs6000/rs6000.md (GPR2): New mode_iterator.
("cstore<mode>4"): Don't always expand with rs6000_emit_int_cmove for
eq and ne if TARGET_ISEL.
(cmp): New code_iterator.
(UNS, UNSU_, UNSIK): New code_attrs.
(<code><GPR:mode><GPR2:mode>2_isel): New define_insn_and_split.
("eq<mode>3"): New define_expand, rename the define_insn_and_split
to...
("eq<mode>3"): ... this.
("ne<mode>3"): New define_expand, rename the define_insn_and_split
to...
("ne<mode>3"): ... this.

From-SVN: r254508

Fix SSE bits dependencies.

gcc/
PR target/82812
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag.
(ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags.
* config/i386/i386-c.c (ix86_target_macros_internal): Ditto.
* config/i386/i386.opt: Ditto.
* config/i386/i386.c (ix86_target_string): Ditto.
(ix86_option_override_internal): Ditto.
(ix86_init_mpx_builtins): Move MPX to args2.
(ix86_expand_builtin): Special handling for OPTION_MASK_ISA_GFNI.
* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi,
__builtin_ia32_vgf2p8affineinvqb_v64qi_mask,
__builtin_ia32_vgf2p8affineinvqb_v32qi,
__builtin_ia32_vgf2p8affineinvqb_v32qi_mask,
__builtin_ia32_vgf2p8affineinvqb_v16qi,
__builtin_ia32_vgf2p8affineinvqb_v16qi_mask): Move to ARGS array.

From-SVN: r254507

Check for S_ISSOCK before use

* src/filesystem/ops-common.h (make_file_type) [S_ISSOCK]: Only use
S_ISSOCK when defined.

From-SVN: r254506

re PR target/80425 (Extra inter-unit register move with zero-extension)

PR target/80425
* config/i386.i386.md (*zero_extendsidi2): Change (?r,*Yj), (?*Yi,r)
and (*x,m) to ($r,Yj), ($Yi,r) and ($x,m).
(zero-extendsidi peephole2): Remove peephole.

testsuite/ChangeLog:

PR target/80425
* gcc.target/i386/pr80425-3.c: New test.

From-SVN: r254505

compiler: don't double count "." in nested_function_num

    Nested functions are named "outerfunc.$nestedN", where N is a
    number. nested_function_num extracts that number. The name is
    first passed to unpack_hidden_name, which handles the "." and
    should result "$nestedN". Don't expect the "." again.

    This fixes assertion failure when escape analysis is enabled
    and -fgo-debug-escape is on. The failure looks

    go1: internal compiler error: in nested_function_num, at go/gofrontend/names.cc:241
    0x7bd7d3 Gogo::nested_function_num(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)

    Reviewed-on: https://go-review.googlesource.com/76213

From-SVN: r254504

re PR c/53037 (warn_if_not_aligned(X))

PR c/53037
* stor-layout.c: Include attribs.h.
(handle_warn_if_not_align): Replace test on TYPE_USER_ALIGN with
explicit lookup of "aligned" attribute.

From-SVN: r254503

* g++.dg/pr50763-3.C (evalPoint): Return a value.

From-SVN: r254502

RISC-V: Implement movmemsi

Without this we aren't getting proper memcpy inlining on RISC-V systems,
which is particularly disastrous for Dhrystone performance on RV32IM
systems.

gcc/ChangeLog

2017-11-07  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv-protos.h (riscv_hard_regno_nregs): New
        prototype.
        (riscv_expand_block_move): Likewise.
        gcc/config/riscv/riscv.h (MOVE_RATIO): Tune cost to movmemsi
        implementation.
        (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER): New define.
        (RISCV_MAX_MOVE_BYTES_STRAIGHT): New define.
        gcc/config/riscv/riscv.c (riscv_block_move_straight): New
        function.
        (riscv_adjust_block_mem): Likewise.
        (riscv_block_move_loop): Likewise.
        (riscv_expand_block_move): Likewise.
        gcc/config/riscv/riscv.md (movmemsi): New pattern.

From-SVN: r254501

RISC-V: Define MUSL_DYNAMIC_LINKER

Use no suffix at all in the musl dynamic linker name for hard
float ABI. Use -sf and -sp suffixes in musl dynamic linker name
for soft float and single precision ABIs. The following table
outlines the musl interpreter names for the RISC-V ABI names.

musl interpreter        | RISC-V ABI
----------------------- | -------------
ld-musl-riscv32.so.1    | riscv32-ilp32d
ld-musl-riscv64.so.1    | riscv64-lp64d
ld-musl-riscv32-sf.so.1 | riscv32-ilp32
ld-musl-riscv64-sf.so.1 | riscv64-lp64
ld-musl-riscv32-sp.so.1 | riscv32-ilp32f
ld-musl-riscv64-sp.so.1 | riscv64-lp64f

gcc/ChangeLog

2017-11-06  Michael Clark  <michaeljclark@mac.com>

        * config/riscv/linux.h (MUSL_ABI_SUFFIX): New define.
        (MUSL_DYNAMIC_LINKER): Likewise.

From-SVN: r254500

[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand

Some of the shift expanders accepted nonmemory_operands but were only
able to handle register_operands or CONST_INTs.  This is probably
academic without SVE, since we're not likely to see shifts by other
types of constant (const_wide_ints, consts, etc).  But for SVE,
it's possible for a vectorised shift induction to have a CONST_POLY_INT
shift amount.

This patch makes the expanders use aarch64_reg_or_imm instead.

2017-11-07  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
nonmmory_operand.

From-SVN: r254499

match.pd: Fix build.

2017-11-07  Richard Biener  <rguenther@suse.de>

* match.pd: Fix build.

From-SVN: r254498

PR71026: Canonicalize negates in division

Canonicalize x / (- y) into (-x) / y.

This moves negates out of the RHS of a division in order to
allow further simplifications and potentially more reciprocal CSEs.

2017-11-07  Wilco Dijkstra  <wdijkstr@arm.com>
    Jackson Woodruff  <jackson.woodruff@arm.com>

    gcc/
PR tree-optimization/71026
* match.pd: Canonicalize negate in division.

    testsuite/
PR 71026/tree-optimization/71026
* gcc.dg/div_neg: New test.

From-SVN: r254497

PR80131: Simplification of 1U << (31 - x)

Currently the code A << (B - C) is not simplified.
However at least a more specific case of 1U << (C -x) where
C = precision(type) - 1 can be simplified to (1 << C) >> x.

This is done by adding a new simplification rule in match.pd.

2017-11-07  Sudakshina Das  <sudi.das@arm.com>

    gcc/
PR middle-end/80131
* match.pd: Simplify 1 << (C - x) where C = precision (x) - 1.

    testsuite/
PR middle-end/80131
* testsuite/gcc.dg/pr80131-1.c: New Test.

From-SVN: r254496

More bitop simplifications in match.pd

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

gcc/
* match.pd ((a&~b)|(a^b),(a&~b)^~a,(a|b)&~(a^b),a|~(a^b),
(a|b)|(a&^b),(a&b)|~(a^b),~(~a&b),~X^Y): New transformations.

gcc/testsuite/
* gcc.dg/tree-ssa/bitops-1.c: New file.

From-SVN: r254495

More fold_negate in match.pd

gcc/ChangeLog:

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

* fold-const.c (negate_expr_p) [PLUS_EXPR, MINUS_EXPR]: Handle
non-scalar integral types.
* match.pd (negate_expr_p): Handle MINUS_EXPR.
(-(A-B), -(~A)): New transformations.

gcc/testsuite/ChangeLog:

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

* gcc.dg/tree-ssa/negminus.c: New test.

From-SVN: r254494

[powerpcspe] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPTIONS

2017-11-07  Tom de Vries  <tom@codesourcery.com>

* config/powerpcspe/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove
semicolon after "do {} while (0)".
* config/powerpcspe/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/powerpcspe/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.

From-SVN: r254493

[rs6000] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPTIONS

2017-11-07  Tom de Vries  <tom@codesourcery.com>

* config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove semicolon
after "do {} while (0)".
* config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
* config/rs6000/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.

From-SVN: r254492

[libgcc, rs6000] Remove semicolon after do {} while (0) in REGISTER_CFA_OFFSET_FOR

2017-11-07  Tom de Vries  <tom@codesourcery.com>

* config/rs6000/aix-unwind.h (REGISTER_CFA_OFFSET_FOR): Remove semicolon
after "do {} while (0)".

From-SVN: r254491

[arm] Remove semicolon after while {} do (0) in HANDLE_NARROW_SHIFT_ARITH

2017-11-07  Tom de Vries  <tom@codesourcery.com>

PR other/82784
* config/arm/arm.c (HANDLE_NARROW_SHIFT_ARITH): Remove semicolon after
"while {} do (0)".
(arm_rtx_costs_internal): Add missing semicolon after
HANDLE_NARROW_SHIFT_ARITH call.

From-SVN: r254490

[libgcc] Remove semicolon after do {} while (0) in FP_HANDLE_EXCEPTIONS

2017-11-07  Tom de Vries  <tom@codesourcery.com>

PR other/82784
* config/aarch64/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Remove
semicolon after "do {} while (0)".
* config/i386/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
* config/ia64/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
* config/mips/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
* config/rs6000/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.

From-SVN: r254489

P0704R1 - fixing const-qualified pointers to members

* typeck2.c (build_m_component_ref): Also accept in lower stds with
a pedwarn.

From-SVN: r254487

Require ngettext in test of system gettext implementation

gcc currently uses ngettext in a number of places (gcc/cp/pt.c,
gcc/diagnostic.c, gcc/collect2.c).  Apparently there are (or used to
be) gettext implementations that lack ngettext.  See config/gettext.m4.

This patch arranges for intl/ to be compiled when the system gettext
lacks ngettext.

* configure.ac: Invoke AM_GNU_GETTEXT with need_ngettext.
* configure: Regenerate.

From-SVN: r254486

rs6000: Don't clear TARGET_ISEL implicitly

We want to actually use isel, so we shouldn't disable it.  It is
already not set by default on CPUs that don't have it, or where we
do not want to use it.

* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
disable isel if it was not set explicitly.

From-SVN: r254485

FT32 makes use of multiple address spaces.

FT32 makes use of multiple address spaces. When trying to inspect
objects in GDB, GDB was treating them as a straight "const". The cause
seems to be in GCC DWARF2 output.

This output is handled in gcc/gcc/dwarf2out.c, where modified_type_die()
checks that TYPE has qualifiers CV_QUALS. However while TYPE has
ADDR_SPACE qualifiers, the modified_type_die() explicitly discards the
ADDR_SPACE qualifiers.

This patch retains the ADDR_SPACE qualifiers as modified_type_die()
outputs the DWARF type tree.  This allows the types to match, and correct
type information for the object is emitted.

[gcc]

2017-11-06  James Bowman  <james.bowman@ftdichip.com>

* gcc/dwarf2out.c (modified_type_die): Retain ADDR_SPACE
qualifiers.
        (add_type_attribute) likewise.

From-SVN: r254484

Daily bump.

From-SVN: r254483

i386: Use reference of struct ix86_frame to avoid copy

When there is no need to make a copy of ix86_frame, we can use reference
of struct ix86_frame to avoid copy.

Tested on x86-64.

* config/i386/i386.c (ix86_can_use_return_insn_p): Use reference
of struct ix86_frame.
(ix86_initial_elimination_offset): Likewise.
(ix86_expand_split_stack_prologue): Likewise.

From-SVN: r254480

stack-check-12.c: Revert to initial version.

* gcc.target/i386/stack-check-12.c: Revert to initial version.  Then..
Add -fomit-frame-pointer.

From-SVN: r254479

Update comment in tree-vrp.h

2017-11-06  Marc Glisse  <marc.glisse@inria.fr>

* tree-vrp.h (enum value_range_type): Update stale comment.

From-SVN: r254478

tr1.cc: Compile with -O0.

2017-11-06  François Dumont  <fdumont@gcc.gnu.org>

* testsuite/libstdc++-prettyprinters/tr1.cc:  Compile with -O0.

From-SVN: r254477

compiler: disable escape analysis for runtime

    Currently the runtime is hard-coded to non-escape in various places.
    Don't run escape analysis for runtime.

    Reviewed-on: https://go-review.googlesource.com/76210

From-SVN: r254476

libgo: pass flags to recursive make

    "make check" runs make recursively to check each package. Pass
    the flags through. So it is possible to run "make check" with
    different settings easily.

    Reviewed-on: https://go-review.googlesource.com/76029

From-SVN: r254475

[AArch64] Pass number of units to aarch64_expand_vec_perm(_const)

This patch passes the number of units to aarch64_expand_vec_perm
and aarch64_expand_vec_perm_const, which avoids a to_constant ()
once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm)
(aarch64_expand_vec_perm_const): Take the number of units too.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm)
(aarch64_expand_vec_perm_const): Likewise.
* config/aarch64/aarch64-simd.md (vec_perm_const<mode>)
(vec_perm<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254469

[AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half

This patch passes the number of units to aarch64_simd_vect_par_cnst_half,
which avoids a to_constant () once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half):
Take the number of units too.
* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise.
(aarch64_simd_check_vect_par_cnst_half): Update call accordingly,
but check for a vector mode before rather than after the call.
* config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>)
(move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>)
(vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>)
(vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>)
(vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>)
(aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3)
(widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>)
(aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>)
(aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>)
(aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>)
(aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>)
(aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>)
(aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>)
(aarch64_sqdmull2_n<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254468

[AArch64] Pass number of units to aarch64_reverse_mask

This patch passes the number of units to aarch64_reverse_mask,
which avoids a to_constant () once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take
the number of units too.
* config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise.
* config/aarch64/aarch64-simd.md (vec_load_lanesoi<mode>)
(vec_store_lanesoi<mode>, vec_load_lanesci<mode>)
(vec_store_lanesci<mode>, vec_load_lanesxi<mode>)
(vec_store_lanesxi<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254467

[AArch64] Add an endian_lane_rtx helper routine

Later patches turn the number of vector units into a poly_int.
We deliberately don't support applying GEN_INT to those (except
in target code that doesn't distinguish between poly_ints and normal
constants); gen_int_mode needs to be used instead.

This patch therefore replaces instances of:

  GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])))

with uses of a new endian_lane_rtx function.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_endian_lane_rtx): Declare.
* config/aarch64/aarch64.c (aarch64_endian_lane_rtx): New function.
* config/aarch64/aarch64.h (ENDIAN_LANE_N): Take the number
of units rather than the mode.
* config/aarch64/iterators.md (nunits): New mode attribute.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):
Use aarch64_endian_lane_rtx instead of GEN_INT (ENDIAN_LANE_N ...).
* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>)
(aarch64_dup_lane_<vswap_width_name><mode>, *aarch64_mul3_elt<mode>)
(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_64v2df, *aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>, *aarch64_mls_elt<mode>)
(*aarch64_mls_elt_<vswap_width_name><mode>, *aarch64_fma4_elt<mode>)
(*aarch64_fma4_elt_<vswap_width_name><mode>):: Likewise.
(*aarch64_fma4_elt_to_64v2df, *aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fnma4_elt_to_64v2df, reduc_plus_scal_<mode>): Likewise.
(reduc_plus_scal_v4sf, reduc_<maxmin_uns>_scal_<mode>): Likewise.
(reduc_<maxmin_uns>_scal_<mode>): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>, *aarch64_mulx_elt_<vswap_width_name><mode>)
(*aarch64_mulx_elt<mode>, *aarch64_vgetfmulx<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>, aarch64_sq<r>dmulh_laneq<mode>)
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Likewise.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
(aarch64_vec_store_lanesoi_lane<mode>): Likewise.
(aarch64_vec_load_lanesci_lane<mode>): Likewise.
(aarch64_vec_store_lanesci_lane<mode>): Likewise.
(aarch64_vec_load_lanesxi_lane<mode>): Likewise.
(aarch64_vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_simd_vec_set<mode>): Update use of ENDIAN_LANE_N.
(aarch64_simd_vec_setv2di): Likewise.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254466

Fix ChangeLog entry

From-SVN: r254465

rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8 definitions.

gcc/ChangeLog:

2017-11-06  Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8
definitions.
(P9V_BUILTIN_VEC_REVB): Remove the power 9 instance definitions.
* config/rs6000/altivec.h (vec_revb): Change the #define from power 9
to power 8.
* config/rs6000/r6000-protos.h (swap_endian_selector_for_mode): Add new
extern declaration.
* config/rs6000/rs6000.c (swap_endian_selector_for_mode): Add function.
* config/rs6000/rs6000-builtin.def (BU_P8V_VSX_1, BU_P8V_OVERLOAD_1):
Add power 8 macro expansions.
(BU_P9V_OVERLOAD_1): Remove power 9 overload expansion.
* config/rs6000/vsx.md (revb_<mode>): Add define_expand to generate
power 8 instructions.  (VSX_XXBR): Add iterator.

gcc/testsuite/ChangeLog:

2017-11-06  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-revb-runnable.c: New runnable test file.

From-SVN: r254464

[Arm] Cleanup IT attributes

A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in
ITs block even when arm_restrict_it was enabled.  Rather than just fixing this
latent issue, change the default of predicable_short_it to "no" so that only
16-bit instructions need to be marked with it.  As a result there are far fewer
patterns that need the attribute, and omitting predicable_short_it is no longer
causing issues.

* config/arm/arm.md (predicable_short_it): Change default to "no",
improve documentation, remove uses that are identical to the default.
(enabled_for_depr_it): Rename to enabled_for_short_it.
* gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
* gcc/config/arm/ldmstm.md (predicable_short_it): Likewise.
* gcc/config/arm/sync.md (predicable_short_it): Likewise.
* gcc/config/arm/thumb2.md (predicable_short_it): Likewise.
* gcc/config/arm/vfp.md (predicable_short_it): Likewise.

From-SVN: r254463

re PR target/82748 (ICE with __builtin_fabsq and __float128 in copy_to_mode_reg, at explow.c:612)

[gcc]
2017-11-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/82748
* config/rs6000/rs6000-builtin.def (BU_FLOAT128_1): Delete
float128 helper macros, which are no longer used after deleting
the old 'q' built-in functions, and moving the round to odd
built-in functions to being special built-in functions.
(BU_FLOAT128_2): Likewise.
(BU_FLOAT128_1_HW): Likewise.
(BU_FLOAT128_2_HW): Likewise.
(BU_FLOAT128_3_HW): Likewise.
(FABSQ): Delete old 'q' built-in functions.
(COPYSIGNQ): Likewise.
(SQRTF128_ODD): Move round to odd built-in functions to be
special built-in functions, so that we can handle
-mabi=ieeelongdouble.
(TRUNCF128_ODD): Likewise.
(ADDF128_ODD): Likewise.
(SUBF128_ODD): Likewise.
(MULF128_ODD): Likewise.
(DIVF128_ODD): Likewise.
(FMAF128_ODD): Likewise.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Map old 'q'
built-in names to 'f128'.
* config/rs6000/rs6000.c (rs6000_fold_builtin): Remove folding the
old 'q' built-in functions, as the machine independent code for
'f128' built-in functions handles this.
(rs6000_expand_builtin): Add expansion for float128 round to odd
functions, keying off on -mabi=ieeelongdouble of whether to use
the KFmode or TFmode variant.
(rs6000_init_builtins): Initialize the _Float128 round to odd
built-in functions.
* doc/extend.texi (PowerPC Built-in Functions): Document the old
_Float128 'q' built-in functions are now mapped into the new
'f128' built-in functions.

[gcc/testsuite]
2017-11-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/82748
* gcc.target/powerpc/pr82748-1.c: New test.
* gcc.target/powerpc/pr82748-2.c: Likewise.

From-SVN: r254462

re PR c++/65579 ([C++11] gcc requires definition of a static constexpr member even though it is not odr-used)

/cp
2017-11-06  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/65579
* decl2.c (finish_static_data_member_decl): If there's an initializer,
complete the type and re-apply the quals.

/testsuite
2017-11-06  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/65579
* g++.dg/cpp0x/constexpr-template11.C: New.

From-SVN: r254461

collect2.c (add_lto_object): Compile for OBJECT_COFF.

* collect2.c (add_lto_object): Compile for OBJECT_COFF.
(scan_prog_file): Don't skip PASS_LTOINFO. Scan for LTO objects.

From-SVN: r254460

* gcc-interface/misc.c (gnat_post_options): Clear warn_return_type.

From-SVN: r254459

ipa-fnsummary.c: fix use-after-free crash (PR jit/82826)

gcc/ChangeLog:
PR jit/82826
* ipa-fnsummary.c (ipa_fnsummary_c_finalize): New function.
* ipa-fnsummary.h (ipa_fnsummary_c_finalize): New decl.
* toplev.c: Include "ipa-fnsummary.h".
(toplev::finalize): Call ipa_fnsummary_c_finalize.

From-SVN: r254458

re PR tree-optimization/82838 (ICE in verify_ssa failed w/ store-merging)

PR tree-optimization/82838
* gimple-ssa-store-merging.c
(imm_store_chain_info::output_merged_store): Call force_gimple_operand_1
on a separate gimple_seq which is then appended to seq.

* gcc.c-torture/compile/pr82838.c: New test.

From-SVN: r254457

re PR target/82788 (wrong code with -fstack-clash-protection --param=stack-clash-protection-probe-interval=10 on simple code)

PR target/82788
* config/i386/i386.c (PROBE_INTERVAL): Remove.
(get_probe_interval): New functions.
(ix86_adjust_stack_and_probe_stack_clash): Use get_probe_interval.
(ix86_adjust_stack_and_probe): Likewise.
(output_adjust_stack_and_probe): Likewise.
(ix86_emit_probe_stack_range): Likewise.
(ix86_expand_prologue): Likewise.

PR target/82788
* gcc.dg/pr82788.c: New test.

From-SVN: r254456

Check in right version of stack-check-12.c

From-SVN: r254455

PR82816: Widening multiplies of bitfields

In this PR we tried to create a widening multiply of two 3-bit numbers,
but that isn't a widening multiply at the optab/rtl level, since both
the input and output still have the same mode.

We could trap this either in is_widening_mult_p or (as the patch does)
in the routines that actually ask for an optab.  The latter seemed
more natural since is_widening_mult_p doesn't otherwise care about modes.

2017-11-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
PR tree-optimization/82816
* tree-ssa-math-opts.c (convert_mult_to_widen): Return false
if the modes of the two types are the same.
(convert_plusminus_to_widen): Likewise.

gcc/testsuite/
* gcc.c-torture/compile/pr82816.c: New test.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254454

[gcc]

2017-11-06  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/altivec.md (*p9_vadu<mode>3) Rename to
p9_vadu<mode>3.
(usadv16qi): New define_expand.
(usadv8hi): New define_expand.

[gcc/testsuite]

2017-11-06  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.target/powerpc/sad-vectorize-1.c: New file.
* gcc.target/powerpc/sad-vectorize-2.c: New file.
* gcc.target/powerpc/sad-vectorize-3.c: New file.
* gcc.target/powerpc/sad-vectorize-4.c: New file.

From-SVN: r254453

re PR bootstrap/82832 (Broken PGO LTO bootstrap on x86_64 after r254379)

PR bootstrap/82832
* ipa-inline-transform.c (update_noncloned_frequencies): Always
scale.
(inline_transform): Likewise.
* predict.c (counts_to_freqs): Remove useless conditional.
* profile-count.h (profile_count::apply_scale): Move sanity check.
* tree-inline.c (copy_bb): Always scale.
(copy_cfg_body): Likewise.

From-SVN: r254452