sim: Implement load_addr_mask auto-calculation

Recent Linux kernels for AArch64 have changed their start addresses
but we still want to relocate the kernel to 0x80080000 which
required hacking the load_addr_mask in Realview.py to be 0x7ffffff
from 0xfffffff to mask off the proper number of MSBs to load the
kernel in the desired location.  To avoid having to make this change
in the future again, we auto-calculate  the load_addr_mask if it is
specified as 0x0 in the System sim-object to find the most restrictive
address mask instead of having the configuration specify it.  If the
configuration does specify the address mask, we use it instead of
auto-calculating.

Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf
Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2323
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

system-arm: change system/arm/aarch64_bootloader/boot.S copyright

The aarch64 boot loader was distributed using a BSD license that was
using non-standard formatting. Updated the license to match gem5's
canonical license format and removed the separete LICENSE.txt file.

Change-Id: I660b73ca5ddd922763a2b72051c73d539248ebcf
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5728
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim: ScopedMigration does nothing if both eqs are the same

Added a check to avoid unlocking/locking the same event queue. Also,
added an optional parameter to enable the migration to be skipped. This
can be useful to disable the synchronization for certain runtime
conditions.

Change-Id: I4b03b3ffff4f9503153cd41dd8aa78705bf16cc4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5730
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: Add script to plot DRAM low power sweep

This change adds a script to generate graphs from the stats file
output by the configuration script low_power_sweep.py.

The graphs show stacked bars for time spent and energy consumed
wherein each component of the stacked bar represents a DRAM power
state (Idle, Refresh, Active, Active Power-down, Precharge Power-down
and Self-refresh). The script generates one plot per delay value. It
also generates a pdf (--pdf option) in which the graphs are laid out
such that you can easily compare how the increasing delay and other
swept params affect the resulting energy.

Change-Id: Id80b0947bfde27e11e5505b23a3adb30f793a43f
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5727
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Add tests for DRAM low power modes

This patch adds two regression tests that execute the script in the
configs dir for triggering low power mode transitions. A separate
test is required for each page policy because for close-adaptive
page policy the DRAM goes into the Precharge Power-down mode while
for open-adaptive page policy it goes into the Activate Power-down
mode.

Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5726
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Add low power sweep for DRAM

This change adds a Python script to sweep a few parameters with a
goal to trigger transitions to the low power states of the DRAM
controller.

This script is largely based on the sweep.py but is helpful to study
the impact of inter-transaction delay on the behaviour of the DRAM
in addition to typical sweep params like stride size, bank
utilization and read percent. An idle period is added as the last
traffic generator state to target hitting self-refresh.

Change-Id: I34380afffbf2de9f4e997dfe9fff5e615e077524
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5725
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

ext, mem: Pull DRAMPower SHA 90d6290 and rebase

This patch syncs the DRAMPower library of gem5 to the
external github (https://github.com/ravenrd/DRAMPower).

The version pulled in is the commit:
90d6290f802c29b3de9e10233ceee22290907ce6
from 30th Oct. 2016.

This change also modifies the DRAM Ctrl interaction with the
DRAMPower, due to changes in the lib API in the above version.

Previously multiple functions were called to prepare the power
lib before calling the function that would calculate the enery. With
the new API, these functions are encompassed inside the function to
calculate the energy and therefore should now be removed from the
DRAM controller.

The other key difference is the introduction of a new function called
calcWindowEnergy which can be useful for any system that wants
to do measurements over intervals. For gem5 DRAM ctrl that means we
now need to accumulate the window energy measurements into the total
stat.

Change-Id: I3570fff2805962e166ff2a1a3217ebf2d5a197fb
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5724
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

pwr: Enable multiple power models per component

This patch allows the user to specify more than one
power model for any given Clocked Object. This is
useful and some times necessary to properly model
components that have multiple power sources (or
subcomponents) but gem5 doesn't model them.

The ideal solution would be to have a DictParam
to replace the VectorParam so each model can have
a name and can be identified in the stats file.

Change-Id: I4080a7054a16b56069c44750a7a9ce4e674cdf9d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5733
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, arm: Print value being ignored on DummyISA write

When ignoring writes to the Dummy ISA device (DummyISADevice),
additionally print the value being ignored in the diagnostic.

Sometimes it is useful to know exactly what we are dropping ...

Change-Id: I9a01623611f0da0aa12b065fbb2031aa27e2c036
Signed-off-by: Sean McGoogan <Sean.McGoogan@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5731
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Clocked object debug message updated for clarity

Change-Id: I5bbf36ef21ac14d9edf68ec6766d33f88e84d308
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5729
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim: Add an option to load additional kernel objects

There are cases where it is desirable to load a kernel and a set of
additional objects. This can, for example, be useful for testing where
the bootstrap code can be loaded from one object (the kernel) and the
test proper from another.

This changeset adds this functionality by adding a kernel_extras
vector parameter to the System class. Object files in this vector are
loaded in order after the kernel when running in full system mode.

Change-Id: I06f57c6a65a17b02eb4267bed0aa829f21bcfa3b
Reviewed-on: https://gem5-review.googlesource.com/5703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Dsb instruction shouldn't flush the pipeline

DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter
attribute will be removed for either the 32 and 64 bit version.

Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5363
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Writes to DCCMVAC shouldn't flush pipeline

Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register
shouldn't flush the pipeline as a result of the operation. This addition
was wrongly introduced for supporting self-modifying code. Software
barriers should be used instead.

Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5362
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Removing FlushPipe fault, using SquashAfter

This Patch is removing the FlushPipe ArmFault, which was used for
flushing the pipeline in favour of the general IsSquashAfter StaticInstr
flag. Using a fault was preventing tracers from tracing barriers like
ISB and from adding them to the instruction count

Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5361
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for armv8 CRC32 instructions

This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32

Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Remove support for hg patches in patch creation script

Simplify the patch creation helper script by removing support for
automatic conversion to Mercurial's patch format. We no longer use
Mercurial as a primary repository, so this support is not likely to be
needed again.

Change-Id: I83f6efb9ccaee9c548b33257a4d6128153750c76
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5162
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Optionally search entire history when listing changes

The helper script to list changes currently only looks at the changes
between a branch point and two heads. This helps performance, but
sometimes misclassifies changes that exist both in the upstream
branch before the branch point and in a feature branch. Such changes
should normally not exist, but can be the product of an incorrect
rebase.

This change adds an option to the helper script to search the entire
upstream repo history when determining the set of upstream
changes. When this option is provided, the script lists the changes
that exist upstream before the branch point and in the feature branch
as "Incorrectly rebased changes".

Change-Id: I4cb72cea2152c49d0317dc43613be94a0a2de1e5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5161

cpu, probe: Fix elastic trace register dependency

Change-Id: I017852eac183fac3f914fdb96d7e72a56ea9d682
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5121
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Fix the "script" SysPath functor.

This particular functor looks in the config root, not in the path
specified by M5_ROOT like binary and disk.

Change-Id: Ib007c36934c65ca9f808e995a2e0c71f0b338788
Reviewed-on: https://gem5-review.googlesource.com/5641
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

config: Add an Energy param type.

This type expects values in joules (J).

Change-Id: I77a3a4f1c19443f573d5fe7a84d5abd954ce1603
Reviewed-on: https://gem5-review.googlesource.com/5625
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Export the "Current" param type from m5.params.

This type was defined, but it was never added to __all__.

Change-Id: I5414829a9562790416f5ceab71af01503d142903
Reviewed-on: https://gem5-review.googlesource.com/5624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Add a "toEnergy" function to the convert module.

Change-Id: I7299af0e2a6ce9bd2272d6ccb898997336e95e51
Reviewed-on: https://gem5-review.googlesource.com/5623
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Simplify the definitions of the Voltage and Current params.

These had a lot of code which duplicated what was already in the
Float param value class. Also, printing into the ini file with "%f"
forces python to truncate values which require more precision than the
fixed float format supports.

Change-Id: Iad9623b71a31d17b69c184082585dcbb881eaa20
Reviewed-on: https://gem5-review.googlesource.com/5622
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Interface for the ArmStaticInst intWidth field

ARMv8 Tracers might want to be able to read the intWidth field of the
ArmStaticInst object. The field is specifying the bit width of the
integer registers used by the current instruction.

Change-Id: Iaee3123823a2c7380917001c453377c1c12e54a7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Corrected encoding for T32 HVC instruction

This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.

Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5541
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util: Simplify/consolidate the python conversion module.

The python conversion module was really repetitive and fragmented,
where some types of conversions use common code, and some use hand
written case statements which did something very similar. Also, some
types like Voltage could only handle V and mV but no other scaling
prefix.

This change restructures the module to centralize a lot of the unit
handling code into toFloat, and makes the various other functions use
it.

Change-Id: Ic8529203cc226c9b551b8535a444e3f2f25ad1eb
Reviewed-on: https://gem5-review.googlesource.com/5621
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Move Transform and termcap functionality into their own files.

Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7
Reviewed-on: https://gem5-review.googlesource.com/5565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Move python path management out of the SConstruct.

Make site_init.py manage sys.path, and the "default" tool set
PYTHONPATH on any environment that's created. The paths to add are
tracked in a common gem5_python_paths.py.

Change-Id: I3387d4394d47a2f9c83322644cfd05909c6890fa
Reviewed-on: https://gem5-review.googlesource.com/5564
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Pull style hook management out of the main SConstruct.

Put the code which supports style hooks for mercurial and git into two
scons "tools".

Change-Id: I3ffed85a177be4f9e458fff7b1cf16a3a479914e
Reviewed-on: https://gem5-review.googlesource.com/5563
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Override the "default" tool to set up the default env.

This imports various environment variables into the scons environment,
and sets some general properties on it. These are basically just copied
directly from the SConstruct and have the same behavior here.

gem5_tool_list will be used later on to add scons "tools" which should
be automatically added to new Environment objects.

Change-Id: Ib255955090c7b1e1cb80c703c18a9c867fcf1c9e
Reviewed-on: https://gem5-review.googlesource.com/5562
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Move scons and python version checking into site_init.py.

In an effort to shrink and modularize the main scons files, this
change pulls the scons and python version checking code out of the
main file and into site_init.py which runs before the SConstruct
starts. This will be a place to put really generic code which has to
do with the very fundemental aspects of getting scons to work. Other
checks, like checks for particular tools or particular versions of
tools, will happen in other more specialized files.

Change-Id: Icd00ecadbe1141aef4dbadcf42d6ddef1f3a701f
Reviewed-on: https://gem5-review.googlesource.com/5561
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Align the snoop behavior in the XBar for atomic and timing

When the XBar receives a Writeback/WriteClean packet, it doesn't need
to snoop the upstream caches. It only queries the snoop filter and
sets the blockCached flag accordingly. This is in line with the
recvTimingReq.

Change-Id: I0ae22f21491d75a111019124bb95bac7b16d3cd3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5043
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1

A program running in EL0 is allowed to execute CMOs when the UCI bit
in SCTLR is set. The execution of dc ivac, however, would fault
uncoditionally when executed from EL0. This change aligns the
permission checks for dc ivac with the rest of the CMOs.

Change-Id: I1a532f37707c7dc0748b4375252c6ec0bbf95419
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5058
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Move generic serial devices to src/dev/serial

Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4291
Reviewed-by: Gabe Black <gabeblack@google.com>

dev: Add a dummy serial device

Add a dummy serial device that discards any output and doesn't provide
any input. This device can be used to terminate UARTs that don't have
a default device (e.g., a terminal) attached.

Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4290
Reviewed-by: Gabe Black <gabeblack@google.com>

dev: Refactor UART->Terminal interface

The UART models currently assume that they are always wired to a
terminal. While true at the moment, this isn't necessarily a valid
assumption. This change introduces the SerialDevice class that defines
the interface for serial devices. Currently, Terminal is the only
class that implements this interface.

Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4289
Reviewed-by: Gabe Black <gabeblack@google.com>

alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.

In the ISA instruction definitions, some classes were declared with
execute, etc., functions outside of the main template because they
had CPU specific signatures and would need to be duplicated with
each CPU plugged into them. Now that the instructions always just
use an ExecContext, there's no reason for those templates to be
separate. This change folds those templates together.

Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa
Reviewed-on: https://gem5-review.googlesource.com/5401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim-se: Add prlimit system call

Some ISAs (namely RISC-V) implement getrlimit and setrlimit using
prlimit. This patch adds an implementation for the prlimit system call.
Normally prlimit is supposed to provide the functionality of both
getrlimit and setrlimit, but because gem5 does not support setrlimit
this implementation of prlimit will simply display a warning and return
a failure code if the setrlimit mode is used. The same thing will happen
if a pid other than 0 is passed to it.

Change-Id: I653af2d5a60e716f4d6286196be7600409efcef8
Reviewed-on: https://gem5-review.googlesource.com/5321
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.

Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.

Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Rework the SysPaths functions into functors.

These functions were already being treated as psuedo objects and had
properties assigned to them setting what their paths were. That's a bit
unusual and made it less obvious what the code was doing, but also
forced the "system" function to know what all the possible path
searching functions were so that they'd have their "path" property
initialized properly in a central location.

This change introduces a PathSearcFunc class which encapsulates the
mechanisms of the old code and makes it implicitly extensible so that
other path searching functions which might look in other directories
can be added in other places.

Change-Id: I7be28e51481a06ec83997677af99927709b18003
Reviewed-on: https://gem5-review.googlesource.com/5341
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Using Configurable image writer in HDLcd

The fixed image writer (which was dumping .bmp images only) has been
replaced by the configurable one in HDLcd device.  Default format is
Auto, which gives gem5 the freedom to choose the format it prefers.

Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5183
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

vnc: Default image writer type set to Auto

This commit modifies the default behaviour of the vnc frame dumping
process: rather than using 'Bitmap' as a default parameter value, it is
using 'Auto'.  Auto parameter is letting gem5 to choose the most
efficient image format among the available ones.

Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5182
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Introducing utility for writing raw data in png format

Originally it was possible to use a Bitmap writer class for dumping a
framebuffer snapshot in a .bmp file. This patch enables you to choose
another format.  In particular it implements the writing of PNG Images
using libpng library.  The latter has to be already installed in your
machine, otherwise gem5 will default to the Bitmap format.  This
configurable writer has been introduced in the VNC frame dumping mechanism,
which is storing changed frame buffers from the VNC server

Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5181
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Fix VEX instruction decoding.

When decoding VEX prefixed instructions, the x86 predecoder wasn't walking
past the opcode byte and so was also interpreting it as the modRM byte.

Reported-by: likunxi@fas.harvard.edu
Change-Id: I6d4bdabfa03411704c48d905c50c7b23072fc615
Reviewed-on: https://gem5-review.googlesource.com/5281
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Fix forcing loopback only binding for listeners.

Despite online documentation, the type used for sin_addr.s_addr is not
actually an unsigned long, it is an in_addr_t. When an unsigned long is a 64
bit value, the endian conversion moves the relevant bits of the 32 bit
in_addr_t to positions which are truncated away. This forces the value to 0
which means to bind to any interface, the opposite of the intended effect.

Change-Id: I53c63dea6bd88144dfef1a9a49b478fab30a8ba2
Reviewed-on: https://gem5-review.googlesource.com/5301
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: RBIT instruction using mirroring func

The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.

Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Function for mirroring bits in variable length word

This patch introduces a high-speed template function for mirroring the
bits (MSB=>LSB) in a variable length word. The function is achieving
high performances since it is using a look-up table.

Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Defining make_unique for C++11

std::make_unique is not available for C++11 compilers, and it has been
introduced only in C++14.  Since gem5 is not officially supporting the
latter at the moment, this patch allows to use it in gem5 if including
base/compiler.hh. If compiled under C++14, std::make_unique will be
used instead.

Change-Id: Ibf1897fad0a1eb1cb0c683cc25170feaa6841997
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5201
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Add M5_VAR_USED to variable

Fixes compile error for gem5.fast on CLANG due to unused variable.

Change-Id: Iabe777a27d75ee8bfa7b214fff577aed3c7582c7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4980
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

scons: Fix the regression tests.

A recent scons cleanup introduced a small bug when setting the variant path of
the regression test SConscript. When turned into a relative path, the
directory can be interpreted differently depending on what it's considered
relative to. When left as a scons node, there is no ambiguity.

Change-Id: I162afdc4fcef81db096ec8304f81bc98fa6bf899
Reviewed-on: https://gem5-review.googlesource.com/5221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Stop generating inc.d in the isa parser.

Generating dependency/build product information in the isa parser breaks scons
idea of how a build is supposed to work. Arm twisting it into working forced
a lot of false dependencies which slowed down the build.

Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca
Reviewed-on: https://gem5-review.googlesource.com/5081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Fix inverted 32/64-bit check in GDB

Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0
Reviewed-on: https://gem5-review.googlesource.com/4720
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Filter out the For-Upstream commit message tag

Some internal review flows, e.g. the flow used by ARM Research, uses
the For-Upstream tag to indicate that a change has been approved for
upstream. This tag isn't meaningful outside of the internal review
system. Remove it automatically when running the maintainer script to
prepare patches to be posted upstream.

Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5141
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Signal an event when executing store exclusives

When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.

Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4480
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Signal the local monitor when clearing the global monitor

ARM systems require the coordination of the global and local
monitors. When the system is run without caches the global monitor is
implemented in the abstract memory object. This change adds a callback
from the abstract memory that notifies the local monitor when the
global monitor is cleared.

Additionally, for ARM systems the local monitor signals the event
register and wakes the thread context up. Subsequent wait-for-event
(WFE) instructions will be immediately signaled.

Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3760
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Check predication before the SQ size for a debug print

The size of the store entry in the LSQ is used to indicate a fault in
the execution of the store. At the same time, a store that is
predicated false will also have 0 size in the corresponding store
queue entry. This changeset ensures that we check if the store was
predicated false before checking the size field. This way we avoid
printing stores as faulting when they are only predicated false.

Change-Id: Ie07982197bd73d7b44d26a3257d54ecb103a952a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-o3: Avoid early checker verification for store conditionals

The O3CPU allows stores to commit before they are completed and as
soon as they enter the store queue. This is the reason why stores are
verified by the the checker CPU, separately, once they complete
and after they are sent to the memory.

Store conditionals, on the other hand, have an additional writeback
stage in the pipeline as they return their result to a register,
similarly to loads. This is the reason why they do not commit
before they receive a response from the memory. This allows store
conditionals to be verified by the checker CPU as soon as they
commit in the same way as all other non-store insturctions.

At the same time, the presense of a checker CPU should not require
changes to way we handle instructions. This change removes explicit
calls to:
* incorrectly set the extra data of the request to 0 (a subsequent
  call to completeAcc already does this without making any ISA
  assumptions about the return value of the failed store conditional)
* complete failing store conditionals

Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4820
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Fix path for module imports in ARM system configs again

One configuration was missed in
 "tests: Fix path for module imports in ARM system configs",
which this changeset remedies.

Change-Id: I705e64298a8251dcfefbdca927d61c9bbb8bbea7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4940
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Add util/packet_pb2.py to .gitignore.

This file is automatically generated and not managed by git.

Change-Id: I077fe1ad89b65716a829b783a8b9c6e23b4d0b6b
Reviewed-on: https://gem5-review.googlesource.com/5006
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Use a Makefile to ensure util/packet_pb2.py is up to date.

Rather than just ensuring that packet_pb2.py is available in general, use a
Makefile to ensure that it's also up to date in case packet.proto has
changed.

Also, remove a check that ensures that the protobuf module is available,
since python will complain if it needs it and can't find it.

Finally, remove a comment which talks about manually regenerating the
packet_pb2.py module, something that hasn't been necessary for a while, even
with the old version of this code.

Change-Id: I40c5c1f577e6d7ad1af9a209309a1eb92f073317
Reviewed-on: https://gem5-review.googlesource.com/5005
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: When building packet_pb2.py, don't assume a particular CWD.

Allow the script to be run from anywhere, and compute the paths relative to
where the script is. The script is assumed to be in util.

Change-Id: I8500ef959f2ff8119540c956f2b27789c96de60e
Reviewed-on: https://gem5-review.googlesource.com/5004
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Make decode_packet_trace.py print the new master ID fields.

Those fields are "repeated" which means they can appear zero times, which
they will in older style traces.

Change-Id: Ib6ff4aab521332cf1405549d0d6e922c51c12f32
Reviewed-on: https://gem5-review.googlesource.com/5003
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Small style fix in _EncodeVarint32.

Added spaces around the '|' operator.

Change-Id: I5cb82b98e7d2769605cde141f76a62a6e3c6570d
Reviewed-on: https://gem5-review.googlesource.com/5002
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Rename the (De|En)codeVarint function _(De|En)codeVarint32.

DecodeVarint implicitly truncates its inputs to 32 bits, and that should be
obvious from its name, and so not a surprise to the caller. EncodeVarint also
has the suffix added for consistency. Both functions are only used in
protolib.py, so add a _ to make it private (in the python sense) to the
module.

Change-Id: I835295717bb51672351b963fe1227ed619836f22
Reviewed-on: https://gem5-review.googlesource.com/5001
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Fix the indentation in DecodeVarint in util/protolib.py.

The DecodeVarint was, as a comment describes, lifted from
google.protobuf.internal.decoder. Unfortunately, the relative indentation of
some lines was changed, changing what scope they fell under. This changed the
behavior of the function, breaking it for multibyte and negative values.

This change restores the correct indentation and fixes the function's
behavior.

Change-Id: If645649506b0fe5a617b37a8202c9ca1c57aaf15
Reviewed-on: https://gem5-review.googlesource.com/5000
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tlm: Elastic Trace Example with L2 Cache Added

The SystemC TLM examples already include an example setup for elastic
traces. However, in the provided examples the L2 cache is omitted. This
patch provides an additionall example, which also includes an L2 cache
on the gem5 side.

Change-Id: I49e9fa074b60007694abff37663f0400caf72099
Reviewed-on: https://gem5-review.googlesource.com/4900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim-se: Fix mremap for downward growing mmap regions

mremapFunc(...) did not respect Process::mmapGrowsDown(). This resulted
in an attempt to remap into an already allocated region and a panic in
FuncPageTable::allocate(...). This behavior can be observed in
435.gromacs.

Change-Id: Ib3ad33816126c76506d69679bdcefa7a98ef69f9
Reviewed-on: https://gem5-review.googlesource.com/4700
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-x86: fix CondInst decoding for MOV to Control Registers

MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).

This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .

Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Reviewed-on: https://gem5-review.googlesource.com/4861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: change panic for Vector traceData to warn_once

Make the traceData panic for Vectors a warn_once.  It's a pity it's
not implemented but it's not a reason to abort the simulation entirely.

Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df
Reviewed-on: https://gem5-review.googlesource.com/4860
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: make compile on FreeBSD prior to 11

FreeBSD before the early 11 development is expecting a char *
for stack.ss_sp rather than the standards compliant void *.
Catch that case and allow gem5 to compile on old FreeBSD versions.

Change-Id: Ic0ae560b52bfe5b3905ae87df791d349e053ec97
Reviewed-on: https://gem5-review.googlesource.com/4660
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Make dot_writer ignore NULL simobjects.

Also centralize the code which iterates over the parameters of a simnode's
children, and remove a copy/paste block of code in the DVFS block of code.

Change-Id: I01305fbff59346010780ee386ba97ad9106b1f5d
Reviewed-on: https://gem5-review.googlesource.com/4849
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

dev: Make the IDE controller handle NULL simobject pointers.

Only panic if there are disks which would actually be connected to it beyond
its limit. Also skip past disks which are set to NULL. This is useful since
it lets you set up disks on different ports of the controller instead of
filling them contiguously.

Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7
Reviewed-on: https://gem5-review.googlesource.com/4848
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

sim: Add a get_config_as_dict to the NullSimObject class.

Change-Id: I1ba6f6b196b7dfa790d1baaa23640bb3ed73f450
Reviewed-on: https://gem5-review.googlesource.com/4847
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

sim: Don't add the NULL SimObject as a child of other SimObjects.

Change-Id: Ibdc48af8e5a461077f75d781cfd8191586c54115
Reviewed-on: https://gem5-review.googlesource.com/4846
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

misc: Make the m5 utilities writefile command accept a host path.

When the writefile command is given one command line argument, it's treated
as the name of the file in the simulation and on the host. When there are two
arguments, the first is the filename in the simulation, and the second is the
name on the host.

Change-Id: I402925a9ff89665bee9910fb18b7f8b06b8f7d35
Reviewed-on: https://gem5-review.googlesource.com/4850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Give the NullSimObject singleton a _name.

The name is 'Null', and is what __str__ returns.

Change-Id: I113f52496f5e9133b8d03206289b719fda003582
Reviewed-on: https://gem5-review.googlesource.com/4845
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a NullSimObject.descendants function.

Null simobjects don't have any descendants.

Change-Id: Ia43a99056709f422c9c817c017912d23d689fb1e
Reviewed-on: https://gem5-review.googlesource.com/4844
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a clear_parent function to NullSimObject.

Change-Id: I3842176f147997105fcc62aaf9cb93b9896708be
Reviewed-on: https://gem5-review.googlesource.com/4843
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Check the SimObjectVector.has_parent function to use the "any" function.

The existing code was essentially doing the same thing, but in a more
roundabout and obscure way. One difference between the two versions is that
I believe this will stop as soon as it encounters an element without a
parent, where the original version would call has_parent() on all the
elements regardless.

Change-Id: Ia1fef3083fc88fca11f8ecfca453476e33194695
Reviewed-on: https://gem5-review.googlesource.com/4842
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Only consider non-NULL elements in SimObjectVector.has_parent.

NullSimObject doesn't have a has_parent function, and it's not clear what its
return value should be if one were added. The appropriate value seems to
depend on why some other bit of code is checking if there's a parent in the
first place.

In SimObjectVector, the has_parent function is checking whether all of its
elements have a parent. In this particular case, the most reasonable thing
to do seems to be to just skip those elements.

Change-Id: I5f8cad66d1b22c5e37962492fd77cff9371e5af8
Reviewed-on: https://gem5-review.googlesource.com/4841
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a set_parent to NullSimObject which does nothing.

This lets attempts to set_parent on NullSimObject fall away harmlessly
without having to add a bunch of checks whenever set_parent is called.

Change-Id: I6d3510772ba71e765c4739e486e9f3d2460c4e11
Reviewed-on: https://gem5-review.googlesource.com/4840
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Fill the new packet ID fields with master IDs when tracing packets.

This will let somebody consuming the memory packet trace make sense out of
the master IDs passed along with individual accesses.

Change-Id: I621d915f218728066ce95e6fc81f36d14ae7e597
Reviewed-on: https://gem5-review.googlesource.com/4800
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Add a "map" of packet IDs to strings in probe traces.

This map is intended to map from request MasterIDs to master names. It could
be used to map to arbitrary strings in other situations, however.

The original idea to store this information was to add a new message type
which would store one ID and the string associated with it. This change stores
the IDs in the header instead so that they'll be easy to find and all
available before the packet data.

One downside of this approach is that it won't be possible to add new master
ID strings as they come up during a trace. If that becomes an issue, the two
approaches could be combined and messages could be added which would augment
the map in the header.

Also worth mentioning is that the proto2 version of the protobuf description
language does not support the "map" field type, and the protoc compiler on my
workstation doesn't support proto3. Because that's such an appropriate
representation for this data, the map is represented in an equivalent format
described in the proto3 documentation.

Change-Id: I137c8611c33d9ce6589e196d50c8638c1d88750c
Reviewed-on: https://gem5-review.googlesource.com/4782
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Trace the request master ID in the MemTraceProbe.

There's a spot for it in the packet trace protobuf, so we should fill it
with something.

Change-Id: I784feb3f668e1b20d67b6ef98d012bcf59b7bd40
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3483
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4781
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Record the request master ID in the PacketInfo structure.

That can be recorded in a packet trace.

Change-Id: I3813ab4ea5aadeb40b355ff01f10e8ecab2bb790
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3482
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4780
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev, virtio: Improvements to diod process handling

* When dispatching multiple gem5 simulations at once, they race
for the socket id, resulting in a panic when calling 'bind'. To
avoid this problem, the socket id is now created before the diod
process is created.  In case of a race, a panic is called in the
gem5 process, whereas before the panic was called in the diod
process where it didn't have any effect.

* In some cases killing the diod process in terminateDiod() using
only SIGTERM failed, so a call using SIGKILL is added.

Change-Id: Ie10741e10af52c8d255210cd4bfe0e5d761485d3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

alpha: Move some initialization logic from loadState into unserialize.

The primary difference between loadState and unserialize, at least when
eventually using the default SimObject implementation of loadState, is that
unserialize is called only if there's a corresponding section in the
checkpoint being restored. In this particular case, the AlphaProcess class
calls the generic Process unserialize function, and that does other critical
initialization like set up the processes page table. If the unserialize
function isn't called, other serious problems would break the simulation
anyway.

This removes the final custom implementation of loadState.

Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6
Reviewed-on: https://gem5-review.googlesource.com/4741
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Stop using loadState in the Root SimObject.

The primary difference between using loadState and letting the default
implementation of loadState call unserialize is that whether or not that code
is called is dependent on that object being associated with a section in the
checkpoint file being unserialized. Since there's always a "root" object,
there should always be a section for it in the checkpoint and those should be
equivalent.

This removes one custom implementation of the loadState function.

Change-Id: Ia674ccc18e141f38746e22ccfddc21475b1a0731
Reviewed-on: https://gem5-review.googlesource.com/4740
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

kvm: arm: Get rid of functions which just wrap the subclasses version.

The MuxingKvmGic class defined a few functions related to checkpointing which
did nothing other than call the underlying Pl390 implementation. These are
unnecessary in general, and are particularly unnecessary for the loadState
function which is a very lightly used part of the checkpointing interface.
It's not actually defined in Pl390 either, and falls through to the
underlying implementation.

Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff
Reviewed-on: https://gem5-review.googlesource.com/4760
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tlm: Don't set SystemC time resolution

Some simulators already set the time resolution of SystemC. By coupling
gem5 by means of SystemC with an other tool this can lead to problems:
When the resolution is set twice the simulation will not work.
Therefore, the line is changed to an assertion that checks if the time
resolution of the SystemC simulation is set to gem5's value of 1ps.

Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
Reviewed-on: https://gem5-review.googlesource.com/4520
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

stats: Move the swpipl function into the Alpha kernel stats.

This stat is only incremented by Alpha. Also move the _hwrei into the Alpha
stats object since it's the class that actually sets up and maintains that
value and it probably should have been there all along.

Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0
Reviewed-on: https://gem5-review.googlesource.com/4601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

stats: Get rid of some kernel stats related cruft.

The kernel stat mechanism should really be refactored and moved somewhere
else, but in the mean time there's some old cruft that can be cleared away.

Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86
Reviewed-on: https://gem5-review.googlesource.com/4600
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fix bi-mode branch predictor thresholds

When different sizes were set for the choice and global saturation
counter (e.g. ex5_big), the threshold calculation used the wrong
size. Thus the branch predictor always predicted "not taken" for
choice > global.

Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110
Reviewed-on: https://gem5-review.googlesource.com/4560
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-minor: Fix for addr range coverage calculation

Coverage was wrongly set to PartialAddrRangeCoverage in the case of
disjoint adjacent ranges

Change-Id: I29aaf5145e6cdcf5f0b8f4e009d57ee57bd4c944
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4640
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: bump required python version to 2.7 to support pybind11

Change-Id: Ic3652f975477f2e5d144e054489ab73ed9f82b55
Reviewed-on: https://gem5-review.googlesource.com/4440
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Only increment SW PMU counters on writes to PMSWINC

When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).

Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add missing override keywords in fault.hh

Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

arch-x86: Add missing override in the X86 TLB

Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4283
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-sparc: Add a FaultVals instantiation for VecDisabled

Recent gcc versions complain about a missing VecDisabled not having an
explicit FaultVals instantiation.

Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4282
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-alpha: Add missing overrides

Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>