David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: add request types for acquire and release
Add support for acquire and release requests. These synchronization operations
are commonly supported by several modern instruction sets.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: allocate a block in CacheMemory without updating LRU state
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly
invalidate all cache blocks using a trigger queue rather than rely on each
individual cache block to be invalidated via requests from the mandatory
queue.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for arbitrary DPRINTF flags (not just RubySlicc)
This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for local variable declarations in action blocks
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: initialize replacement policies with their own simobjs
this is in preparation for other replacement policies that take additional
parameters.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for multiple cache entry types in the same state machine
To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:
structure(DirEntry, desc="...", interface="AbstractCacheEntry",
main="false") {
...and the primary type would be declared:
structure(Entry, desc="...", interface="AbstractCacheEntry") {
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: Fix bug in enqueue and peek statements.
These were not generating the correct c names for types declared within a
machine scope.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: fix missing inline function in LocalVariableAST
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: improve support for prefix operations
This patch fixes the type handling when prefix operations are used. Previously
prefix operators would assume a void return type, which made it impossible to
combine prefix operations with other expressions. This patch allows SLICC
programmers to use prefix operations more naturally.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for transitions with a wildcard next state
This patches adds support for transitions of the form:
transition(START, EVENTS, *) { ACTIONS }
This allows a machine to collapse states that differ only in the next state
transition to collapse into one, and can help shorten/simplfy some protocols
significantly.
When * is encountered as an end state of a transition, the next state is
determined by calling the machine-specific getNextState function. The next
state is determined before any actions of the transition execute, and
therefore the next state calculation cannot depend on any of the transition
actions.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for multiple message types on the same buffer
This patch allows SLICC protocols to use more than one message type with a
message buffer. For example, you can declare two in ports as such:
in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... }
in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
Brad Beckmann [Sat, 1 Aug 2015 16:37:52 +0000 (12:37 -0400)]
slicc: fatal->panic on invalid transitions
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: Hit callback delay fix
This patch was created by Bihn Pham during his internship at AMD.
There is no need to delay hit callback response messages by a cycle because
the response latency is already incurred in the Ruby protocol. This ensures
correct timing of memory instructions.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
cpu: Fixed a bug on where to fetch the next instruction from
Figure out if the next instruction to fetch comes from the micro-op ROM
or not. Otherwise, wrong instructions may be fetched.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
x86: x86 instruction-implementation bug fixes
Added explicit data sizes and an opcode type for correct execution.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
util: added .cl OpenCL extension to file_type.py
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
util: added .mk makefile extension to file_types.py
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: re-added the addressToInt slicc interface function
This helper function is very useful converting address offsets to integers
that can be used for protocol specific destination mapping.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
syscall: Add readlink to x86 with special case /proc/self/exe
This patch implements the correct behavior.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: add useful dprints to sequencer
Added two data block dprints that are useful when tracking down data check
failures in the ruby random tester.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: isinstance bugfix
This fix prevents spurious errors when searching for a symbol that may be
located in one of multiple symbol tables.
Anthony Gutierrez [Sat, 1 Aug 2015 02:53:17 +0000 (22:53 -0400)]
util: add a vimrc that matches gem5 style guide
Andreas Sandberg [Fri, 31 Jul 2015 16:04:59 +0000 (17:04 +0100)]
stats: Update switcheroo reference stats
The Minor draining fixes affect perturb the timing slightly since it
affects how the simulator is drained. Update reference statistics to
reflect this expected change.
Andreas Sandberg [Fri, 31 Jul 2015 16:04:59 +0000 (17:04 +0100)]
cpu: Update debug message from Fetch1 isDrained() in Minor
Fix a spurious %s and include the state of the Fetch1 stage in the
debug printout.
Andreas Sandberg [Fri, 31 Jul 2015 16:04:59 +0000 (17:04 +0100)]
cpu: Fix Minor drain issues when switched out
The Minor CPU currently doesn't drain properly when it is switched
out. This happens because Fetch 1 expects to be in the FetchHalted
state when it is drained. However, because the CPU is switched out, it
is stuck in the FetchWaitingForPC state. Fix this by ignoring drain
requests and returning DrainState::Drained from MinorCPU::drain() if
the CPU is switched out. This is always safe since a switched out CPU,
by definition, doesn't have any instructions in flight.
Andreas Sandberg [Thu, 30 Jul 2015 09:16:36 +0000 (10:16 +0100)]
stats: Bump stats after Minor switcheroo inclusion
Andreas Sandberg [Thu, 30 Jul 2015 09:16:28 +0000 (10:16 +0100)]
tests: Add Minor to the ARM full switcheroo tests
Add the Minor CPU to the RealView and RealView64 full switcheroo
tests.
Andreas Sandberg [Thu, 30 Jul 2015 09:15:50 +0000 (10:15 +0100)]
cpu: Only activate thread 0 in Minor if the CPU is active
Minor currently activates thread 0 in startup() to work around an
issue where activateContext() is called from LiveProcess before the
process entry point is known. When activateContext() is called, Minor
creates a branch instruction to the process's entry point. The first
time it is called, the branch points to an undefined location (0). The
call in startup() updates the branch to point to the actual entry
point.
When instantiating a switched out Minor CPU, it still tries to
activate thread 0. This is clearly incorrect since a switched out CPU
can't have any active threads. This changeset adds a check to ensure
that the thread is active before reactivating it.
Andreas Sandberg [Thu, 30 Jul 2015 09:15:50 +0000 (10:15 +0100)]
cpu: Fix drain issues in the Minor CPU
The drain refactor patches introduced a couple of bugs in the way
Minor handles draining. This patch fixes an incorrect assert and a
case of infinite recursion when the CPU signals drain done.
Andreas Hansson [Thu, 30 Jul 2015 07:42:27 +0000 (03:42 -0400)]
stats: Update stats for clean eviction addition
Andreas Hansson [Thu, 30 Jul 2015 07:42:25 +0000 (03:42 -0400)]
mem: Add missing clean eviction on uncacheable access
This patch adds a missing clean eviction, occuring when an uncacheable
access flushes and invalidates an existing block.
Andreas Hansson [Thu, 30 Jul 2015 07:41:43 +0000 (03:41 -0400)]
mem: Remove unused RequestCause in cache
This patch removes the RequestCause, and also simplifies how we
schedule the sending of packets through the memory-side port. The
deassertion of bus requests is removed as it is not used.
David Guillen-Fandos [Thu, 30 Jul 2015 07:41:42 +0000 (03:41 -0400)]
mem: Make caches way aware
This patch makes cache sets aware of the way number. This enables
some nice features such as the ablity to restrict way allocation. The
implemented mechanism allows to set a maximum way number to be
allocated 'k' which must fulfill 0 < k <= N (where N is the number of
ways). In the future more sophisticated mechasims can be implemented.
Andreas Hansson [Thu, 30 Jul 2015 07:41:40 +0000 (03:41 -0400)]
mem: Transition away from isSupplyExclusive for writebacks
This patch changes how writebacks communicate whether the line is
passed as modified or owned. Previously we relied on the
isSupplyExclusive mechanism, which was originally designed to avoid
unecessary snoops.
For normal cache requests we use the sharedAsserted mechanism to
determine if a block should be marked writeable or not, and with this
patch we transition the writebacks to also use this
mechanism. Conceptually this is cleaner and more consistent.
Andreas Hansson [Thu, 30 Jul 2015 07:41:39 +0000 (03:41 -0400)]
mem: Tidy up CacheBlk class
This patch modernises and tidies up the CacheBlk, removing dead code.
Andreas Hansson [Thu, 30 Jul 2015 07:41:38 +0000 (03:41 -0400)]
mem: Tidy up packet
Some minor fixes and removal of dead code. Changing the flags to be
enums rather than static const (to avoid any linking issues caused by
the latter). Also adding a getBlockAddr member which hopefully can
slowly finds its way into caches, snoop filters etc.
Andreas Hansson [Thu, 30 Jul 2015 07:41:36 +0000 (03:41 -0400)]
stats: Bump stats to match current behaviour
Somehow this one seems to have slipped through. Perhaps
non-determinism somewhere?
Andreas Hansson [Thu, 30 Jul 2015 07:41:22 +0000 (03:41 -0400)]
cpu: Fix issue identified by UBSan
Nilay Vaish [Tue, 28 Jul 2015 06:58:04 +0000 (01:58 -0500)]
Nilay Vaish [Sun, 26 Jul 2015 15:21:20 +0000 (10:21 -0500)]
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Nilay Vaish [Sun, 26 Jul 2015 15:20:07 +0000 (10:20 -0500)]
cpu: o3: slight correction to identation in rename_impl.hh
Brandon Potter [Fri, 24 Jul 2015 19:25:23 +0000 (12:25 -0700)]
style: change Process function calls to use camelCase
The Process class methods were using an improper style and this subsequently
bled into the system call code. The following regular expressions should be
helpful if someone transitions private system call patches on top of these
changesets:
s/alloc_fd/allocFD/
s/sim_fd(/simFD(/
s/sim_fd_obj/getFDEntry/
s/fix_file_offsets/fixFileOffsets/
s/find_file_offsets/findFileOffsets/
Brandon Potter [Fri, 24 Jul 2015 19:25:23 +0000 (12:25 -0700)]
syscall_emul: standardized file descriptor name and add return checks.
The patch clarifies whether file descriptors are host file descriptors or
target file descriptors in the system call code. (Host file descriptors
are file descriptors which have been allocated through real system calls
where target file descriptors are allocated from an array in the Process
class.)
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
base: refactor process class (specifically FdMap and friends)
This patch extends the previous patch's alterations around fd_map. It cleans
up some of the uglier code in the process file and replaces it with a more
concise C++11 version. As part of the changes, the FdMap class is pulled out
of the Process class and receives its own file.
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
syscall_emul: file descriptor interface changes
This patch gets rid of unused Process::dup_fd method and does minor
refactoring in the process class files. The file descriptor max has been
changed to be the number of file descriptors since this clarifies the loop
boundary condition and cleans up the code a bit. The fd_map field has been
altered to be dynamically allocated as opposed to being an array; the
intention here is to build on this is subsequent patches to allow processes
to share their file descriptors with the clone system call.
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
ruby: dma sequencer: removes redundant code
Nilay Vaish [Wed, 22 Jul 2015 16:20:07 +0000 (11:20 -0500)]
ruby: network: NetworkLink inherits from Consumer now.
Nilay Vaish [Tue, 21 Jul 2015 15:08:25 +0000 (10:08 -0500)]
configs: network test: remove redundant physical memory
Nilay Vaish [Sat, 18 Jul 2015 20:07:35 +0000 (15:07 -0500)]
stats: x86: updates due to patch on vex
Nilay Vaish [Fri, 17 Jul 2015 16:31:22 +0000 (11:31 -0500)]
x86: decode instructions with vex prefix
This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
Gabor Dozsa [Thu, 16 Jul 2015 00:53:50 +0000 (19:53 -0500)]
dev: add support for multi gem5 runs
Multi gem5 is an extension to gem5 to enable parallel simulation of a
distributed system (e.g. simulation of a pool of machines
connected by Ethernet links). A multi gem5 run consists of seperate gem5
processes running in parallel (potentially on different hosts/slots on
a cluster). Each gem5 process executes the simulation of a component of the
simulated distributed system (e.g. a multi-core board with an Ethernet NIC).
The patch implements the "distributed" Ethernet link device
(dev/src/multi_etherlink.[hh.cc]). This device will send/receive
(simulated) Ethernet packets to/from peer gem5 processes. The interface
to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and
in tcp_iface.hh.
There is also a central message server process (util/multi/tcp_server.[hh,cc])
which acts like an Ethernet switch and transfers messages among the gem5 peers.
A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh
wrapper script.
Checkpoints are supported by multi-gem5. The checkpoint must be
initiated by a single gem5 process. E.g., the gem5 process with rank 0
can take a checkpoint from the bootscript just before it invokes
'mpirun' to launch an MPI test. The message server process will notify
all the other peer gem5 processes and make them take a checkpoint, too
(after completing a global synchronisation to ensure that there are no
inflight messages among gem5).
Andreas Hansson [Mon, 13 Jul 2015 12:46:28 +0000 (08:46 -0400)]
mem: Fix (ab)use of emplace to avoid temporary object creation
Andreas Hansson [Mon, 13 Jul 2015 12:46:16 +0000 (08:46 -0400)]
mem: Updated DRAMSim2 wrapper to new drain API
Somehow this one slipped through without being updated.
Brandon Potter [Fri, 10 Jul 2015 21:05:24 +0000 (16:05 -0500)]
ruby: replace global g_abs_controls with per-RubySystem var
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.
The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.
Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: replace global g_system_ptr with per-object pointers
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.
With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: replace g_ruby_start with per-RubySystem m_start_cycle
This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.
This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: remove extra whitespace and correct misspelled words
Andreas Sandberg [Tue, 7 Jul 2015 09:03:14 +0000 (10:03 +0100)]
dev, arm: Add a device model that uses the NoMali model
Add a simple device shim that interfaces with the NoMali model
library. The gem5 side of the interface supports Mali T60x/T62x/T760
GPUs. This device model pretends to be a Mali GPU, but doesn't render
anything and executes in zero time.
Andreas Sandberg [Tue, 7 Jul 2015 09:03:13 +0000 (10:03 +0100)]
ext: Add the NoMali GPU no-simulation library
Add revision
9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model
from https://github.com/ARM-software/nomali-model. This library
implements the register interface of the Mali T6xx/T7xx series GPUs,
but doesn't do any rendering. It can be used to hide the effects of
software rendering.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after
decoupling draining from the SimObject hierarchy. This is expected
since objects aren't drained in the exact same order as before.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
sim: Refactor and simplify the drain API
The drain() call currently passes around a DrainManager pointer, which
is now completely pointless since there is only ever one global
DrainManager in the system. It also contains vestiges from the time
when SimObjects had to keep track of their child objects that needed
draining.
This changeset moves all of the DrainState handling to the Drainable
base class and changes the drain() and drainResume() calls to reflect
this. Particularly, the drain() call has been updated to take no
parameters (the DrainManager argument isn't needed) and return a
DrainState instead of an unsigned integer (there is no point returning
anything other than 0 or 1 any more). Drainable objects should return
either DrainState::Draining (equivalent to returning 1 in the old
system) if they need more time to drain or DrainState::Drained
(equivalent to returning 0 in the old system) if they are already in a
consistent state. Returning DrainState::Running is considered an
error.
Drain done signalling is now done through the signalDrainDone() method
in the Drainable class instead of using the DrainManager directly. The
new call checks if the state of the object is DrainState::Draining
before notifying the drain manager. This means that it is safe to call
signalDrainDone() without first checking if the simulator has
requested draining. The intention here is to reduce the code needed to
implement draining in simple objects.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
sim: Decouple draining from the SimObject hierarchy
Draining is currently done by traversing the SimObject graph and
calling drain()/drainResume() on the SimObjects. This is not ideal
when non-SimObjects (e.g., ports) need draining since this means that
SimObjects owning those objects need to be aware of this.
This changeset moves the responsibility for finding objects that need
draining from SimObjects and the Python-side of the simulator to the
DrainManager. The DrainManager now maintains a set of all objects that
need draining. To reduce the overhead in classes owning non-SimObjects
that need draining, objects inheriting from Drainable now
automatically register with the DrainManager. If such an object is
destroyed, it is automatically unregistered. This means that drain()
and drainResume() should never be called directly on a Drainable
object.
While implementing the new functionality, the DrainManager has now
been made thread safe. In practice, this means that it takes a lock
whenever it manipulates the set of Drainable objects since SimObjects
in different threads may create Drainable objects
dynamically. Similarly, the drain counter is now an atomic_uint, which
ensures that it is manipulated correctly when objects signal that they
are done draining.
A nice side effect of these changes is that it makes the drain state
changes stricter, which the simulation scripts can exploit to avoid
redundant drains.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Move mem(Writeback|Invalidate) to SimObject
The memWriteback() and memInvalidate() calls used to live in the
Serializable interface. In this series of patches, the Serializable
interface will be redesigned to make serialization independent of the
object graph and always work on the entire simulator. This means that
the Serialization interface won't be useful to perform maintenance of
the caches in a sub-graph of the entire SimObject graph. This
changeset moves these memory maintenance methods to the SimObject
interface instead.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Make the drain state a global typed enum
The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
python: Remove redundant drain when changing memory modes
When the Python helper code switches CPU models, it sometimes also
needs to change the memory mode of the simulator. When this happens,
it accidentally tried to drain the simulator despite having done so
already. This changeset removes the redundant drain.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Add macros to serialize objects into a section
Add the SERIALIZE_OBJ / UNSERIALIZE_OBJ macros that serialize an
object into a subsection of the current checkpoint section.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
base: Add serialization support to Pixels and FrameBuffer
Serialize pixels as unsigned 32 bit integers by adding the required
to_number() and stream operators. This is used by the FrameBuffer,
which now implements the Serializable interface. Users of frame
buffers are expected to serialize it into its own section by calling
serializeSection().
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Fix broken event unserialization
Events expected to be unserialized using an event-specific
unserializeEvent call. This call was never actually used, which meant
the events relying on it never got unserialized (or scheduled after
unserialization).
Instead of relying on a custom call, we now use the normal
serialization code again. In order to schedule the event correctly,
the parrent object is expected to use the
EventQueue::checkpointReschedule() call. This happens automatically
for events that are serialized using the AutoSerialize mechanism.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:03 +0000 (09:51 +0100)]
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.
* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).
* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.
* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:03 +0000 (09:51 +0100)]
tests: Skip SPARC tests if the required binaries are missing
The full-system SPARC tests depend on several binaries that aren't
generally available to the wider community. Flag the tests as skipped
instead of failed if these binaries can't be found.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:03 +0000 (09:51 +0100)]
sim: Add serialization macros for std containers
Andreas Sandberg [Mon, 6 Jul 2015 16:08:53 +0000 (17:08 +0100)]
mem: Cleanup CommMonitor in preparation for probe support
Make configuration parameters constant and get rid of an unnecessary
dependency on the Time class.
Nilay Vaish [Mon, 6 Jul 2015 01:26:18 +0000 (20:26 -0500)]
stats: x86: update stats missed out on in preivous changeset
Nilay Vaish [Sat, 4 Jul 2015 15:43:47 +0000 (10:43 -0500)]
stats: update stale config.ini files, eio and few other stats.
Nikos Nikoleris [Sat, 4 Jul 2015 15:43:47 +0000 (10:43 -0500)]
x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values
but in real hardware the size of some of these registers is smaller.
Previsouly all 64 bits where incorrectly set and then later read. To
ensure correctness we mask the value in setMiscRegNoEffect to write
only the valid bits.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
David Hashe [Sat, 4 Jul 2015 15:43:47 +0000 (10:43 -0500)]
config: Update location of ruby topologies in help
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
o3: correct the number of cc registers in rename map
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
mem: packet: Add const to constructor argument
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
ruby: drop NetworkMessage class
This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
ruby: mesi three level: name change to avoid clash
The accessor function getDestination() for Destination variable in the
coherence message clashes with the getDestination() that is part of the Message
class. Hence the name change.
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
ruby: remove message buffer node
This structure's only purpose was to provide a comparison function for
ordering messages in the MessageBuffer. The comparison function is now
being moved to the Message class itself. So we no longer require this
structure.
Andreas Hansson [Fri, 3 Jul 2015 14:15:03 +0000 (10:15 -0400)]
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Andreas Hansson [Fri, 3 Jul 2015 14:14:48 +0000 (10:14 -0400)]
mem: Increase the default buffer sizes for the DDR4 controller
This patch increases the default read/write buffer sizes for the DDR4
controller config to values that are more suitable for the high
bandwidth and high bank count.
Wendy Elsasser [Fri, 3 Jul 2015 14:14:46 +0000 (10:14 -0400)]
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
Andreas Hansson [Fri, 3 Jul 2015 14:14:45 +0000 (10:14 -0400)]
mem: Avoid DRAM write queue iteration for merging and read lookup
This patch adds a simple lookup structure to avoid iterating over the
write queue to find read matches, and for the merging of write
bursts. Instead of relying on iteration we simply store a set of
currently-buffered write-burst addresses and compare against
these. For the reads we still perform the iteration if we have a
match. For the writes, we rely entirely on the set. Note that there
are corner-cases where sub-bursts would actually not be mergeable
without a read-modify-write. We ignore these cases and opt for speed.
Andreas Hansson [Fri, 3 Jul 2015 14:14:44 +0000 (10:14 -0400)]
mem: Delay responses in the crossbar before forwarding
This patch changes how the crossbar classes deal with
responses. Instead of forwarding responses directly and burdening the
neighbouring modules in paying for the latency (through the
pkt->headerDelay), we now queue them before sending them.
The coherency protocol is not affected as requests and any snoop
requests/responses are still passed on in zero time. Thus, the
responses end up paying for any header delay accumulated when passing
through the crossbar. Any latency incurred on the request path will be
paid for on the response side, if no other module has dealt with it.
As a result of this patch, responses are returned at a later
point. This affects the number of outstanding transactions, and quite
a few regressions see an impact in blocking due to no MSHRs, increased
cache-miss latencies, etc.
Going forward we should be able to use the same concept also for snoop
responses, and any request that is not an express snoop.
Andreas Hansson [Fri, 3 Jul 2015 14:14:43 +0000 (10:14 -0400)]
mem: Remove redundant is_top_level cache parameter
This patch takes the final step in removing the is_top_level parameter
from the cache. With the recent changes to read requests and write
invalidations, the parameter is no longer needed, and consequently
removed.
This also means that asymmetric cache hierarchies are now fully
supported (and we are actually using them already with L1 caches, but
no table-walker caches, connected to a shared L2).
Andreas Hansson [Fri, 3 Jul 2015 14:14:41 +0000 (10:14 -0400)]
mem: Split WriteInvalidateReq into write and invalidate
WriteInvalidateReq ensures that a whole-line write does not incur the
cost of first doing a read exclusive, only to later overwrite the
data. This patch splits the existing WriteInvalidateReq into a
WriteLineReq, which is done locally, and an InvalidateReq that is sent
out throughout the memory system. The WriteLineReq re-uses the normal
WriteResp.
The change allows us to better express the difference between the
cache that is performing the write, and the ones that are merely
invalidating. As a consequence, we no longer have to rely on the
isTopLevel flag. Moreover, the actual memory in the system does not
see the intitial write, only the writeback. We were marking the
written line as dirty already, so there is really no need to also push
the write all the way to the memory.
The overall flow of the write-invalidate operation remains the same,
i.e. the operation is only carried out once the response for the
invalidate comes back. This patch adds the InvalidateResp for this
very reason.
Andreas Hansson [Fri, 3 Jul 2015 14:14:40 +0000 (10:14 -0400)]
mem: Add ReadCleanReq and ReadSharedReq packets
This patch adds two new read requests packets:
ReadCleanReq - For a cache to explicitly request clean data. The
response is thus exclusive or shared, but not owned or modified. The
read-only caches (see previous patch) use this request type to ensure
they do not get dirty data.
ReadSharedReq - We add this to distinguish cache read requests from
those issued by other masters, such as devices and CPUs. Thus, devices
use ReadReq, and caches use ReadCleanReq, ReadExReq, or
ReadSharedReq. For the latter, the response can be any state, shared,
exclusive, owned or even modified.
Both ReadCleanReq and ReadSharedReq re-use the normal ReadResp. The
two transactions are aligned with the emerging cache-coherent TLM
standard and the AMBA nomenclature.
With this change, the normal ReadReq should never be used by a cache,
and is reserved for the actual (non-caching) masters in the system. We
thus have a way of identifying if a request came from a cache or
not. The introduction of ReadSharedReq thus removes the need for the
current isTopLevel hack, and also allows us to stop relying on
checking the packet size to determine if the source is a cache or
not. This is fixed in follow-on patches.
Andreas Hansson [Fri, 3 Jul 2015 14:14:39 +0000 (10:14 -0400)]
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.
Ali Jafri [Fri, 3 Jul 2015 14:14:37 +0000 (10:14 -0400)]
mem: Add clean evicts to improve snoop filter tracking
This patch adds eviction notices to the caches, to provide accurate
tracking of cache blocks in snoop filters. We add the CleanEvict
message to the memory heirarchy and use both CleanEvicts and
Writebacks with BLOCK_CACHED flags to propagate notice of clean and
dirty evictions respectively, down the memory hierarchy. Note that the
BLOCK_CACHED flag indicates whether there exist any copies of the
evicted block in the caches above the evicting cache.
The purpose of the CleanEvict message is to notify snoop filters of
silent evictions in the relevant caches. The CleanEvict message
behaves much like a Writeback. CleanEvict is a write and a request but
unlike a Writeback, CleanEvict does not have data and does not need
exclusive access to the block. The cache generates the CleanEvict
message on a fill resulting in eviction of a clean block. Before
travelling downwards CleanEvict requests generate zero-time snoop
requests to check if the same block is cached in upper levels of the
memory heirarchy. If the block exists, the cache discards the
CleanEvict message. The snoops check the tags, writeback queue and the
MSHRs of upper level caches in a manner similar to snoops generated
from HardPFReqs. Currently CleanEvicts keep travelling towards main
memory unless they encounter the block corresponding to their address
or reach main memory (since we have no well defined point of
serialisation). Main memory simply discards CleanEvict messages.
We have modified the behavior of Writebacks, such that they generate
snoops to check for the presence of blocks in upper level caches. It
is possible in our current implmentation for a lower level cache to be
writing back a block while a shared copy of the same block exists in
the upper level cache. If the snoops find the same block in upper
level caches, we set the BLOCK_CACHED flag in the Writeback message.
We have also added logic to account for interaction of other message
types with CleanEvicts waiting in the writeback queue. A simple
example is of a response arriving at a cache removing any CleanEvicts
to the same address from the cache's writeback queue.
Andreas Hansson [Fri, 3 Jul 2015 14:14:36 +0000 (10:14 -0400)]
mem: Convert Request static const flags to enums
This patch fixes an issue which is very wide spread in the codebase,
causing sporadic linking failures. The issue is that we declare static
const class variables in the header, without any definition (as part
of a source file). In most cases the compiler propagates the value and
we have no issues. However, especially for less optimising builds such
as debug, we get sporadic linking failures due to undefined
references.
This patch fixes the Request class, by turning the static const flags
and master IDs into C++11 typed enums.
Curtis Dunham [Fri, 3 Jul 2015 14:14:35 +0000 (10:14 -0400)]
scons: remove dead leading underscore check
e56c3d8 (2008) added it but
8e37348 (2010) removed its only use.
Curtis Dunham [Fri, 3 Jul 2015 14:14:34 +0000 (10:14 -0400)]
base: remove fd from object loaders
All the object loaders directly examine the (already completely loaded
by object_file.cc) memory image. There is no current motivation to
keep the fd around.
Andreas Hansson [Fri, 3 Jul 2015 14:14:24 +0000 (10:14 -0400)]
util: Remove DRAMPower trace script
This script is deprecated and DRAMPower is now properly integrated
with the controller model.
Andreas Hansson [Fri, 3 Jul 2015 14:14:15 +0000 (10:14 -0400)]
scons: Bump compiler requirement to gcc >= 4.7 and clang >= 3.1
This patch updates the compiler minimum requirement to gcc 4.7 and
clang 3.1, thus allowing:
1. Explicit virtual overrides (no need for M5_ATTR_OVERRIDE)
2. Non-static data member initializers
3. Template aliases
4. Delegating constructors
This patch also enables a transition from --std=c++0x to --std=c++11.
Nilay Vaish [Thu, 25 Jun 2015 16:58:30 +0000 (11:58 -0500)]
ruby: slicc: remove README
No longer maintained. Updates are only made to the wiki page. So being
dropped.
Nilay Vaish [Thu, 25 Jun 2015 16:58:29 +0000 (11:58 -0500)]
ruby: message: remove a data member added by mistake
I (Nilay) had mistakenly added a data member to the Message class in revision
c1694b4032a6.
The data member is being removed.