Clifford Wolf [Wed, 22 May 2019 11:29:04 +0000 (13:29 +0200)]
Merge pull request #1019 from YosysHQ/clifford/fix1016
Add "wreduce -keepdc"
Clifford Wolf [Wed, 22 May 2019 10:01:19 +0000 (12:01 +0200)]
Merge pull request #1021 from ucb-bar/fixfirrtl_shr,neg
Fix static shift operands, neg result type, minor formatting
Eddie Hung [Wed, 22 May 2019 01:20:58 +0000 (18:20 -0700)]
Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces
Eddie Hung [Wed, 22 May 2019 01:20:31 +0000 (18:20 -0700)]
Rename label
Eddie Hung [Wed, 22 May 2019 00:20:19 +0000 (17:20 -0700)]
Try again
Eddie Hung [Tue, 21 May 2019 23:26:20 +0000 (16:26 -0700)]
Fix warning
Jim Lawson [Tue, 21 May 2019 20:04:56 +0000 (13:04 -0700)]
Fix static shift operands, neg result type, minor formatting
Static shift operands must be constants.
The result of FIRRTL's neg operator is signed.
Fix poor indentation for gen_read().
Jim Lawson [Tue, 21 May 2019 19:47:55 +0000 (12:47 -0700)]
Merge remote-tracking branch 'upstream/master'
Clifford Wolf [Mon, 20 May 2019 13:36:13 +0000 (15:36 +0200)]
Add "wreduce -keepdc", fixes #1016
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 18 May 2019 14:54:47 +0000 (16:54 +0200)]
Merge pull request #1017 from Kmanfi/bigger_verilog_files
Read bigger Verilog files.
Kaj Tuomi [Sat, 18 May 2019 11:20:30 +0000 (14:20 +0300)]
Read bigger Verilog files.
Hit parser limit with 3M gate design. This commit fix it.
Clifford Wolf [Thu, 16 May 2019 12:21:18 +0000 (14:21 +0200)]
Merge pull request #1013 from antmicro/parameter_attributes
Support for attributes on parameters and localparams for Verilog frontend
Maciej Kurc [Thu, 16 May 2019 10:53:43 +0000 (12:53 +0200)]
Added tests for Verilog frontent for attributes on parameters and localparams
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Maciej Kurc [Thu, 16 May 2019 10:44:16 +0000 (12:44 +0200)]
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Clifford Wolf [Wed, 15 May 2019 19:00:56 +0000 (21:00 +0200)]
Merge pull request #1012 from YosysHQ/clifford/sigspecrw
Another rounds of opt_clean improvements
Clifford Wolf [Wed, 15 May 2019 14:01:28 +0000 (16:01 +0200)]
Improvements in opt_clean
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 15 May 2019 14:01:00 +0000 (16:01 +0200)]
Add rewrite_sigspecs2, Improve remove() wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 15 May 2019 11:51:02 +0000 (13:51 +0200)]
Do not leak file descriptors in cover.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 15 May 2019 11:35:52 +0000 (13:35 +0200)]
Merge pull request #1011 from hzeller/fix-constructing-string-from-int
Fix two instances of integer-assignment to string.
Clifford Wolf [Wed, 15 May 2019 11:29:55 +0000 (13:29 +0200)]
Merge pull request #1010 from hzeller/yacc-self-contained
Make the generated *.tab.hh include all the headers needed
Clifford Wolf [Wed, 15 May 2019 11:28:52 +0000 (13:28 +0200)]
Merge pull request #1008 from thasti/fix_libyosys_build
Create $(LIBDIR) to fix broken build in isolated environments
David Shah [Wed, 15 May 2019 07:20:50 +0000 (08:20 +0100)]
Merge pull request #1005 from smunaut/ice40_hfosc_trim
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
Henner Zeller [Wed, 15 May 2019 05:01:15 +0000 (22:01 -0700)]
Fix two instances of integer-assignment to string.
o In cover.cc, the int-result of mkstemps() was assigned to a string
and silently interpreted as a single-character filename with a funny
value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
visible constructors, this is ambiguous. Explicitly cast this to
a char.
Henner Zeller [Wed, 15 May 2019 04:07:26 +0000 (21:07 -0700)]
Make the generated *.tab.hh include all the headers needed to define the union.
Stefan Biereigel [Tue, 14 May 2019 13:28:03 +0000 (15:28 +0200)]
extract python prefix to allow overriding
Stefan Biereigel [Tue, 14 May 2019 12:49:40 +0000 (14:49 +0200)]
remove ldconfig call
Stefan Biereigel [Tue, 14 May 2019 12:36:31 +0000 (14:36 +0200)]
add mkdir for libyosys target, explicitly copy to target folder
whitequark [Mon, 13 May 2019 16:55:15 +0000 (16:55 +0000)]
bugpoint: check for -script option.
Fixes #925.
Sylvain Munaut [Mon, 13 May 2019 10:51:06 +0000 (12:51 +0200)]
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Sun, 12 May 2019 13:33:53 +0000 (15:33 +0200)]
Merge pull request #1004 from YosysHQ/clifford/fix1002
Fix handling of glob_abort_cnt in opt_muxtree
Clifford Wolf [Sun, 12 May 2019 11:51:12 +0000 (13:51 +0200)]
Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 11 May 2019 11:56:51 +0000 (13:56 +0200)]
Merge pull request #1003 from makaimann/zinit-all
Zinit option '-singleton' -> '-all'
Clifford Wolf [Sat, 11 May 2019 07:28:55 +0000 (09:28 +0200)]
Add "fmcombine -initeq -anyeq"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 11 May 2019 07:24:52 +0000 (09:24 +0200)]
Add "stat -tech xilinx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Makai Mann [Fri, 10 May 2019 17:23:14 +0000 (10:23 -0700)]
Zinit option '-singleton' -> '-all'
Clifford Wolf [Thu, 9 May 2019 16:41:38 +0000 (18:41 +0200)]
Merge pull request #1000 from bwidawsk/synth-format
Add clang format, and use on intel_synth (v2)
Ben Widawsky [Sat, 4 May 2019 17:36:06 +0000 (10:36 -0700)]
Fix formatting for synth_intel.cc
This is realized through the recently added .clang-format file.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Sat, 4 May 2019 05:07:05 +0000 (22:07 -0700)]
Add a .clang-format
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Clifford Wolf [Thu, 9 May 2019 13:31:40 +0000 (15:31 +0200)]
Add $stop to documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Jakob Wenzel [Thu, 9 May 2019 10:37:31 +0000 (12:37 +0200)]
initialize more registers in setundef -init
Clifford Wolf [Wed, 8 May 2019 09:26:58 +0000 (11:26 +0200)]
Remove added newline (by re-running minisat 00_UPDATE.sh)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 8 May 2019 09:25:22 +0000 (11:25 +0200)]
Merge pull request #991 from kristofferkoch/gcc9-warnings
Fix all warnings that occurred when compiling with gcc9
Kristoffer Ellersgaard Koch [Sun, 5 May 2019 08:00:27 +0000 (10:00 +0200)]
Fix all warnings that occurred when compiling with gcc9
Clifford Wolf [Wed, 8 May 2019 06:34:35 +0000 (08:34 +0200)]
Merge pull request #998 from mdaiter/get_bool_attribute_opts
Minor optimization to get_attribute_bool
Matthew Daiter [Wed, 8 May 2019 03:04:28 +0000 (22:04 -0500)]
Minor optimization to get_attribute_bool
Clifford Wolf [Tue, 7 May 2019 17:58:04 +0000 (19:58 +0200)]
Add test case from #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 7 May 2019 17:55:36 +0000 (19:55 +0200)]
Fix handling of partial init attributes in write_verilog, fixes #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 7 May 2019 17:46:27 +0000 (19:46 +0200)]
Merge pull request #996 from mdaiter/ceil_log2_opts
Optimize ceil_log2 function
Matthew Daiter [Mon, 6 May 2019 23:33:56 +0000 (18:33 -0500)]
Optimize ceil_log2 function
Clifford Wolf [Tue, 7 May 2019 13:04:36 +0000 (15:04 +0200)]
Add "synth_xilinx -arch"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 7 May 2019 12:41:58 +0000 (14:41 +0200)]
More opt_clean cleanups
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 18:57:15 +0000 (20:57 +0200)]
Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
Clifford Wolf [Mon, 6 May 2019 18:53:38 +0000 (20:53 +0200)]
Merge pull request #975 from YosysHQ/clifford/fix968
Re-enable "final loop assignment" feature and fix opt_clean warnings
Clifford Wolf [Mon, 6 May 2019 18:51:59 +0000 (20:51 +0200)]
Merge pull request #871 from YosysHQ/verific_import
Improve verific -chparam and add hierarchy -chparam
Clifford Wolf [Mon, 6 May 2019 14:03:15 +0000 (16:03 +0200)]
Add tests/various/chparam.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 13:41:13 +0000 (15:41 +0200)]
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
Clifford Wolf [Mon, 6 May 2019 13:38:43 +0000 (15:38 +0200)]
Fix the other bison warning in ilang_parser.y
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 13:34:19 +0000 (15:34 +0200)]
Bugfix in peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 12:00:49 +0000 (14:00 +0200)]
Merge pull request #992 from bwidawsk/bison-fix
verilog_parser: Fix Bison warning
Clifford Wolf [Mon, 6 May 2019 11:57:35 +0000 (13:57 +0200)]
Merge pull request #989 from YosysHQ/dave/abc_name_improve
ABC name recovery fixes
Clifford Wolf [Mon, 6 May 2019 11:30:43 +0000 (13:30 +0200)]
Fix bug in "expose -input"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 10:45:22 +0000 (12:45 +0200)]
Cleanups in opt_clean
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 10:26:15 +0000 (12:26 +0200)]
Improve tests/various/specify.ys
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 10:00:40 +0000 (12:00 +0200)]
Add "real" keyword to ilang format
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 6 May 2019 09:46:10 +0000 (11:46 +0200)]
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
Ben Widawsky [Mon, 6 May 2019 02:29:11 +0000 (19:29 -0700)]
verilog_parser: Fix Bison warning
As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
%name-prefix "frontend_verilog_yy"
For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html
Compile tested only.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Clifford Wolf [Sat, 4 May 2019 19:58:25 +0000 (21:58 +0200)]
Merge pull request #988 from YosysHQ/clifford/fix987
Add approximate support for SV "var" keyword
David Shah [Sat, 4 May 2019 16:17:30 +0000 (17:17 +0100)]
abc: Fix handling of postfixed names (e.g. for retiming)
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Sat, 4 May 2019 15:53:25 +0000 (16:53 +0100)]
abc: Improve name recovery
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Sat, 4 May 2019 07:47:16 +0000 (09:47 +0200)]
Improve opt_clean handling of unused wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 4 May 2019 07:25:32 +0000 (09:25 +0200)]
Add support for SVA "final" keyword
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 4 May 2019 06:46:24 +0000 (08:46 +0200)]
Improve write_verilog specify support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 4 May 2019 06:01:39 +0000 (08:01 +0200)]
Update README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 4 May 2019 05:52:51 +0000 (07:52 +0200)]
Add approximate support for SV "var" keyword, fixes #987
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 3 May 2019 22:54:25 +0000 (15:54 -0700)]
More testing
Eddie Hung [Fri, 3 May 2019 22:42:02 +0000 (15:42 -0700)]
Fix spacing
Eddie Hung [Fri, 3 May 2019 22:35:26 +0000 (15:35 -0700)]
Add quick-and-dirty specify tests
Eddie Hung [Fri, 3 May 2019 22:05:57 +0000 (15:05 -0700)]
Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung [Fri, 3 May 2019 21:40:32 +0000 (14:40 -0700)]
Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung [Fri, 3 May 2019 21:03:51 +0000 (14:03 -0700)]
iverilog with simcells.v as well
Clifford Wolf [Fri, 3 May 2019 20:03:43 +0000 (22:03 +0200)]
Add "hierarchy -chparam" support for non-verific top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 14 Mar 2019 15:29:43 +0000 (15:29 +0000)]
log_warning_noprefix -> log_warning as per review
Eddie Hung [Wed, 13 Mar 2019 22:40:00 +0000 (22:40 +0000)]
For hier_tree::Elaborate() also include SV root modules (bind)
Eddie Hung [Wed, 13 Mar 2019 22:05:55 +0000 (22:05 +0000)]
Fix verific_parameters construction, use attribute to mark top netlists
Eddie Hung [Wed, 13 Mar 2019 19:42:18 +0000 (19:42 +0000)]
WIP -chparam support for hierarchy when verific
Eddie Hung [Wed, 13 Mar 2019 00:02:04 +0000 (00:02 +0000)]
verific_import() changes to avoid ElaborateAll()
Clifford Wolf [Fri, 3 May 2019 18:39:50 +0000 (20:39 +0200)]
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
Clifford Wolf [Fri, 3 May 2019 18:34:32 +0000 (20:34 +0200)]
Merge pull request #984 from YosysHQ/eddie/fix_982
dffinit to do nothing when (* init *) value is 1'bx
Eddie Hung [Fri, 3 May 2019 16:55:02 +0000 (09:55 -0700)]
Revert "synth_xilinx to call dffinit with -noreinit"
This reverts commit
1f62dc9081feb4852b1848d01951f631853edb38.
Eddie Hung [Fri, 3 May 2019 15:06:16 +0000 (08:06 -0700)]
If init is 1'bx, do not add to dict as per @cliffordwolf
Eddie Hung [Fri, 3 May 2019 15:05:37 +0000 (08:05 -0700)]
Revert "dffinit -noreinit to silently continue when init value is 1'bx"
This reverts commit
aa081f83c791b1d666214776aaf744a80ce6a690.
Clifford Wolf [Fri, 3 May 2019 13:29:44 +0000 (15:29 +0200)]
Merge pull request #976 from YosysHQ/clifford/fix974
Fix width detection of memory access with bit slice
Clifford Wolf [Fri, 3 May 2019 13:25:46 +0000 (15:25 +0200)]
Merge pull request #985 from YosysHQ/clifford/fix981
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
Clifford Wolf [Fri, 3 May 2019 12:40:51 +0000 (14:40 +0200)]
Fix typo in tests/svinterfaces/runone.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 12:37:46 +0000 (14:37 +0200)]
Merge pull request #979 from jakobwenzel/svinterfacesTestcase
fail svinterfaces testcases on yosys error exit
Clifford Wolf [Fri, 3 May 2019 12:24:53 +0000 (14:24 +0200)]
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 07:22:26 +0000 (09:22 +0200)]
Further improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 07:12:10 +0000 (09:12 +0200)]
Improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 06:35:45 +0000 (08:35 +0200)]
Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 3 May 2019 06:25:30 +0000 (08:25 +0200)]
Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>